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Merge pull request #2479 from zachjs/const-arg-hint
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/mem.h"
26 #include "kernel/log.h"
27
28 USING_YOSYS_NAMESPACE
29 PRIVATE_NAMESPACE_BEGIN
30
31 // [[CITE]]
32 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
33 // Information Processing Letters, Vol. 47, pp 319-323, 1993
34 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
35
36 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
37 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
38 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
39 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
40 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
41 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
42 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
43 template<class T>
44 struct Scheduler {
45 struct Vertex {
46 T *data;
47 Vertex *prev, *next;
48 pool<Vertex*, hash_ptr_ops> preds, succs;
49
50 Vertex() : data(NULL), prev(this), next(this) {}
51 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
52
53 bool empty() const
54 {
55 log_assert(data == NULL);
56 if (next == this) {
57 log_assert(prev == next);
58 return true;
59 }
60 return false;
61 }
62
63 void link(Vertex *list)
64 {
65 log_assert(prev == NULL && next == NULL);
66 next = list;
67 prev = list->prev;
68 list->prev->next = this;
69 list->prev = this;
70 }
71
72 void unlink()
73 {
74 log_assert(prev->next == this && next->prev == this);
75 prev->next = next;
76 next->prev = prev;
77 next = prev = NULL;
78 }
79
80 int delta() const
81 {
82 return succs.size() - preds.size();
83 }
84 };
85
86 std::vector<Vertex*> vertices;
87 Vertex *sources = new Vertex;
88 Vertex *sinks = new Vertex;
89 dict<int, Vertex*> bins;
90
91 ~Scheduler()
92 {
93 delete sources;
94 delete sinks;
95 for (auto bin : bins)
96 delete bin.second;
97 for (auto vertex : vertices)
98 delete vertex;
99 }
100
101 Vertex *add(T *data)
102 {
103 Vertex *vertex = new Vertex(data);
104 vertices.push_back(vertex);
105 return vertex;
106 }
107
108 void relink(Vertex *vertex)
109 {
110 if (vertex->succs.empty())
111 vertex->link(sinks);
112 else if (vertex->preds.empty())
113 vertex->link(sources);
114 else {
115 int delta = vertex->delta();
116 if (!bins.count(delta))
117 bins[delta] = new Vertex;
118 vertex->link(bins[delta]);
119 }
120 }
121
122 Vertex *remove(Vertex *vertex)
123 {
124 vertex->unlink();
125 for (auto pred : vertex->preds) {
126 if (pred == vertex)
127 continue;
128 log_assert(pred->succs[vertex]);
129 pred->unlink();
130 pred->succs.erase(vertex);
131 relink(pred);
132 }
133 for (auto succ : vertex->succs) {
134 if (succ == vertex)
135 continue;
136 log_assert(succ->preds[vertex]);
137 succ->unlink();
138 succ->preds.erase(vertex);
139 relink(succ);
140 }
141 vertex->preds.clear();
142 vertex->succs.clear();
143 return vertex;
144 }
145
146 std::vector<Vertex*> schedule()
147 {
148 std::vector<Vertex*> s1, s2r;
149 for (auto vertex : vertices)
150 relink(vertex);
151 bool bins_empty = false;
152 while (!(sinks->empty() && sources->empty() && bins_empty)) {
153 while (!sinks->empty())
154 s2r.push_back(remove(sinks->next));
155 while (!sources->empty())
156 s1.push_back(remove(sources->next));
157 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
158 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
159 // naive implementation of find-max-key.
160 bins_empty = true;
161 bins.template sort<std::greater<int>>();
162 for (auto bin : bins) {
163 if (!bin.second->empty()) {
164 bins_empty = false;
165 s1.push_back(remove(bin.second->next));
166 break;
167 }
168 }
169 }
170 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
171 return s1;
172 }
173 };
174
175 bool is_unary_cell(RTLIL::IdString type)
176 {
177 return type.in(
178 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
179 ID($pos), ID($neg));
180 }
181
182 bool is_binary_cell(RTLIL::IdString type)
183 {
184 return type.in(
185 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
186 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
187 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
188 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
189 }
190
191 bool is_extending_cell(RTLIL::IdString type)
192 {
193 return !type.in(
194 ID($logic_not), ID($logic_and), ID($logic_or),
195 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
196 }
197
198 bool is_inlinable_cell(RTLIL::IdString type)
199 {
200 return is_unary_cell(type) || is_binary_cell(type) || type.in(
201 ID($mux), ID($concat), ID($slice), ID($pmux));
202 }
203
204 bool is_ff_cell(RTLIL::IdString type)
205 {
206 return type.in(
207 ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
208 ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
209 ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
210 }
211
212 bool is_internal_cell(RTLIL::IdString type)
213 {
214 return !type.isPublic() && !type.begins_with("$paramod");
215 }
216
217 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
218 {
219 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
220 log_assert(cell_module != nullptr);
221 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
222 }
223
224 enum class CxxrtlPortType {
225 UNKNOWN = 0, // or mixed comb/sync
226 COMB = 1,
227 SYNC = 2,
228 };
229
230 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
231 {
232 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
233 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
234 return CxxrtlPortType::UNKNOWN;
235 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
236 log_assert(cell_output_wire != nullptr);
237 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
238 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
239 if (is_comb && is_sync)
240 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
241 log_id(cell_module), log_signal(cell_output_wire));
242 else if (is_comb)
243 return CxxrtlPortType::COMB;
244 else if (is_sync)
245 return CxxrtlPortType::SYNC;
246 return CxxrtlPortType::UNKNOWN;
247 }
248
249 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
250 {
251 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
252 }
253
254 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
255 {
256 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
257 }
258
259 struct FlowGraph {
260 struct Node {
261 enum class Type {
262 CONNECT,
263 CELL_SYNC,
264 CELL_EVAL,
265 PROCESS
266 };
267
268 Type type;
269 RTLIL::SigSig connect = {};
270 const RTLIL::Cell *cell = NULL;
271 const RTLIL::Process *process = NULL;
272 };
273
274 std::vector<Node*> nodes;
275 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
276 dict<const RTLIL::Wire*, bool> wire_def_inlinable, wire_use_inlinable;
277 dict<RTLIL::SigBit, bool> bit_has_state;
278
279 ~FlowGraph()
280 {
281 for (auto node : nodes)
282 delete node;
283 }
284
285 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool inlinable)
286 {
287 for (auto chunk : sig.chunks())
288 if (chunk.wire) {
289 if (is_ff) {
290 // A sync def means that a wire holds design state because it is driven directly by
291 // a flip-flop output. Such a wire can never be unbuffered.
292 wire_sync_defs[chunk.wire].insert(node);
293 } else {
294 // A comb def means that a wire doesn't hold design state. It might still be connected,
295 // indirectly, to a flip-flop output.
296 wire_comb_defs[chunk.wire].insert(node);
297 }
298 }
299 for (auto bit : sig.bits())
300 bit_has_state[bit] |= is_ff;
301 // Only comb defs of an entire wire in the right order can be inlined.
302 if (!is_ff && sig.is_wire())
303 wire_def_inlinable[sig.as_wire()] = inlinable;
304 }
305
306 void add_uses(Node *node, const RTLIL::SigSpec &sig)
307 {
308 for (auto chunk : sig.chunks())
309 if (chunk.wire) {
310 wire_uses[chunk.wire].insert(node);
311 // Only a single use of an entire wire in the right order can be inlined.
312 // (But the use can include other chunks.)
313 if (!wire_use_inlinable.count(chunk.wire))
314 wire_use_inlinable[chunk.wire] = true;
315 else
316 wire_use_inlinable[chunk.wire] = false;
317 }
318 }
319
320 bool is_inlinable(const RTLIL::Wire *wire) const
321 {
322 if (wire_def_inlinable.count(wire) && wire_use_inlinable.count(wire))
323 return wire_def_inlinable.at(wire) && wire_use_inlinable.at(wire);
324 return false;
325 }
326
327 // Connections
328 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
329 {
330 add_defs(node, conn.first, /*is_ff=*/false, /*inlinable=*/true);
331 add_uses(node, conn.second);
332 }
333
334 Node *add_node(const RTLIL::SigSig &conn)
335 {
336 Node *node = new Node;
337 node->type = Node::Type::CONNECT;
338 node->connect = conn;
339 nodes.push_back(node);
340 add_connect_defs_uses(node, conn);
341 return node;
342 }
343
344 // Cells
345 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
346 {
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
352 //
353 // wire<1> i_tmp;
354 // cell->p_i = i_tmp.curr;
355 // cell->eval();
356 // i_tmp.next = cell->p_o.curr;
357 //
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
361 //
362 // value<1> i_tmp;
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
365 // cell->eval();
366 //
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn : cell->connections())
374 if (cell->output(conn.first))
375 if (is_cxxrtl_sync_port(cell, conn.first)) {
376 // See note regarding inlinability below.
377 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
378 }
379 }
380
381 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
382 {
383 for (auto conn : cell->connections()) {
384 if (cell->output(conn.first)) {
385 if (is_inlinable_cell(cell->type))
386 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/true);
387 else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
388 add_defs(node, conn.second, /*is_ff=*/true, /*inlinable=*/false);
389 else if (is_internal_cell(cell->type))
390 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
391 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
392 // Although at first it looks like outputs of user-defined cells may always be inlined, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in inlining. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be inlined, but should be rare in practical designs and don't justify
396 // the infrastructure required to inline outputs of cells with many of them.
397 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
398 }
399 }
400 if (cell->input(conn.first))
401 add_uses(node, conn.second);
402 }
403 }
404
405 Node *add_node(const RTLIL::Cell *cell)
406 {
407 log_assert(cell->known());
408
409 bool has_fully_sync_outputs = false;
410 for (auto conn : cell->connections())
411 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
412 has_fully_sync_outputs = true;
413 break;
414 }
415 if (has_fully_sync_outputs) {
416 Node *node = new Node;
417 node->type = Node::Type::CELL_SYNC;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_sync_defs(node, cell);
421 }
422
423 Node *node = new Node;
424 node->type = Node::Type::CELL_EVAL;
425 node->cell = cell;
426 nodes.push_back(node);
427 add_cell_eval_defs_uses(node, cell);
428 return node;
429 }
430
431 // Processes
432 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
433 {
434 for (auto &action : case_->actions) {
435 add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
436 add_uses(node, action.second);
437 }
438 for (auto sub_switch : case_->switches) {
439 add_uses(node, sub_switch->signal);
440 for (auto sub_case : sub_switch->cases) {
441 for (auto &compare : sub_case->compare)
442 add_uses(node, compare);
443 add_case_defs_uses(node, sub_case);
444 }
445 }
446 }
447
448 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
449 {
450 add_case_defs_uses(node, &process->root_case);
451 for (auto sync : process->syncs)
452 for (auto action : sync->actions) {
453 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
454 add_defs(node, action.first, /*is_ff=*/true, /*inlinable=*/false);
455 else
456 add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
457 add_uses(node, action.second);
458 }
459 }
460
461 Node *add_node(const RTLIL::Process *process)
462 {
463 Node *node = new Node;
464 node->type = Node::Type::PROCESS;
465 node->process = process;
466 nodes.push_back(node);
467 add_process_defs_uses(node, process);
468 return node;
469 }
470 };
471
472 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
473 {
474 std::vector<std::string> result;
475 size_t prev = 0;
476 while (true) {
477 size_t curr = str.find_first_of(sep, prev);
478 if (curr == std::string::npos) {
479 std::string part = str.substr(prev);
480 if (!part.empty()) result.push_back(part);
481 break;
482 } else {
483 std::string part = str.substr(prev, curr - prev);
484 if (!part.empty()) result.push_back(part);
485 prev = curr + 1;
486 }
487 }
488 return result;
489 }
490
491 std::string escape_cxx_string(const std::string &input)
492 {
493 std::string output = "\"";
494 for (auto c : input) {
495 if (::isprint(c)) {
496 if (c == '\\')
497 output.push_back('\\');
498 output.push_back(c);
499 } else {
500 char l = c & 0xf, h = (c >> 4) & 0xf;
501 output.append("\\x");
502 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
503 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
504 }
505 }
506 output.push_back('"');
507 if (output.find('\0') != std::string::npos) {
508 output.insert(0, "std::string {");
509 output.append(stringf(", %zu}", input.size()));
510 }
511 return output;
512 }
513
514 template<class T>
515 std::string get_hdl_name(T *object)
516 {
517 if (object->has_attribute(ID::hdlname))
518 return object->get_string_attribute(ID::hdlname);
519 else
520 return object->name.str().substr(1);
521 }
522
523 struct CxxrtlWorker {
524 bool split_intf = false;
525 std::string intf_filename;
526 std::string design_ns = "cxxrtl_design";
527 std::ostream *impl_f = nullptr;
528 std::ostream *intf_f = nullptr;
529
530 bool run_hierarchy = false;
531 bool run_flatten = false;
532 bool run_proc = false;
533
534 bool unbuffer_internal = false;
535 bool unbuffer_public = false;
536 bool localize_internal = false;
537 bool localize_public = false;
538 bool inline_internal = false;
539 bool inline_public = false;
540
541 bool debug_info = false;
542 bool debug_alias = false;
543 bool debug_eval = false;
544
545 std::ostringstream f;
546 std::string indent;
547 int temporary = 0;
548
549 dict<const RTLIL::Module*, SigMap> sigmaps;
550 pool<const RTLIL::Wire*> edge_wires;
551 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
552 pool<const RTLIL::Memory*> writable_memories;
553 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
554 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
555 pool<const RTLIL::Wire*> unbuffered_wires;
556 pool<const RTLIL::Wire*> localized_wires;
557 dict<const RTLIL::Wire*, FlowGraph::Node> inlined_wires;
558 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
559 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
560 pool<const RTLIL::Wire*> debug_outlined_wires;
561 dict<RTLIL::SigBit, bool> bit_has_state;
562 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
563 dict<const RTLIL::Module*, bool> eval_converges;
564
565 void inc_indent() {
566 indent += "\t";
567 }
568 void dec_indent() {
569 indent.resize(indent.size() - 1);
570 }
571
572 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
573 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
574 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
575 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
576 // 1. All generated identifiers start with `_`.
577 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
578 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
579 // 2. An underscore is escaped with another underscore, i.e. `__`.
580 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
581 std::string mangle_name(const RTLIL::IdString &name)
582 {
583 std::string mangled;
584 bool first = true;
585 for (char c : name.str()) {
586 if (first) {
587 first = false;
588 if (c == '\\')
589 mangled += "p_";
590 else if (c == '$')
591 mangled += "i_";
592 else
593 log_assert(false);
594 } else {
595 if (isalnum(c)) {
596 mangled += c;
597 } else if (c == '_') {
598 mangled += "__";
599 } else {
600 char l = c & 0xf, h = (c >> 4) & 0xf;
601 mangled += '_';
602 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
603 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
604 mangled += '_';
605 }
606 }
607 }
608 return mangled;
609 }
610
611 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
612 {
613 // Class namespace.
614 if (is_blackbox)
615 return "bb_" + mangle_name(name);
616 return mangle_name(name);
617 }
618
619 std::string mangle_memory_name(const RTLIL::IdString &name)
620 {
621 // Class member namespace.
622 return "memory_" + mangle_name(name);
623 }
624
625 std::string mangle_cell_name(const RTLIL::IdString &name)
626 {
627 // Class member namespace.
628 return "cell_" + mangle_name(name);
629 }
630
631 std::string mangle_wire_name(const RTLIL::IdString &name)
632 {
633 // Class member namespace.
634 return mangle_name(name);
635 }
636
637 std::string mangle(const RTLIL::Module *module)
638 {
639 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
640 }
641
642 std::string mangle(const RTLIL::Memory *memory)
643 {
644 return mangle_memory_name(memory->name);
645 }
646
647 std::string mangle(const RTLIL::Cell *cell)
648 {
649 return mangle_cell_name(cell->name);
650 }
651
652 std::string mangle(const RTLIL::Wire *wire)
653 {
654 return mangle_wire_name(wire->name);
655 }
656
657 std::string mangle(RTLIL::SigBit sigbit)
658 {
659 log_assert(sigbit.wire != NULL);
660 if (sigbit.wire->width == 1)
661 return mangle(sigbit.wire);
662 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
663 }
664
665 std::vector<std::string> template_param_names(const RTLIL::Module *module)
666 {
667 if (!module->has_attribute(ID(cxxrtl_template)))
668 return {};
669
670 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
671 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
672
673 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
674 for (const auto &param_name : param_names) {
675 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
676 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
677 // in both Verilog and C++, anyway.)
678 if (!isupper(param_name[0]))
679 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
680 "which does not start with an uppercase letter.\n",
681 log_id(module), param_name.c_str());
682 }
683 return param_names;
684 }
685
686 std::string template_params(const RTLIL::Module *module, bool is_decl)
687 {
688 std::vector<std::string> param_names = template_param_names(module);
689 if (param_names.empty())
690 return "";
691
692 std::string params = "<";
693 bool first = true;
694 for (const auto &param_name : param_names) {
695 if (!first)
696 params += ", ";
697 first = false;
698 if (is_decl)
699 params += "size_t ";
700 params += param_name;
701 }
702 params += ">";
703 return params;
704 }
705
706 std::string template_args(const RTLIL::Cell *cell)
707 {
708 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
709 log_assert(cell_module != nullptr);
710 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
711 return "";
712
713 std::vector<std::string> param_names = template_param_names(cell_module);
714 if (param_names.empty())
715 return "";
716
717 std::string params = "<";
718 bool first = true;
719 for (const auto &param_name : param_names) {
720 if (!first)
721 params += ", ";
722 first = false;
723 params += "/*" + param_name + "=*/";
724 RTLIL::IdString id_param_name = '\\' + param_name;
725 if (!cell->hasParam(id_param_name))
726 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
727 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
728 RTLIL::Const param_value = cell->getParam(id_param_name);
729 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
730 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
731 "is not a positive integer.\n",
732 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
733 params += std::to_string(cell->getParam(id_param_name).as_int());
734 }
735 params += ">";
736 return params;
737 }
738
739 std::string fresh_temporary()
740 {
741 return stringf("tmp_%d", temporary++);
742 }
743
744 void dump_attrs(const RTLIL::AttrObject *object)
745 {
746 for (auto attr : object->attributes) {
747 f << indent << "// " << attr.first.str() << ": ";
748 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
749 f << attr.second.decode_string();
750 } else {
751 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
752 }
753 f << "\n";
754 }
755 }
756
757 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
758 {
759 const int CHUNK_SIZE = 32;
760 f << "{";
761 while (width > 0) {
762 int chunk_width = min(width, CHUNK_SIZE);
763 uint32_t chunk = data.extract(offset, chunk_width).as_int();
764 if (fixed_width)
765 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
766 else
767 f << stringf("%#xu", chunk);
768 if (width > CHUNK_SIZE)
769 f << ',';
770 offset += CHUNK_SIZE;
771 width -= CHUNK_SIZE;
772 }
773 f << "}";
774 }
775
776 void dump_const_init(const RTLIL::Const &data)
777 {
778 dump_const_init(data, data.size());
779 }
780
781 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
782 {
783 f << "value<" << width << ">";
784 dump_const_init(data, width, offset, fixed_width);
785 }
786
787 void dump_const(const RTLIL::Const &data)
788 {
789 dump_const(data, data.size());
790 }
791
792 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs, bool for_debug = false)
793 {
794 if (chunk.wire == NULL) {
795 dump_const(chunk.data, chunk.width, chunk.offset);
796 return false;
797 } else {
798 if (inlined_wires.count(chunk.wire) && (!for_debug || !debug_outlined_wires[chunk.wire])) {
799 log_assert(!is_lhs);
800 const FlowGraph::Node &node = inlined_wires[chunk.wire];
801 switch (node.type) {
802 case FlowGraph::Node::Type::CONNECT:
803 dump_connect_expr(node.connect, for_debug);
804 break;
805 case FlowGraph::Node::Type::CELL_EVAL:
806 log_assert(is_inlinable_cell(node.cell->type));
807 dump_cell_expr(node.cell, for_debug);
808 break;
809 default:
810 log_assert(false);
811 }
812 } else if (unbuffered_wires[chunk.wire]) {
813 f << mangle(chunk.wire);
814 } else {
815 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
816 }
817 if (chunk.width == chunk.wire->width && chunk.offset == 0)
818 return false;
819 else if (chunk.width == 1)
820 f << ".slice<" << chunk.offset << ">()";
821 else
822 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
823 return true;
824 }
825 }
826
827 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs, bool for_debug = false)
828 {
829 if (sig.empty()) {
830 f << "value<0>()";
831 return false;
832 } else if (sig.is_chunk()) {
833 return dump_sigchunk(sig.as_chunk(), is_lhs, for_debug);
834 } else {
835 bool first = true;
836 auto chunks = sig.chunks();
837 for (auto it = chunks.rbegin(); it != chunks.rend(); it++) {
838 if (!first)
839 f << ".concat(";
840 bool is_complex = dump_sigchunk(*it, is_lhs, for_debug);
841 if (!is_lhs && it->width == 1) {
842 size_t repeat = 1;
843 while ((it + repeat) != chunks.rend() && *(it + repeat) == *it)
844 repeat++;
845 if (repeat > 1) {
846 if (is_complex)
847 f << ".val()";
848 f << ".repeat<" << repeat << ">()";
849 }
850 it += repeat - 1;
851 }
852 if (!first)
853 f << ")";
854 first = false;
855 }
856 return true;
857 }
858 }
859
860 void dump_sigspec_lhs(const RTLIL::SigSpec &sig, bool for_debug = false)
861 {
862 dump_sigspec(sig, /*is_lhs=*/true, for_debug);
863 }
864
865 void dump_sigspec_rhs(const RTLIL::SigSpec &sig, bool for_debug = false)
866 {
867 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
868 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
869 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
870 // type conversion, but only if the expression needs it.
871 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false, for_debug);
872 if (is_complex)
873 f << ".val()";
874 }
875
876 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
877 {
878 for (auto chunk : sig.chunks()) {
879 if (!chunk.wire || !inlined_wires.count(chunk.wire))
880 continue;
881
882 const FlowGraph::Node &node = inlined_wires[chunk.wire];
883 switch (node.type) {
884 case FlowGraph::Node::Type::CONNECT:
885 collect_connect(node.connect, cells);
886 break;
887 case FlowGraph::Node::Type::CELL_EVAL:
888 collect_cell_eval(node.cell, cells);
889 break;
890 default:
891 log_assert(false);
892 }
893 }
894 }
895
896 void dump_connect_expr(const RTLIL::SigSig &conn, bool for_debug = false)
897 {
898 dump_sigspec_rhs(conn.second, for_debug);
899 }
900
901 bool is_connect_inlined(const RTLIL::SigSig &conn)
902 {
903 return conn.first.is_wire() && inlined_wires.count(conn.first.as_wire());
904 }
905
906 bool is_connect_outlined(const RTLIL::SigSig &conn)
907 {
908 for (auto chunk : conn.first.chunks())
909 if (debug_outlined_wires.count(chunk.wire))
910 return true;
911 return false;
912 }
913
914 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
915 {
916 if (!is_connect_inlined(conn))
917 return;
918
919 collect_sigspec_rhs(conn.second, cells);
920 }
921
922 void dump_connect(const RTLIL::SigSig &conn, bool for_debug = false)
923 {
924 if (!for_debug && is_connect_inlined(conn))
925 return;
926 if (for_debug && !is_connect_outlined(conn))
927 return;
928
929 std::vector<RTLIL::IdString> inlined_cells;
930 collect_sigspec_rhs(conn.second, inlined_cells);
931 if (for_debug || inlined_cells.empty()) {
932 f << indent << "// connection\n";
933 } else {
934 f << indent << "// cells";
935 for (auto inlined_cell : inlined_cells)
936 f << " " << inlined_cell.str();
937 f << "\n";
938 }
939 f << indent;
940 dump_sigspec_lhs(conn.first, for_debug);
941 f << " = ";
942 dump_connect_expr(conn, for_debug);
943 f << ";\n";
944 }
945
946 void dump_cell_sync(const RTLIL::Cell *cell)
947 {
948 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
949 f << indent << "// cell " << cell->name.str() << " syncs\n";
950 for (auto conn : cell->connections())
951 if (cell->output(conn.first))
952 if (is_cxxrtl_sync_port(cell, conn.first)) {
953 f << indent;
954 dump_sigspec_lhs(conn.second);
955 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
956 }
957 }
958
959 void dump_cell_expr(const RTLIL::Cell *cell, bool for_debug = false)
960 {
961 // Unary cells
962 if (is_unary_cell(cell->type)) {
963 f << cell->type.substr(1);
964 if (is_extending_cell(cell->type))
965 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
966 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
967 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
968 f << ")";
969 // Binary cells
970 } else if (is_binary_cell(cell->type)) {
971 f << cell->type.substr(1);
972 if (is_extending_cell(cell->type))
973 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
974 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
975 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
976 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
977 f << ", ";
978 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
979 f << ")";
980 // Muxes
981 } else if (cell->type == ID($mux)) {
982 f << "(";
983 dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
984 f << " ? ";
985 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
986 f << " : ";
987 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
988 f << ")";
989 // Parallel (one-hot) muxes
990 } else if (cell->type == ID($pmux)) {
991 int width = cell->getParam(ID::WIDTH).as_int();
992 int s_width = cell->getParam(ID::S_WIDTH).as_int();
993 for (int part = 0; part < s_width; part++) {
994 f << "(";
995 dump_sigspec_rhs(cell->getPort(ID::S).extract(part), for_debug);
996 f << " ? ";
997 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width), for_debug);
998 f << " : ";
999 }
1000 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
1001 for (int part = 0; part < s_width; part++) {
1002 f << ")";
1003 }
1004 // Concats
1005 } else if (cell->type == ID($concat)) {
1006 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
1007 f << ".concat(";
1008 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
1009 f << ").val()";
1010 // Slices
1011 } else if (cell->type == ID($slice)) {
1012 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
1013 f << ".slice<";
1014 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
1015 f << ",";
1016 f << cell->getParam(ID::OFFSET).as_int();
1017 f << ">().val()";
1018 } else {
1019 log_assert(false);
1020 }
1021 }
1022
1023 bool is_cell_inlined(const RTLIL::Cell *cell)
1024 {
1025 return is_inlinable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
1026 inlined_wires.count(cell->getPort(ID::Y).as_wire());
1027 }
1028
1029 bool is_cell_outlined(const RTLIL::Cell *cell)
1030 {
1031 if (is_internal_cell(cell->type))
1032 for (auto conn : cell->connections())
1033 if (cell->output(conn.first))
1034 for (auto chunk : conn.second.chunks())
1035 if (debug_outlined_wires.count(chunk.wire))
1036 return true;
1037 return false;
1038 }
1039
1040 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
1041 {
1042 if (!is_cell_inlined(cell))
1043 return;
1044
1045 cells.push_back(cell->name);
1046 for (auto port : cell->connections())
1047 if (port.first != ID::Y)
1048 collect_sigspec_rhs(port.second, cells);
1049 }
1050
1051 void dump_cell_eval(const RTLIL::Cell *cell, bool for_debug = false)
1052 {
1053 if (!for_debug && is_cell_inlined(cell))
1054 return;
1055 if (for_debug && !is_cell_outlined(cell))
1056 return;
1057 if (cell->type == ID($meminit))
1058 return; // Handled elsewhere.
1059
1060 std::vector<RTLIL::IdString> inlined_cells;
1061 if (is_inlinable_cell(cell->type)) {
1062 for (auto port : cell->connections())
1063 if (port.first != ID::Y)
1064 collect_sigspec_rhs(port.second, inlined_cells);
1065 }
1066 if (inlined_cells.empty()) {
1067 dump_attrs(cell);
1068 f << indent << "// cell " << cell->name.str() << "\n";
1069 } else {
1070 f << indent << "// cells";
1071 for (auto inlined_cell : inlined_cells)
1072 f << " " << inlined_cell.str();
1073 f << "\n";
1074 }
1075
1076 // Elidable cells
1077 if (is_inlinable_cell(cell->type)) {
1078 f << indent;
1079 dump_sigspec_lhs(cell->getPort(ID::Y), for_debug);
1080 f << " = ";
1081 dump_cell_expr(cell, for_debug);
1082 f << ";\n";
1083 // Flip-flops
1084 } else if (is_ff_cell(cell->type)) {
1085 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1086 // Edge-sensitive logic
1087 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1088 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1089 if (clk_bit.wire) {
1090 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1091 << mangle(clk_bit) << ") {\n";
1092 } else {
1093 f << indent << "if (false) {\n";
1094 }
1095 inc_indent();
1096 if (cell->hasPort(ID::EN)) {
1097 f << indent << "if (";
1098 dump_sigspec_rhs(cell->getPort(ID::EN));
1099 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1100 inc_indent();
1101 }
1102 f << indent;
1103 dump_sigspec_lhs(cell->getPort(ID::Q));
1104 f << " = ";
1105 dump_sigspec_rhs(cell->getPort(ID::D));
1106 f << ";\n";
1107 if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
1108 dec_indent();
1109 f << indent << "}\n";
1110 }
1111 if (cell->hasPort(ID::SRST)) {
1112 f << indent << "if (";
1113 dump_sigspec_rhs(cell->getPort(ID::SRST));
1114 f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
1115 inc_indent();
1116 f << indent;
1117 dump_sigspec_lhs(cell->getPort(ID::Q));
1118 f << " = ";
1119 dump_const(cell->getParam(ID::SRST_VALUE));
1120 f << ";\n";
1121 dec_indent();
1122 f << indent << "}\n";
1123 }
1124 if (cell->hasPort(ID::EN) && cell->type == ID($sdffce)) {
1125 dec_indent();
1126 f << indent << "}\n";
1127 }
1128 dec_indent();
1129 f << indent << "}\n";
1130 } else if (cell->hasPort(ID::EN)) {
1131 // Level-sensitive logic
1132 f << indent << "if (";
1133 dump_sigspec_rhs(cell->getPort(ID::EN));
1134 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1135 inc_indent();
1136 f << indent;
1137 dump_sigspec_lhs(cell->getPort(ID::Q));
1138 f << " = ";
1139 dump_sigspec_rhs(cell->getPort(ID::D));
1140 f << ";\n";
1141 dec_indent();
1142 f << indent << "}\n";
1143 }
1144 if (cell->hasPort(ID::ARST)) {
1145 // Asynchronous reset (entire coarse cell at once)
1146 f << indent << "if (";
1147 dump_sigspec_rhs(cell->getPort(ID::ARST));
1148 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1149 inc_indent();
1150 f << indent;
1151 dump_sigspec_lhs(cell->getPort(ID::Q));
1152 f << " = ";
1153 dump_const(cell->getParam(ID::ARST_VALUE));
1154 f << ";\n";
1155 dec_indent();
1156 f << indent << "}\n";
1157 }
1158 if (cell->hasPort(ID::SET)) {
1159 // Asynchronous set (for individual bits)
1160 f << indent;
1161 dump_sigspec_lhs(cell->getPort(ID::Q));
1162 f << " = ";
1163 dump_sigspec_lhs(cell->getPort(ID::Q));
1164 f << ".update(";
1165 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1166 f << ", ";
1167 dump_sigspec_rhs(cell->getPort(ID::SET));
1168 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1169 }
1170 if (cell->hasPort(ID::CLR)) {
1171 // Asynchronous clear (for individual bits; priority over set)
1172 f << indent;
1173 dump_sigspec_lhs(cell->getPort(ID::Q));
1174 f << " = ";
1175 dump_sigspec_lhs(cell->getPort(ID::Q));
1176 f << ".update(";
1177 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1178 f << ", ";
1179 dump_sigspec_rhs(cell->getPort(ID::CLR));
1180 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1181 }
1182 // Memory ports
1183 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1184 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1185 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1186 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1187 if (clk_bit.wire) {
1188 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1189 << mangle(clk_bit) << ") {\n";
1190 } else {
1191 f << indent << "if (false) {\n";
1192 }
1193 inc_indent();
1194 }
1195 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1196 std::string valid_index_temp = fresh_temporary();
1197 f << indent << "auto " << valid_index_temp << " = memory_index(";
1198 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1199 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1200 if (cell->type == ID($memrd)) {
1201 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1202 if (has_enable) {
1203 f << indent << "if (";
1204 dump_sigspec_rhs(cell->getPort(ID::EN));
1205 f << ") {\n";
1206 inc_indent();
1207 }
1208 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1209 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1210 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DCXXRTL_NDEBUG
1211 // not only for release builds, but also to make sure the simulator (which is presumably embedded in some
1212 // larger program) will never crash the code that calls into it.
1213 //
1214 // If assertions are disabled, out of bounds reads are defined to return zero.
1215 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1216 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1217 inc_indent();
1218 if (writable_memories[memory]) {
1219 std::string lhs_temp = fresh_temporary();
1220 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1221 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1222 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1223 if (!memwr_cells.empty()) {
1224 std::string addr_temp = fresh_temporary();
1225 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1226 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1227 f << ";\n";
1228 std::sort(memwr_cells.begin(), memwr_cells.end(),
1229 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1230 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1231 });
1232 for (auto memwr_cell : memwr_cells) {
1233 f << indent << "if (" << addr_temp << " == ";
1234 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1235 f << ") {\n";
1236 inc_indent();
1237 f << indent << lhs_temp << " = " << lhs_temp;
1238 f << ".update(";
1239 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1240 f << ", ";
1241 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1242 f << ");\n";
1243 dec_indent();
1244 f << indent << "}\n";
1245 }
1246 }
1247 f << indent;
1248 dump_sigspec_lhs(cell->getPort(ID::DATA));
1249 f << " = " << lhs_temp << ";\n";
1250 } else {
1251 f << indent;
1252 dump_sigspec_lhs(cell->getPort(ID::DATA));
1253 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1254 }
1255 dec_indent();
1256 f << indent << "} else {\n";
1257 inc_indent();
1258 f << indent;
1259 dump_sigspec_lhs(cell->getPort(ID::DATA));
1260 f << " = value<" << memory->width << "> {};\n";
1261 dec_indent();
1262 f << indent << "}\n";
1263 if (has_enable) {
1264 dec_indent();
1265 f << indent << "}\n";
1266 }
1267 } else /*if (cell->type == ID($memwr))*/ {
1268 log_assert(writable_memories[memory]);
1269 // See above for rationale of having both the assert and the condition.
1270 //
1271 // If assertions are disabled, out of bounds writes are defined to do nothing.
1272 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1273 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1274 inc_indent();
1275 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1276 dump_sigspec_rhs(cell->getPort(ID::DATA));
1277 f << ", ";
1278 dump_sigspec_rhs(cell->getPort(ID::EN));
1279 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1280 dec_indent();
1281 f << indent << "}\n";
1282 }
1283 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1284 dec_indent();
1285 f << indent << "}\n";
1286 }
1287 // Internal cells
1288 } else if (is_internal_cell(cell->type)) {
1289 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1290 // User cells
1291 } else {
1292 log_assert(cell->known());
1293 bool buffered_inputs = false;
1294 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1295 for (auto conn : cell->connections())
1296 if (cell->input(conn.first)) {
1297 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1298 log_assert(cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire());
1299 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1300 f << indent << mangle(cell) << access << mangle_wire_name(conn.first);
1301 if (!is_cxxrtl_blackbox_cell(cell) && !unbuffered_wires[cell_module_wire]) {
1302 buffered_inputs = true;
1303 f << ".next";
1304 }
1305 f << " = ";
1306 dump_sigspec_rhs(conn.second);
1307 f << ";\n";
1308 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1309 // Until we have proper clock tree detection, this really awful hack that opportunistically
1310 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1311 // be if only one clock edge was simulated by replacing:
1312 // top.p_clk = value<1>{0u}; top.step();
1313 // top.p_clk = value<1>{1u}; top.step();
1314 // with:
1315 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1316 // Don't rely on this; it will be removed without warning.
1317 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1318 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1319 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1320 }
1321 }
1322 }
1323 auto assign_from_outputs = [&](bool cell_converged) {
1324 for (auto conn : cell->connections()) {
1325 if (cell->output(conn.first)) {
1326 if (conn.second.empty())
1327 continue; // ignore disconnected ports
1328 if (is_cxxrtl_sync_port(cell, conn.first))
1329 continue; // fully sync ports are handled in CELL_SYNC nodes
1330 f << indent;
1331 dump_sigspec_lhs(conn.second);
1332 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1333 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1334 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1335 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1336 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1337 // and consider the fate of the localized wires that used to be output ports.)
1338 //
1339 // It is not possible to know apriori whether the cell (which may be late bound) will converge immediately.
1340 // Because of this, the choice between using .curr (appropriate for buffered outputs) and .next (appropriate
1341 // for unbuffered outputs) is made at runtime.
1342 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1343 f << ".next;\n";
1344 else
1345 f << ".curr;\n";
1346 }
1347 }
1348 };
1349 if (buffered_inputs) {
1350 // If we have any buffered inputs, there's no chance of converging immediately.
1351 f << indent << mangle(cell) << access << "eval();\n";
1352 f << indent << "converged = false;\n";
1353 assign_from_outputs(/*cell_converged=*/false);
1354 } else {
1355 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1356 inc_indent();
1357 assign_from_outputs(/*cell_converged=*/true);
1358 dec_indent();
1359 f << indent << "} else {\n";
1360 inc_indent();
1361 f << indent << "converged = false;\n";
1362 assign_from_outputs(/*cell_converged=*/false);
1363 dec_indent();
1364 f << indent << "}\n";
1365 }
1366 }
1367 }
1368
1369 void dump_assign(const RTLIL::SigSig &sigsig)
1370 {
1371 f << indent;
1372 dump_sigspec_lhs(sigsig.first);
1373 f << " = ";
1374 dump_sigspec_rhs(sigsig.second);
1375 f << ";\n";
1376 }
1377
1378 void dump_case_rule(const RTLIL::CaseRule *rule)
1379 {
1380 for (auto action : rule->actions)
1381 dump_assign(action);
1382 for (auto switch_ : rule->switches)
1383 dump_switch_rule(switch_);
1384 }
1385
1386 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1387 {
1388 // The switch attributes are printed before the switch condition is captured.
1389 dump_attrs(rule);
1390 std::string signal_temp = fresh_temporary();
1391 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1392 dump_sigspec(rule->signal, /*is_lhs=*/false);
1393 f << ";\n";
1394
1395 bool first = true;
1396 for (auto case_ : rule->cases) {
1397 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1398 dump_attrs(rule);
1399 f << indent;
1400 if (!first)
1401 f << "} else ";
1402 first = false;
1403 if (!case_->compare.empty()) {
1404 f << "if (";
1405 bool first = true;
1406 for (auto &compare : case_->compare) {
1407 if (!first)
1408 f << " || ";
1409 first = false;
1410 if (compare.is_fully_def()) {
1411 f << signal_temp << " == ";
1412 dump_sigspec(compare, /*is_lhs=*/false);
1413 } else if (compare.is_fully_const()) {
1414 RTLIL::Const compare_mask, compare_value;
1415 for (auto bit : compare.as_const()) {
1416 switch (bit) {
1417 case RTLIL::S0:
1418 case RTLIL::S1:
1419 compare_mask.bits.push_back(RTLIL::S1);
1420 compare_value.bits.push_back(bit);
1421 break;
1422
1423 case RTLIL::Sx:
1424 case RTLIL::Sz:
1425 case RTLIL::Sa:
1426 compare_mask.bits.push_back(RTLIL::S0);
1427 compare_value.bits.push_back(RTLIL::S0);
1428 break;
1429
1430 default:
1431 log_assert(false);
1432 }
1433 }
1434 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1435 dump_const(compare_mask);
1436 f << ") == ";
1437 dump_const(compare_value);
1438 } else {
1439 log_assert(false);
1440 }
1441 }
1442 f << ") ";
1443 }
1444 f << "{\n";
1445 inc_indent();
1446 dump_case_rule(case_);
1447 dec_indent();
1448 }
1449 f << indent << "}\n";
1450 }
1451
1452 void dump_process(const RTLIL::Process *proc)
1453 {
1454 dump_attrs(proc);
1455 f << indent << "// process " << proc->name.str() << "\n";
1456 // The case attributes (for root case) are always empty.
1457 log_assert(proc->root_case.attributes.empty());
1458 dump_case_rule(&proc->root_case);
1459 for (auto sync : proc->syncs) {
1460 RTLIL::SigBit sync_bit;
1461 if (!sync->signal.empty()) {
1462 sync_bit = sync->signal[0];
1463 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1464 }
1465
1466 pool<std::string> events;
1467 switch (sync->type) {
1468 case RTLIL::STp:
1469 log_assert(sync_bit.wire != nullptr);
1470 events.insert("posedge_" + mangle(sync_bit));
1471 break;
1472 case RTLIL::STn:
1473 log_assert(sync_bit.wire != nullptr);
1474 events.insert("negedge_" + mangle(sync_bit));
1475 break;
1476 case RTLIL::STe:
1477 log_assert(sync_bit.wire != nullptr);
1478 events.insert("posedge_" + mangle(sync_bit));
1479 events.insert("negedge_" + mangle(sync_bit));
1480 break;
1481
1482 case RTLIL::STa:
1483 events.insert("true");
1484 break;
1485
1486 case RTLIL::ST0:
1487 case RTLIL::ST1:
1488 case RTLIL::STg:
1489 case RTLIL::STi:
1490 log_assert(false);
1491 }
1492 if (!events.empty()) {
1493 f << indent << "if (";
1494 bool first = true;
1495 for (auto &event : events) {
1496 if (!first)
1497 f << " || ";
1498 first = false;
1499 f << event;
1500 }
1501 f << ") {\n";
1502 inc_indent();
1503 for (auto action : sync->actions)
1504 dump_assign(action);
1505 dec_indent();
1506 f << indent << "}\n";
1507 }
1508 }
1509 }
1510
1511 void dump_wire(const RTLIL::Wire *wire, bool is_local)
1512 {
1513 if (is_local && localized_wires[wire] && !inlined_wires.count(wire)) {
1514 dump_attrs(wire);
1515 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1516 }
1517 if (!is_local && !localized_wires[wire]) {
1518 std::string width;
1519 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1520 width = wire->get_string_attribute(ID(cxxrtl_width));
1521 } else {
1522 width = std::to_string(wire->width);
1523 }
1524
1525 dump_attrs(wire);
1526 f << indent;
1527 if (wire->port_input && wire->port_output)
1528 f << "/*inout*/ ";
1529 else if (wire->port_input)
1530 f << "/*input*/ ";
1531 else if (wire->port_output)
1532 f << "/*output*/ ";
1533 f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1534 if (wire->has_attribute(ID::init)) {
1535 f << " ";
1536 dump_const_init(wire->attributes.at(ID::init));
1537 }
1538 f << ";\n";
1539 if (edge_wires[wire]) {
1540 if (unbuffered_wires[wire]) {
1541 f << indent << "value<" << width << "> prev_" << mangle(wire);
1542 if (wire->has_attribute(ID::init)) {
1543 f << " ";
1544 dump_const_init(wire->attributes.at(ID::init));
1545 }
1546 f << ";\n";
1547 }
1548 for (auto edge_type : edge_types) {
1549 if (edge_type.first.wire == wire) {
1550 std::string prev, next;
1551 if (unbuffered_wires[wire]) {
1552 prev = "prev_" + mangle(edge_type.first.wire);
1553 next = mangle(edge_type.first.wire);
1554 } else {
1555 prev = mangle(edge_type.first.wire) + ".curr";
1556 next = mangle(edge_type.first.wire) + ".next";
1557 }
1558 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1559 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1560 if (edge_type.second != RTLIL::STn) {
1561 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1562 inc_indent();
1563 f << indent << "return !" << prev << " && " << next << ";\n";
1564 dec_indent();
1565 f << indent << "}\n";
1566 }
1567 if (edge_type.second != RTLIL::STp) {
1568 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1569 inc_indent();
1570 f << indent << "return " << prev << " && !" << next << ";\n";
1571 dec_indent();
1572 f << indent << "}\n";
1573 }
1574 }
1575 }
1576 }
1577 }
1578 }
1579
1580 void dump_debug_wire(const RTLIL::Wire *wire, bool is_local)
1581 {
1582 if (!debug_outlined_wires[wire])
1583 return;
1584
1585 bool is_outlined_member = wire->name.isPublic() &&
1586 !(debug_const_wires.count(wire) || debug_alias_wires.count(wire));
1587 if (is_local && !is_outlined_member) {
1588 dump_attrs(wire);
1589 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1590 }
1591 if (!is_local && is_outlined_member) {
1592 dump_attrs(wire);
1593 f << indent << "/*outline*/ value<" << wire->width << "> " << mangle(wire) << ";\n";
1594 }
1595 }
1596
1597 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1598 {
1599 vector<const RTLIL::Cell*> init_cells;
1600 for (auto cell : module->cells())
1601 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1602 init_cells.push_back(cell);
1603
1604 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1605 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1606 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1607 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1608 });
1609
1610 dump_attrs(memory);
1611 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1612 << " { " << memory->size << "u";
1613 if (init_cells.empty()) {
1614 f << " };\n";
1615 } else {
1616 f << ",\n";
1617 inc_indent();
1618 for (auto cell : init_cells) {
1619 dump_attrs(cell);
1620 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1621 size_t width = cell->getParam(ID::WIDTH).as_int();
1622 size_t words = cell->getParam(ID::WORDS).as_int();
1623 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1624 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1625 inc_indent();
1626 for (size_t n = 0; n < words; n++) {
1627 if (n % 4 == 0)
1628 f << "\n" << indent;
1629 else
1630 f << " ";
1631 dump_const(data, width, n * width, /*fixed_width=*/true);
1632 f << ",";
1633 }
1634 dec_indent();
1635 f << "\n" << indent << "}},\n";
1636 }
1637 dec_indent();
1638 f << indent << "};\n";
1639 }
1640 }
1641
1642 void dump_eval_method(RTLIL::Module *module)
1643 {
1644 inc_indent();
1645 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1646 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1647 for (auto wire : module->wires()) {
1648 if (edge_wires[wire]) {
1649 for (auto edge_type : edge_types) {
1650 if (edge_type.first.wire == wire) {
1651 if (edge_type.second != RTLIL::STn) {
1652 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1653 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1654 }
1655 if (edge_type.second != RTLIL::STp) {
1656 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1657 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1658 }
1659 }
1660 }
1661 }
1662 }
1663 for (auto wire : module->wires())
1664 dump_wire(wire, /*is_local=*/true);
1665 for (auto node : schedule[module]) {
1666 switch (node.type) {
1667 case FlowGraph::Node::Type::CONNECT:
1668 dump_connect(node.connect);
1669 break;
1670 case FlowGraph::Node::Type::CELL_SYNC:
1671 dump_cell_sync(node.cell);
1672 break;
1673 case FlowGraph::Node::Type::CELL_EVAL:
1674 dump_cell_eval(node.cell);
1675 break;
1676 case FlowGraph::Node::Type::PROCESS:
1677 dump_process(node.process);
1678 break;
1679 }
1680 }
1681 }
1682 f << indent << "return converged;\n";
1683 dec_indent();
1684 }
1685
1686 void dump_debug_eval_method(RTLIL::Module *module)
1687 {
1688 inc_indent();
1689 for (auto wire : module->wires())
1690 dump_debug_wire(wire, /*is_local=*/true);
1691 for (auto node : schedule[module]) {
1692 switch (node.type) {
1693 case FlowGraph::Node::Type::CONNECT:
1694 dump_connect(node.connect, /*for_debug=*/true);
1695 break;
1696 case FlowGraph::Node::Type::CELL_EVAL:
1697 dump_cell_eval(node.cell, /*for_debug=*/true);
1698 break;
1699 case FlowGraph::Node::Type::CELL_SYNC:
1700 case FlowGraph::Node::Type::PROCESS:
1701 break;
1702 }
1703 }
1704 dec_indent();
1705 }
1706
1707 void dump_commit_method(RTLIL::Module *module)
1708 {
1709 inc_indent();
1710 f << indent << "bool changed = false;\n";
1711 for (auto wire : module->wires()) {
1712 if (inlined_wires.count(wire))
1713 continue;
1714 if (unbuffered_wires[wire]) {
1715 if (edge_wires[wire])
1716 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1717 continue;
1718 }
1719 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1720 f << indent << "if (" << mangle(wire) << ".commit()) changed = true;\n";
1721 }
1722 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1723 for (auto memory : module->memories) {
1724 if (!writable_memories[memory.second])
1725 continue;
1726 f << indent << "if (" << mangle(memory.second) << ".commit()) changed = true;\n";
1727 }
1728 for (auto cell : module->cells()) {
1729 if (is_internal_cell(cell->type))
1730 continue;
1731 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1732 f << indent << "if (" << mangle(cell) << access << "commit()) changed = true;\n";
1733 }
1734 }
1735 f << indent << "return changed;\n";
1736 dec_indent();
1737 }
1738
1739 void dump_debug_info_method(RTLIL::Module *module)
1740 {
1741 size_t count_public_wires = 0;
1742 size_t count_const_wires = 0;
1743 size_t count_alias_wires = 0;
1744 size_t count_inline_wires = 0;
1745 size_t count_member_wires = 0;
1746 size_t count_skipped_wires = 0;
1747 size_t count_driven_sync = 0;
1748 size_t count_driven_comb = 0;
1749 size_t count_undriven = 0;
1750 size_t count_mixed_driver = 0;
1751 inc_indent();
1752 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1753 for (auto wire : module->wires()) {
1754 if (!wire->name.isPublic())
1755 continue;
1756 if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
1757 continue;
1758 count_public_wires++;
1759 if (debug_const_wires.count(wire)) {
1760 // Wire tied to a constant
1761 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1762 dump_const(debug_const_wires[wire]);
1763 f << ";\n";
1764 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1765 f << ", debug_item(const_" << mangle(wire) << ", ";
1766 f << wire->start_offset << "));\n";
1767 count_const_wires++;
1768 } else if (debug_alias_wires.count(wire)) {
1769 // Alias of a member wire
1770 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1771 f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
1772 f << wire->start_offset << "));\n";
1773 count_alias_wires++;
1774 } else if (debug_outlined_wires.count(wire)) {
1775 // Inlined but rematerializable wire
1776 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1777 f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", ";
1778 f << wire->start_offset << "));\n";
1779 count_inline_wires++;
1780 } else if (!localized_wires.count(wire)) {
1781 // Member wire
1782 std::vector<std::string> flags;
1783
1784 if (wire->port_input && wire->port_output)
1785 flags.push_back("INOUT");
1786 else if (wire->port_input)
1787 flags.push_back("INPUT");
1788 else if (wire->port_output)
1789 flags.push_back("OUTPUT");
1790
1791 bool has_driven_sync = false;
1792 bool has_driven_comb = false;
1793 bool has_undriven = false;
1794 SigSpec sig(wire);
1795 for (auto bit : sig.bits())
1796 if (!bit_has_state.count(bit))
1797 has_undriven = true;
1798 else if (bit_has_state[bit])
1799 has_driven_sync = true;
1800 else
1801 has_driven_comb = true;
1802 if (has_driven_sync)
1803 flags.push_back("DRIVEN_SYNC");
1804 if (has_driven_sync && !has_driven_comb && !has_undriven)
1805 count_driven_sync++;
1806 if (has_driven_comb)
1807 flags.push_back("DRIVEN_COMB");
1808 if (!has_driven_sync && has_driven_comb && !has_undriven)
1809 count_driven_comb++;
1810 if (has_undriven)
1811 flags.push_back("UNDRIVEN");
1812 if (!has_driven_sync && !has_driven_comb && has_undriven)
1813 count_undriven++;
1814 if (has_driven_sync + has_driven_comb + has_undriven > 1)
1815 count_mixed_driver++;
1816
1817 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1818 f << ", debug_item(" << mangle(wire) << ", ";
1819 f << wire->start_offset;
1820 bool first = true;
1821 for (auto flag : flags) {
1822 if (first) {
1823 first = false;
1824 f << ", ";
1825 } else {
1826 f << "|";
1827 }
1828 f << "debug_item::" << flag;
1829 }
1830 f << "));\n";
1831 count_member_wires++;
1832 } else {
1833 // Localized or inlined wire with no debug information
1834 count_skipped_wires++;
1835 }
1836 }
1837 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1838 for (auto &memory_it : module->memories) {
1839 if (!memory_it.first.isPublic())
1840 continue;
1841 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1842 f << ", debug_item(" << mangle(memory_it.second) << ", ";
1843 f << memory_it.second->start_offset << "));\n";
1844 }
1845 for (auto cell : module->cells()) {
1846 if (is_internal_cell(cell->type))
1847 continue;
1848 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1849 f << indent << mangle(cell) << access << "debug_info(items, ";
1850 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1851 }
1852 }
1853 dec_indent();
1854
1855 log_debug("Debug information statistics for module `%s':\n", log_id(module));
1856 log_debug(" Public wires: %zu, of which:\n", count_public_wires);
1857 log_debug(" Member wires: %zu, of which:\n", count_member_wires);
1858 log_debug(" Driven sync: %zu\n", count_driven_sync);
1859 log_debug(" Driven comb: %zu\n", count_driven_comb);
1860 log_debug(" Mixed driver: %zu\n", count_mixed_driver);
1861 log_debug(" Undriven: %zu\n", count_undriven);
1862 log_debug(" Inline wires: %zu\n", count_inline_wires);
1863 log_debug(" Alias wires: %zu\n", count_alias_wires);
1864 log_debug(" Const wires: %zu\n", count_const_wires);
1865 log_debug(" Other wires: %zu%s\n", count_skipped_wires,
1866 count_skipped_wires > 0 ? " (debug information unavailable)" : "");
1867 }
1868
1869 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1870 {
1871 if (metadata_map.empty()) {
1872 f << "metadata_map()";
1873 return;
1874 }
1875 f << "metadata_map({\n";
1876 inc_indent();
1877 for (auto metadata_item : metadata_map) {
1878 if (!metadata_item.first.begins_with("\\"))
1879 continue;
1880 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1881 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1882 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1883 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1884 f << escape_cxx_string(metadata_item.second.decode_string());
1885 } else {
1886 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1887 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1888 f << "u";
1889 }
1890 f << " },\n";
1891 }
1892 dec_indent();
1893 f << indent << "})";
1894 }
1895
1896 void dump_module_intf(RTLIL::Module *module)
1897 {
1898 dump_attrs(module);
1899 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1900 if (module->has_attribute(ID(cxxrtl_template)))
1901 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1902 f << indent << "struct " << mangle(module) << " : public module {\n";
1903 inc_indent();
1904 for (auto wire : module->wires()) {
1905 if (wire->port_id != 0)
1906 dump_wire(wire, /*is_local=*/false);
1907 }
1908 f << "\n";
1909 f << indent << "bool eval() override {\n";
1910 dump_eval_method(module);
1911 f << indent << "}\n";
1912 f << "\n";
1913 f << indent << "bool commit() override {\n";
1914 dump_commit_method(module);
1915 f << indent << "}\n";
1916 f << "\n";
1917 if (debug_info) {
1918 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1919 dump_debug_info_method(module);
1920 f << indent << "}\n";
1921 f << "\n";
1922 }
1923 f << indent << "static std::unique_ptr<" << mangle(module);
1924 f << template_params(module, /*is_decl=*/false) << "> ";
1925 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1926 dec_indent();
1927 f << indent << "}; // struct " << mangle(module) << "\n";
1928 f << "\n";
1929 if (blackbox_specializations.count(module)) {
1930 // If templated black boxes are used, the constructor of any module which includes the black box cell
1931 // (which calls the declared but not defined in the generated code `create` function) may only be used
1932 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1933 // a forward-declared explicit specialization.
1934 //
1935 // Option (b) makes it possible to have the generated code and the black box implementation in different
1936 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1937 // a specialization for every combination of parameters the generated code may use; but since the main
1938 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1939 // be very few such combinations anyway.
1940 for (auto specialization : blackbox_specializations[module]) {
1941 f << indent << "template<>\n";
1942 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1943 f << mangle(module) << specialization << "::";
1944 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1945 f << "\n";
1946 }
1947 }
1948 } else {
1949 f << indent << "struct " << mangle(module) << " : public module {\n";
1950 inc_indent();
1951 for (auto wire : module->wires())
1952 dump_wire(wire, /*is_local=*/false);
1953 for (auto wire : module->wires())
1954 dump_debug_wire(wire, /*is_local=*/false);
1955 bool has_memories = false;
1956 for (auto memory : module->memories) {
1957 dump_memory(module, memory.second);
1958 has_memories = true;
1959 }
1960 if (has_memories)
1961 f << "\n";
1962 bool has_cells = false;
1963 for (auto cell : module->cells()) {
1964 if (is_internal_cell(cell->type))
1965 continue;
1966 dump_attrs(cell);
1967 RTLIL::Module *cell_module = module->design->module(cell->type);
1968 log_assert(cell_module != nullptr);
1969 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1970 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1971 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1972 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1973 dump_metadata_map(cell->parameters);
1974 f << ", ";
1975 dump_metadata_map(cell->attributes);
1976 f << ");\n";
1977 } else {
1978 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1979 }
1980 has_cells = true;
1981 }
1982 if (has_cells)
1983 f << "\n";
1984 f << indent << mangle(module) << "() {}\n";
1985 if (has_cells) {
1986 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) :\n";
1987 bool first = true;
1988 for (auto cell : module->cells()) {
1989 if (is_internal_cell(cell->type))
1990 continue;
1991 if (first) {
1992 first = false;
1993 } else {
1994 f << ",\n";
1995 }
1996 RTLIL::Module *cell_module = module->design->module(cell->type);
1997 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1998 f << indent << " " << mangle(cell) << "(std::move(other." << mangle(cell) << "))";
1999 } else {
2000 f << indent << " " << mangle(cell) << "(adopt {}, std::move(other." << mangle(cell) << "))";
2001 }
2002 }
2003 f << " {\n";
2004 inc_indent();
2005 for (auto cell : module->cells()) {
2006 if (is_internal_cell(cell->type))
2007 continue;
2008 RTLIL::Module *cell_module = module->design->module(cell->type);
2009 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2010 f << indent << mangle(cell) << "->reset();\n";
2011 }
2012 dec_indent();
2013 f << indent << "}\n";
2014 } else {
2015 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) {}\n";
2016 }
2017 f << "\n";
2018 f << indent << "void reset() override {\n";
2019 inc_indent();
2020 f << indent << "*this = " << mangle(module) << "(adopt {}, std::move(*this));\n";
2021 dec_indent();
2022 f << indent << "}\n";
2023 f << "\n";
2024 f << indent << "bool eval() override;\n";
2025 f << indent << "bool commit() override;\n";
2026 if (debug_info) {
2027 if (debug_eval) {
2028 f << "\n";
2029 f << indent << "void debug_eval();\n";
2030 for (auto wire : module->wires())
2031 if (debug_outlined_wires.count(wire)) {
2032 f << indent << "debug_outline debug_eval_outline { std::bind(&"
2033 << mangle(module) << "::debug_eval, this) };\n";
2034 break;
2035 }
2036 }
2037 f << "\n";
2038 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
2039 }
2040 dec_indent();
2041 f << indent << "}; // struct " << mangle(module) << "\n";
2042 f << "\n";
2043 }
2044 }
2045
2046 void dump_module_impl(RTLIL::Module *module)
2047 {
2048 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
2049 return;
2050 f << indent << "bool " << mangle(module) << "::eval() {\n";
2051 dump_eval_method(module);
2052 f << indent << "}\n";
2053 f << "\n";
2054 f << indent << "bool " << mangle(module) << "::commit() {\n";
2055 dump_commit_method(module);
2056 f << indent << "}\n";
2057 f << "\n";
2058 if (debug_info) {
2059 if (debug_eval) {
2060 f << indent << "void " << mangle(module) << "::debug_eval() {\n";
2061 dump_debug_eval_method(module);
2062 f << indent << "}\n";
2063 f << "\n";
2064 }
2065 f << indent << "CXXRTL_EXTREMELY_COLD\n";
2066 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
2067 dump_debug_info_method(module);
2068 f << indent << "}\n";
2069 f << "\n";
2070 }
2071 }
2072
2073 void dump_design(RTLIL::Design *design)
2074 {
2075 RTLIL::Module *top_module = nullptr;
2076 std::vector<RTLIL::Module*> modules;
2077 TopoSort<RTLIL::Module*> topo_design;
2078 for (auto module : design->modules()) {
2079 if (!design->selected_module(module))
2080 continue;
2081 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
2082 modules.push_back(module); // cxxrtl blackboxes first
2083 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
2084 continue;
2085 if (module->get_bool_attribute(ID::top))
2086 top_module = module;
2087
2088 topo_design.node(module);
2089 for (auto cell : module->cells()) {
2090 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
2091 continue;
2092 RTLIL::Module *cell_module = design->module(cell->type);
2093 log_assert(cell_module != nullptr);
2094 topo_design.edge(cell_module, module);
2095 }
2096 }
2097 bool no_loops = topo_design.sort();
2098 log_assert(no_loops);
2099 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
2100
2101 if (split_intf) {
2102 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
2103 std::string include_guard = design_ns + "_header";
2104 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
2105
2106 f << "#ifndef " << include_guard << "\n";
2107 f << "#define " << include_guard << "\n";
2108 f << "\n";
2109 if (top_module != nullptr && debug_info) {
2110 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
2111 f << "\n";
2112 f << "#ifdef __cplusplus\n";
2113 f << "extern \"C\" {\n";
2114 f << "#endif\n";
2115 f << "\n";
2116 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
2117 f << "\n";
2118 f << "#ifdef __cplusplus\n";
2119 f << "}\n";
2120 f << "#endif\n";
2121 f << "\n";
2122 } else {
2123 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
2124 f << "\n";
2125 }
2126 f << "#ifdef __cplusplus\n";
2127 f << "\n";
2128 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2129 f << "\n";
2130 f << "using namespace cxxrtl;\n";
2131 f << "\n";
2132 f << "namespace " << design_ns << " {\n";
2133 f << "\n";
2134 for (auto module : modules)
2135 dump_module_intf(module);
2136 f << "} // namespace " << design_ns << "\n";
2137 f << "\n";
2138 f << "#endif // __cplusplus\n";
2139 f << "\n";
2140 f << "#endif\n";
2141 *intf_f << f.str(); f.str("");
2142 }
2143
2144 if (split_intf)
2145 f << "#include \"" << intf_filename << "\"\n";
2146 else
2147 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2148 f << "\n";
2149 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
2150 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2151 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
2152 f << "#endif\n";
2153 f << "\n";
2154 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2155 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
2156 f << "#endif\n";
2157 f << "\n";
2158 f << "using namespace cxxrtl_yosys;\n";
2159 f << "\n";
2160 f << "namespace " << design_ns << " {\n";
2161 f << "\n";
2162 for (auto module : modules) {
2163 if (!split_intf)
2164 dump_module_intf(module);
2165 dump_module_impl(module);
2166 }
2167 f << "} // namespace " << design_ns << "\n";
2168 f << "\n";
2169 if (top_module != nullptr && debug_info) {
2170 f << "extern \"C\"\n";
2171 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
2172 inc_indent();
2173 std::string top_type = design_ns + "::" + mangle(top_module);
2174 f << indent << "return new _cxxrtl_toplevel { ";
2175 f << "std::unique_ptr<" << top_type << ">(new " + top_type + ")";
2176 f << " };\n";
2177 dec_indent();
2178 f << "}\n";
2179 }
2180
2181 *impl_f << f.str(); f.str("");
2182 }
2183
2184 // Edge-type sync rules require us to emit edge detectors, which require coordination between
2185 // eval and commit phases. To do this we need to collect them upfront.
2186 //
2187 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
2188 // operate at wire bit granularity; it is possible to have code similar to:
2189 // wire [3:0] clocks;
2190 // always @(posedge clocks[0]) ...
2191 // To handle this we track edge sensitivity both for wires and wire bits.
2192 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
2193 {
2194 signal = sigmap(signal);
2195 log_assert(signal.is_wire() && signal.is_bit());
2196 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
2197
2198 RTLIL::SigBit sigbit = signal[0];
2199 if (!edge_types.count(sigbit))
2200 edge_types[sigbit] = type;
2201 else if (edge_types[sigbit] != type)
2202 edge_types[sigbit] = RTLIL::STe;
2203 edge_wires.insert(signal.as_wire());
2204 }
2205
2206 void analyze_design(RTLIL::Design *design)
2207 {
2208 bool has_feedback_arcs = false;
2209 bool has_buffered_comb_wires = false;
2210
2211 for (auto module : design->modules()) {
2212 if (!design->selected_module(module))
2213 continue;
2214
2215 SigMap &sigmap = sigmaps[module];
2216 sigmap.set(module);
2217
2218 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
2219 for (auto port : module->ports) {
2220 RTLIL::Wire *wire = module->wire(port);
2221 if (wire->port_input && !wire->port_output)
2222 unbuffered_wires.insert(wire);
2223 if (wire->has_attribute(ID(cxxrtl_edge))) {
2224 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
2225 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
2226 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
2227 log_id(module), log_signal(wire));
2228
2229 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
2230 for (int i = 0; i < GetSize(wire); i++) {
2231 RTLIL::SigSpec wire_sig = wire;
2232 switch (edges[i]) {
2233 case '-': break;
2234 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
2235 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
2236 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
2237 default:
2238 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
2239 "other than '-', 'p', 'n', or 'a'.\n",
2240 log_id(module), log_signal(wire));
2241 }
2242 }
2243 }
2244 }
2245
2246 // Black boxes converge by default, since their implementations are quite unlikely to require
2247 // internal propagation of comb signals.
2248 eval_converges[module] = true;
2249 continue;
2250 }
2251
2252 FlowGraph flow;
2253
2254 for (auto conn : module->connections())
2255 flow.add_node(conn);
2256
2257 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
2258 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
2259 pool<const RTLIL::Cell*>> memwr_per_domain;
2260 for (auto cell : module->cells()) {
2261 if (!cell->known())
2262 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2263
2264 RTLIL::Module *cell_module = design->module(cell->type);
2265 if (cell_module &&
2266 cell_module->get_blackbox_attribute() &&
2267 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2268 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2269
2270 if (cell_module &&
2271 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2272 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2273 blackbox_specializations[cell_module].insert(template_args(cell));
2274
2275 FlowGraph::Node *node = flow.add_node(cell);
2276
2277 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2278 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
2279 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2280 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2281 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2282 }
2283 // Similar for memory port cells.
2284 if (cell->type.in(ID($memrd), ID($memwr))) {
2285 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2286 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2287 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2288 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2289 }
2290 memrw_cell_nodes[cell] = node;
2291 }
2292 // Optimize access to read-only memories.
2293 if (cell->type == ID($memwr))
2294 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2295 // Collect groups of memory write ports in the same domain.
2296 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2297 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2298 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2299 memwr_per_domain[{clk_bit, memory}].insert(cell);
2300 }
2301 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2302 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2303 if (cell->type.in(ID($mem)))
2304 log_assert(false);
2305 }
2306 for (auto cell : module->cells()) {
2307 // Collect groups of memory write ports read by every transparent read port.
2308 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2309 cell->getParam(ID::TRANSPARENT).as_bool()) {
2310 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2311 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2312 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2313 transparent_for[cell].insert(memwr_cell);
2314 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2315 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2316 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2317 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2318 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2319 }
2320 }
2321 }
2322
2323 for (auto proc : module->processes) {
2324 flow.add_node(proc.second);
2325
2326 for (auto sync : proc.second->syncs)
2327 switch (sync->type) {
2328 // Edge-type sync rules require pre-registration.
2329 case RTLIL::STp:
2330 case RTLIL::STn:
2331 case RTLIL::STe:
2332 register_edge_signal(sigmap, sync->signal, sync->type);
2333 break;
2334
2335 // Level-type sync rules require no special handling.
2336 case RTLIL::ST0:
2337 case RTLIL::ST1:
2338 case RTLIL::STa:
2339 break;
2340
2341 case RTLIL::STg:
2342 log_cmd_error("Global clock is not supported.\n");
2343
2344 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2345 // attribute regardless of input.
2346 case RTLIL::STi:
2347 log_assert(false);
2348 }
2349 }
2350
2351 for (auto wire : module->wires()) {
2352 if (!flow.is_inlinable(wire)) continue;
2353 if (wire->port_id != 0) continue;
2354 if (wire->get_bool_attribute(ID::keep)) continue;
2355 if (wire->name.begins_with("$") && !inline_internal) continue;
2356 if (wire->name.begins_with("\\") && !inline_public) continue;
2357 if (edge_wires[wire]) continue;
2358 if (flow.wire_comb_defs[wire].size() > 1)
2359 log_cmd_error("Wire %s.%s has multiple drivers.\n", log_id(module), log_id(wire));
2360 log_assert(flow.wire_comb_defs[wire].size() == 1);
2361 inlined_wires[wire] = **flow.wire_comb_defs[wire].begin();
2362 }
2363
2364 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2365 for (auto wire_comb_def : flow.wire_comb_defs)
2366 for (auto node : wire_comb_def.second)
2367 node_defs[node].insert(wire_comb_def.first);
2368
2369 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_uses;
2370 for (auto wire_use : flow.wire_uses)
2371 for (auto node : wire_use.second)
2372 node_uses[node].insert(wire_use.first);
2373
2374 Scheduler<FlowGraph::Node> scheduler;
2375 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2376 for (auto node : flow.nodes)
2377 node_map[node] = scheduler.add(node);
2378 for (auto node_def : node_defs) {
2379 auto vertex = node_map[node_def.first];
2380 for (auto wire : node_def.second)
2381 for (auto succ_node : flow.wire_uses[wire]) {
2382 auto succ_vertex = node_map[succ_node];
2383 vertex->succs.insert(succ_vertex);
2384 succ_vertex->preds.insert(vertex);
2385 }
2386 }
2387
2388 auto eval_order = scheduler.schedule();
2389 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2390 pool<const RTLIL::Wire*> feedback_wires;
2391 for (auto vertex : eval_order) {
2392 auto node = vertex->data;
2393 schedule[module].push_back(*node);
2394 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2395 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2396 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2397 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2398 evaluated.insert(node);
2399 for (auto wire : node_defs[node])
2400 for (auto succ_node : flow.wire_uses[wire])
2401 if (evaluated[succ_node]) {
2402 feedback_wires.insert(wire);
2403 // Feedback wires may never be inlined because feedback requires state, but the point of
2404 // inlining (and localization) is to eliminate state.
2405 inlined_wires.erase(wire);
2406 }
2407 }
2408
2409 if (!feedback_wires.empty()) {
2410 has_feedback_arcs = true;
2411 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2412 for (auto wire : feedback_wires)
2413 log(" %s\n", log_id(wire));
2414 }
2415
2416 for (auto wire : module->wires()) {
2417 if (feedback_wires[wire]) continue;
2418 if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
2419 if (wire->name.begins_with("$") && !unbuffer_internal) continue;
2420 if (wire->name.begins_with("\\") && !unbuffer_public) continue;
2421 if (flow.wire_sync_defs.count(wire) > 0) continue;
2422 unbuffered_wires.insert(wire);
2423 if (edge_wires[wire]) continue;
2424 if (wire->get_bool_attribute(ID::keep)) continue;
2425 if (wire->port_input || wire->port_output) continue;
2426 if (wire->name.begins_with("$") && !localize_internal) continue;
2427 if (wire->name.begins_with("\\") && !localize_public) continue;
2428 localized_wires.insert(wire);
2429 }
2430
2431 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2432 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2433 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2434 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2435 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2436 // also require more than one delta cycle to converge.
2437 pool<const RTLIL::Wire*> buffered_comb_wires;
2438 for (auto wire : module->wires()) {
2439 if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
2440 buffered_comb_wires.insert(wire);
2441 }
2442 if (!buffered_comb_wires.empty()) {
2443 has_buffered_comb_wires = true;
2444 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2445 for (auto wire : buffered_comb_wires)
2446 log(" %s\n", log_id(wire));
2447 }
2448
2449 eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
2450
2451 for (auto item : flow.bit_has_state)
2452 bit_has_state.insert(item);
2453
2454 if (debug_info && debug_eval) {
2455 // Find wires that can be be outlined, i.e. whose values can be always recovered from
2456 // the values of other wires. (This is the inverse of inlining--any wire that can be
2457 // inlined can also be outlined.) Although this may seem strictly less efficient, since
2458 // such values are computed at least twice, second-order effects make outlining useful.
2459 pool<const RTLIL::Wire*> worklist, visited;
2460 for (auto wire : module->wires()) {
2461 if (!wire->name.isPublic())
2462 continue;
2463 worklist.insert(wire);
2464 }
2465 while (!worklist.empty()) {
2466 const RTLIL::Wire *wire = worklist.pop();
2467 visited.insert(wire);
2468 if (!localized_wires.count(wire) && !inlined_wires.count(wire))
2469 continue; // member wire, doesn't need outlining
2470 if (wire->name.isPublic() || !inlined_wires.count(wire))
2471 debug_outlined_wires.insert(wire); // allow outlining of internal wires only
2472 for (auto node : flow.wire_comb_defs[wire])
2473 for (auto node_use : node_uses[node])
2474 if (!visited.count(node_use))
2475 worklist.insert(node_use);
2476 }
2477 }
2478 if (debug_info && debug_alias) {
2479 // Find wires that alias other wires or are tied to a constant. Both of these cases are
2480 // directly expressible in the debug information, improving coverage at zero cost.
2481 for (auto wire : module->wires()) {
2482 if (!wire->name.isPublic())
2483 continue;
2484 const RTLIL::Wire *cursor = wire;
2485 RTLIL::SigSpec alias_of;
2486 while (1) {
2487 if (!(flow.wire_def_inlinable.count(cursor) && flow.wire_def_inlinable[cursor]))
2488 break; // not an alias: complex def
2489 log_assert(flow.wire_comb_defs[cursor].size() == 1);
2490 FlowGraph::Node *node = *flow.wire_comb_defs[cursor].begin();
2491 if (node->type != FlowGraph::Node::Type::CONNECT)
2492 break; // not an alias: def by cell
2493 RTLIL::SigSpec rhs_sig = node->connect.second;
2494 if (rhs_sig.is_fully_const()) {
2495 alias_of = rhs_sig; // alias of const
2496 break;
2497 } else if (rhs_sig.is_wire()) {
2498 RTLIL::Wire *rhs_wire = rhs_sig.as_wire(); // possible alias of wire
2499 if (rhs_wire->port_input && !rhs_wire->port_output) {
2500 alias_of = rhs_wire; // alias of input
2501 break;
2502 } else if (!localized_wires.count(rhs_wire) && !inlined_wires.count(rhs_wire)) {
2503 alias_of = rhs_wire; // alias of member
2504 break;
2505 } else {
2506 if (rhs_wire->name.isPublic() && debug_outlined_wires.count(rhs_wire))
2507 alias_of = rhs_wire; // alias of either outline or another alias
2508 cursor = rhs_wire; // keep looking
2509 }
2510 } else {
2511 break; // not an alias: complex rhs
2512 }
2513 }
2514 if (alias_of.empty()) {
2515 continue;
2516 } else if (alias_of.is_fully_const()) {
2517 debug_const_wires[wire] = alias_of.as_const();
2518 } else if (alias_of.is_wire()) {
2519 debug_alias_wires[wire] = alias_of.as_wire();
2520 } else log_abort();
2521 if (inlined_wires.count(wire))
2522 debug_outlined_wires.erase(wire);
2523 }
2524 }
2525 }
2526 if (has_feedback_arcs || has_buffered_comb_wires) {
2527 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2528 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2529 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2530 const char *why_pessimistic = nullptr;
2531 if (has_feedback_arcs)
2532 why_pessimistic = "feedback wires";
2533 else if (has_buffered_comb_wires)
2534 why_pessimistic = "buffered combinatorial wires";
2535 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2536 if (!run_flatten)
2537 log("Flattening may eliminate %s from the design.\n", why_pessimistic);
2538 if (!run_proc)
2539 log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic);
2540 }
2541 }
2542
2543 void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init, bool &has_packed_mem)
2544 {
2545 has_sync_init = has_packed_mem = has_top = false;
2546
2547 for (auto module : design->modules()) {
2548 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2549 continue;
2550
2551 if (!design->selected_whole_module(module))
2552 if (design->selected_module(module))
2553 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2554 if (!design->selected_module(module))
2555 continue;
2556
2557 if (module->get_bool_attribute(ID::top))
2558 has_top = true;
2559
2560 for (auto proc : module->processes)
2561 for (auto sync : proc.second->syncs)
2562 if (sync->type == RTLIL::STi)
2563 has_sync_init = true;
2564
2565 // The Mem constructor also checks for well-formedness of $meminit cells, if any.
2566 for (auto &mem : Mem::get_all_memories(module))
2567 if (mem.packed)
2568 has_packed_mem = true;
2569 }
2570 }
2571
2572 void prepare_design(RTLIL::Design *design)
2573 {
2574 bool did_anything = false;
2575 bool has_top, has_sync_init, has_packed_mem;
2576 log_push();
2577 check_design(design, has_top, has_sync_init, has_packed_mem);
2578 if (run_hierarchy && !has_top) {
2579 Pass::call(design, "hierarchy -auto-top");
2580 did_anything = true;
2581 }
2582 if (run_flatten) {
2583 Pass::call(design, "flatten");
2584 did_anything = true;
2585 }
2586 if (run_proc) {
2587 Pass::call(design, "proc");
2588 did_anything = true;
2589 } else if (has_sync_init) {
2590 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2591 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2592 Pass::call(design, "proc_prune");
2593 Pass::call(design, "proc_clean");
2594 Pass::call(design, "proc_init");
2595 did_anything = true;
2596 }
2597 if (has_packed_mem) {
2598 Pass::call(design, "memory_unpack");
2599 did_anything = true;
2600 }
2601 // Recheck the design if it was modified.
2602 if (did_anything)
2603 check_design(design, has_top, has_sync_init, has_packed_mem);
2604 log_assert(has_top && !has_sync_init && !has_packed_mem);
2605 log_pop();
2606 if (did_anything)
2607 log_spacer();
2608 analyze_design(design);
2609 }
2610 };
2611
2612 struct CxxrtlBackend : public Backend {
2613 static const int DEFAULT_OPT_LEVEL = 6;
2614 static const int DEFAULT_DEBUG_LEVEL = 3;
2615
2616 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2617 void help() override
2618 {
2619 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2620 log("\n");
2621 log(" write_cxxrtl [options] [filename]\n");
2622 log("\n");
2623 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2624 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2625 log("\n");
2626 log("The following driver may be used as an example for a design with a single clock\n");
2627 log("driving rising edge triggered flip-flops:\n");
2628 log("\n");
2629 log(" #include \"top.cc\"\n");
2630 log("\n");
2631 log(" int main() {\n");
2632 log(" cxxrtl_design::p_top top;\n");
2633 log(" top.step();\n");
2634 log(" while (1) {\n");
2635 log(" /* user logic */\n");
2636 log(" top.p_clk.set(false);\n");
2637 log(" top.step();\n");
2638 log(" top.p_clk.set(true);\n");
2639 log(" top.step();\n");
2640 log(" }\n");
2641 log(" }\n");
2642 log("\n");
2643 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2644 log("subject to race conditions. If, in the example above, the user logic would run\n");
2645 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2646 log("\n");
2647 log("This backend supports replacing parts of the design with black boxes implemented\n");
2648 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2649 log("and the generated code consists only of an interface and a factory function.\n");
2650 log("The driver must implement the factory function that creates an implementation of\n");
2651 log("the black box, taking into account the parameters it is instantiated with.\n");
2652 log("\n");
2653 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2654 log("a synchronous debug sink:\n");
2655 log("\n");
2656 log(" (* cxxrtl_blackbox *)\n");
2657 log(" module debug(...);\n");
2658 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2659 log(" input en;\n");
2660 log(" input [7:0] i_data;\n");
2661 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2662 log(" endmodule\n");
2663 log("\n");
2664 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2665 log("\n");
2666 log(" struct bb_p_debug : public module {\n");
2667 log(" value<1> p_clk;\n");
2668 log(" bool posedge_p_clk() const { /* ... */ }\n");
2669 log(" value<1> p_en;\n");
2670 log(" value<8> p_i_data;\n");
2671 log(" wire<8> p_o_data;\n");
2672 log("\n");
2673 log(" bool eval() override;\n");
2674 log(" bool commit() override;\n");
2675 log("\n");
2676 log(" static std::unique_ptr<bb_p_debug>\n");
2677 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2678 log(" };\n");
2679 log("\n");
2680 log("The `create' function must be implemented by the driver. For example, it could\n");
2681 log("always provide an implementation logging the values to standard error stream:\n");
2682 log("\n");
2683 log(" namespace cxxrtl_design {\n");
2684 log("\n");
2685 log(" struct stderr_debug : public bb_p_debug {\n");
2686 log(" bool eval() override {\n");
2687 log(" if (posedge_p_clk() && p_en)\n");
2688 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2689 log(" p_o_data.next = p_i_data;\n");
2690 log(" return bb_p_debug::eval();\n");
2691 log(" }\n");
2692 log(" };\n");
2693 log("\n");
2694 log(" std::unique_ptr<bb_p_debug>\n");
2695 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2696 log(" cxxrtl::metadata_map attributes) {\n");
2697 log(" return std::make_unique<stderr_debug>();\n");
2698 log(" }\n");
2699 log("\n");
2700 log(" }\n");
2701 log("\n");
2702 log("For complex applications of black boxes, it is possible to parameterize their\n");
2703 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2704 log("interface for a configurable width debug sink:\n");
2705 log("\n");
2706 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2707 log(" module debug(...);\n");
2708 log(" parameter WIDTH = 8;\n");
2709 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2710 log(" input en;\n");
2711 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2712 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2713 log(" endmodule\n");
2714 log("\n");
2715 log("For this parametric HDL interface, this backend will generate the following C++\n");
2716 log("interface (only the differences are shown):\n");
2717 log("\n");
2718 log(" template<size_t WIDTH>\n");
2719 log(" struct bb_p_debug : public module {\n");
2720 log(" // ...\n");
2721 log(" value<WIDTH> p_i_data;\n");
2722 log(" wire<WIDTH> p_o_data;\n");
2723 log(" // ...\n");
2724 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2725 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2726 log(" };\n");
2727 log("\n");
2728 log("The `create' function must be implemented by the driver, specialized for every\n");
2729 log("possible combination of template parameters. (Specialization is necessary to\n");
2730 log("enable separate compilation of generated code and black box implementations.)\n");
2731 log("\n");
2732 log(" template<size_t SIZE>\n");
2733 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2734 log(" // ...\n");
2735 log(" };\n");
2736 log("\n");
2737 log(" template<>\n");
2738 log(" std::unique_ptr<bb_p_debug<8>>\n");
2739 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2740 log(" cxxrtl::metadata_map attributes) {\n");
2741 log(" return std::make_unique<stderr_debug<8>>();\n");
2742 log(" }\n");
2743 log("\n");
2744 log("The following attributes are recognized by this backend:\n");
2745 log("\n");
2746 log(" cxxrtl_blackbox\n");
2747 log(" only valid on modules. if specified, the module contents are ignored,\n");
2748 log(" and the generated code includes only the module interface and a factory\n");
2749 log(" function, which will be called to instantiate the module.\n");
2750 log("\n");
2751 log(" cxxrtl_edge\n");
2752 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2753 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2754 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2755 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2756 log("\n");
2757 log(" cxxrtl_template\n");
2758 log(" only valid on black boxes. must contain a space separated sequence of\n");
2759 log(" identifiers that have a corresponding black box parameters. for each\n");
2760 log(" of them, the generated code includes a `size_t` template parameter.\n");
2761 log("\n");
2762 log(" cxxrtl_width\n");
2763 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2764 log(" is directly inserted into generated code.\n");
2765 log("\n");
2766 log(" cxxrtl_comb, cxxrtl_sync\n");
2767 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2768 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2769 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2770 log(" if neither is specified, the output will be pessimistically treated as\n");
2771 log(" driven by both combinatorial and synchronous logic.\n");
2772 log("\n");
2773 log("The following options are supported by this backend:\n");
2774 log("\n");
2775 log(" -header\n");
2776 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2777 log(" if specified, the backend must be called with a filename, and filename\n");
2778 log(" of the interface is derived from filename of the implementation.\n");
2779 log(" otherwise, interface and implementation are generated together.\n");
2780 log("\n");
2781 log(" -namespace <ns-name>\n");
2782 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2783 log(" \"cxxrtl_design\" is used.\n");
2784 log("\n");
2785 log(" -nohierarchy\n");
2786 log(" use design hierarchy as-is. in most designs, a top module should be\n");
2787 log(" present as it is exposed through the C API and has unbuffered outputs\n");
2788 log(" for improved performance; it will be determined automatically if absent.\n");
2789 log("\n");
2790 log(" -noflatten\n");
2791 log(" don't flatten the design. fully flattened designs can evaluate within\n");
2792 log(" one delta cycle if they have no combinatorial feedback.\n");
2793 log(" note that the debug interface and waveform dumps use full hierarchical\n");
2794 log(" names for all wires even in flattened designs.\n");
2795 log("\n");
2796 log(" -noproc\n");
2797 log(" don't convert processes to netlists. in most designs, converting\n");
2798 log(" processes significantly improves evaluation performance at the cost of\n");
2799 log(" slight increase in compilation time.\n");
2800 log("\n");
2801 log(" -O <level>\n");
2802 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2803 log(" levels dramatically decrease compile and run time, and highest level\n");
2804 log(" possible for a design should be used.\n");
2805 log("\n");
2806 log(" -O0\n");
2807 log(" no optimization.\n");
2808 log("\n");
2809 log(" -O1\n");
2810 log(" localize internal wires if possible.\n");
2811 log("\n");
2812 log(" -O2\n");
2813 log(" like -O1, and unbuffer internal wires if possible.\n");
2814 log("\n");
2815 log(" -O3\n");
2816 log(" like -O2, and inline internal wires if possible.\n");
2817 log("\n");
2818 log(" -O4\n");
2819 log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
2820 log("\n");
2821 log(" -O5\n");
2822 log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
2823 log("\n");
2824 log(" -O6\n");
2825 log(" like -O5, and inline public wires not marked (*keep*) if possible.\n");
2826 log("\n");
2827 log(" -g <level>\n");
2828 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2829 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2830 log("\n");
2831 log(" -g0\n");
2832 log(" no debug information. the C API is unavailable.\n");
2833 log("\n");
2834 log(" -g1\n");
2835 log(" debug information for member public wires only. this is the bare minimum\n");
2836 log(" necessary to access all design state. enables the C API.\n");
2837 log("\n");
2838 log(" -g2\n");
2839 log(" like -g1, and include debug information for public wires that are tied\n");
2840 log(" to a constant or another public wire.\n");
2841 log("\n");
2842 log(" -g3\n");
2843 log(" like -g2, and compute debug information on demand for all public wires\n");
2844 log(" that were optimized out.\n");
2845 log("\n");
2846 }
2847
2848 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
2849 {
2850 bool nohierarchy = false;
2851 bool noflatten = false;
2852 bool noproc = false;
2853 int opt_level = DEFAULT_OPT_LEVEL;
2854 int debug_level = DEFAULT_DEBUG_LEVEL;
2855 CxxrtlWorker worker;
2856
2857 log_header(design, "Executing CXXRTL backend.\n");
2858
2859 size_t argidx;
2860 for (argidx = 1; argidx < args.size(); argidx++)
2861 {
2862 if (args[argidx] == "-nohierarchy") {
2863 nohierarchy = true;
2864 continue;
2865 }
2866 if (args[argidx] == "-noflatten") {
2867 noflatten = true;
2868 continue;
2869 }
2870 if (args[argidx] == "-noproc") {
2871 noproc = true;
2872 continue;
2873 }
2874 if (args[argidx] == "-Og") {
2875 log_warning("The `-Og` option has been removed. Use `-g3` instead for complete "
2876 "design coverage regardless of optimization level.\n");
2877 continue;
2878 }
2879 if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
2880 argidx++;
2881 log_warning("The `-Og` option has been removed. Use `-g3` instead for complete "
2882 "design coverage regardless of optimization level.\n");
2883 continue;
2884 }
2885 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2886 opt_level = std::stoi(args[++argidx]);
2887 continue;
2888 }
2889 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2890 opt_level = std::stoi(args[argidx].substr(2));
2891 continue;
2892 }
2893 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2894 debug_level = std::stoi(args[++argidx]);
2895 continue;
2896 }
2897 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2898 debug_level = std::stoi(args[argidx].substr(2));
2899 continue;
2900 }
2901 if (args[argidx] == "-header") {
2902 worker.split_intf = true;
2903 continue;
2904 }
2905 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2906 worker.design_ns = args[++argidx];
2907 continue;
2908 }
2909 break;
2910 }
2911 extra_args(f, filename, args, argidx);
2912
2913 worker.run_hierarchy = !nohierarchy;
2914 worker.run_flatten = !noflatten;
2915 worker.run_proc = !noproc;
2916 switch (opt_level) {
2917 // the highest level here must match DEFAULT_OPT_LEVEL
2918 case 6:
2919 worker.inline_public = true;
2920 YS_FALLTHROUGH
2921 case 5:
2922 worker.localize_public = true;
2923 YS_FALLTHROUGH
2924 case 4:
2925 worker.unbuffer_public = true;
2926 YS_FALLTHROUGH
2927 case 3:
2928 worker.inline_internal = true;
2929 YS_FALLTHROUGH
2930 case 2:
2931 worker.localize_internal = true;
2932 YS_FALLTHROUGH
2933 case 1:
2934 worker.unbuffer_internal = true;
2935 YS_FALLTHROUGH
2936 case 0:
2937 break;
2938 default:
2939 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2940 }
2941 switch (debug_level) {
2942 // the highest level here must match DEFAULT_DEBUG_LEVEL
2943 case 3:
2944 worker.debug_eval = true;
2945 YS_FALLTHROUGH
2946 case 2:
2947 worker.debug_alias = true;
2948 YS_FALLTHROUGH
2949 case 1:
2950 worker.debug_info = true;
2951 YS_FALLTHROUGH
2952 case 0:
2953 break;
2954 default:
2955 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2956 }
2957
2958 std::ofstream intf_f;
2959 if (worker.split_intf) {
2960 if (filename == "<stdout>")
2961 log_cmd_error("Option -header must be used with a filename.\n");
2962
2963 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2964 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2965 if (intf_f.fail())
2966 log_cmd_error("Can't open file `%s' for writing: %s\n",
2967 worker.intf_filename.c_str(), strerror(errno));
2968
2969 worker.intf_f = &intf_f;
2970 }
2971 worker.impl_f = f;
2972
2973 worker.prepare_design(design);
2974 worker.dump_design(design);
2975 }
2976 } CxxrtlBackend;
2977
2978 PRIVATE_NAMESPACE_END