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Merge pull request #2468 from whitequark/cxxrtl-assert
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/mem.h"
26 #include "kernel/log.h"
27
28 USING_YOSYS_NAMESPACE
29 PRIVATE_NAMESPACE_BEGIN
30
31 // [[CITE]]
32 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
33 // Information Processing Letters, Vol. 47, pp 319-323, 1993
34 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
35
36 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
37 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
38 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
39 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
40 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
41 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
42 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
43 template<class T>
44 struct Scheduler {
45 struct Vertex {
46 T *data;
47 Vertex *prev, *next;
48 pool<Vertex*, hash_ptr_ops> preds, succs;
49
50 Vertex() : data(NULL), prev(this), next(this) {}
51 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
52
53 bool empty() const
54 {
55 log_assert(data == NULL);
56 if (next == this) {
57 log_assert(prev == next);
58 return true;
59 }
60 return false;
61 }
62
63 void link(Vertex *list)
64 {
65 log_assert(prev == NULL && next == NULL);
66 next = list;
67 prev = list->prev;
68 list->prev->next = this;
69 list->prev = this;
70 }
71
72 void unlink()
73 {
74 log_assert(prev->next == this && next->prev == this);
75 prev->next = next;
76 next->prev = prev;
77 next = prev = NULL;
78 }
79
80 int delta() const
81 {
82 return succs.size() - preds.size();
83 }
84 };
85
86 std::vector<Vertex*> vertices;
87 Vertex *sources = new Vertex;
88 Vertex *sinks = new Vertex;
89 dict<int, Vertex*> bins;
90
91 ~Scheduler()
92 {
93 delete sources;
94 delete sinks;
95 for (auto bin : bins)
96 delete bin.second;
97 for (auto vertex : vertices)
98 delete vertex;
99 }
100
101 Vertex *add(T *data)
102 {
103 Vertex *vertex = new Vertex(data);
104 vertices.push_back(vertex);
105 return vertex;
106 }
107
108 void relink(Vertex *vertex)
109 {
110 if (vertex->succs.empty())
111 vertex->link(sinks);
112 else if (vertex->preds.empty())
113 vertex->link(sources);
114 else {
115 int delta = vertex->delta();
116 if (!bins.count(delta))
117 bins[delta] = new Vertex;
118 vertex->link(bins[delta]);
119 }
120 }
121
122 Vertex *remove(Vertex *vertex)
123 {
124 vertex->unlink();
125 for (auto pred : vertex->preds) {
126 if (pred == vertex)
127 continue;
128 log_assert(pred->succs[vertex]);
129 pred->unlink();
130 pred->succs.erase(vertex);
131 relink(pred);
132 }
133 for (auto succ : vertex->succs) {
134 if (succ == vertex)
135 continue;
136 log_assert(succ->preds[vertex]);
137 succ->unlink();
138 succ->preds.erase(vertex);
139 relink(succ);
140 }
141 vertex->preds.clear();
142 vertex->succs.clear();
143 return vertex;
144 }
145
146 std::vector<Vertex*> schedule()
147 {
148 std::vector<Vertex*> s1, s2r;
149 for (auto vertex : vertices)
150 relink(vertex);
151 bool bins_empty = false;
152 while (!(sinks->empty() && sources->empty() && bins_empty)) {
153 while (!sinks->empty())
154 s2r.push_back(remove(sinks->next));
155 while (!sources->empty())
156 s1.push_back(remove(sources->next));
157 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
158 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
159 // naive implementation of find-max-key.
160 bins_empty = true;
161 bins.template sort<std::greater<int>>();
162 for (auto bin : bins) {
163 if (!bin.second->empty()) {
164 bins_empty = false;
165 s1.push_back(remove(bin.second->next));
166 break;
167 }
168 }
169 }
170 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
171 return s1;
172 }
173 };
174
175 bool is_unary_cell(RTLIL::IdString type)
176 {
177 return type.in(
178 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
179 ID($pos), ID($neg));
180 }
181
182 bool is_binary_cell(RTLIL::IdString type)
183 {
184 return type.in(
185 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
186 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
187 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
188 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
189 }
190
191 bool is_extending_cell(RTLIL::IdString type)
192 {
193 return !type.in(
194 ID($logic_not), ID($logic_and), ID($logic_or),
195 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
196 }
197
198 bool is_elidable_cell(RTLIL::IdString type)
199 {
200 return is_unary_cell(type) || is_binary_cell(type) || type.in(
201 ID($mux), ID($concat), ID($slice), ID($pmux));
202 }
203
204 bool is_ff_cell(RTLIL::IdString type)
205 {
206 return type.in(
207 ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
208 ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
209 ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
210 }
211
212 bool is_internal_cell(RTLIL::IdString type)
213 {
214 return type[0] == '$' && !type.begins_with("$paramod");
215 }
216
217 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
218 {
219 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
220 log_assert(cell_module != nullptr);
221 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
222 }
223
224 enum class CxxrtlPortType {
225 UNKNOWN = 0, // or mixed comb/sync
226 COMB = 1,
227 SYNC = 2,
228 };
229
230 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
231 {
232 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
233 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
234 return CxxrtlPortType::UNKNOWN;
235 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
236 log_assert(cell_output_wire != nullptr);
237 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
238 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
239 if (is_comb && is_sync)
240 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
241 log_id(cell_module), log_signal(cell_output_wire));
242 else if (is_comb)
243 return CxxrtlPortType::COMB;
244 else if (is_sync)
245 return CxxrtlPortType::SYNC;
246 return CxxrtlPortType::UNKNOWN;
247 }
248
249 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
250 {
251 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
252 }
253
254 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
255 {
256 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
257 }
258
259 struct FlowGraph {
260 struct Node {
261 enum class Type {
262 CONNECT,
263 CELL_SYNC,
264 CELL_EVAL,
265 PROCESS
266 };
267
268 Type type;
269 RTLIL::SigSig connect = {};
270 const RTLIL::Cell *cell = NULL;
271 const RTLIL::Process *process = NULL;
272 };
273
274 std::vector<Node*> nodes;
275 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
276 dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
277 dict<RTLIL::SigBit, bool> bit_has_state;
278
279 ~FlowGraph()
280 {
281 for (auto node : nodes)
282 delete node;
283 }
284
285 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool elidable)
286 {
287 for (auto chunk : sig.chunks())
288 if (chunk.wire) {
289 if (is_ff) {
290 // A sync def means that a wire holds design state because it is driven directly by
291 // a flip-flop output. Such a wire can never be unbuffered.
292 wire_sync_defs[chunk.wire].insert(node);
293 } else {
294 // A comb def means that a wire doesn't hold design state. It might still be connected,
295 // indirectly, to a flip-flop output.
296 wire_comb_defs[chunk.wire].insert(node);
297 }
298 }
299 for (auto bit : sig.bits())
300 bit_has_state[bit] |= is_ff;
301 // Only comb defs of an entire wire in the right order can be elided.
302 if (!is_ff && sig.is_wire())
303 wire_def_elidable[sig.as_wire()] = elidable;
304 }
305
306 void add_uses(Node *node, const RTLIL::SigSpec &sig)
307 {
308 for (auto chunk : sig.chunks())
309 if (chunk.wire) {
310 wire_uses[chunk.wire].insert(node);
311 // Only a single use of an entire wire in the right order can be elided.
312 // (But the use can include other chunks.)
313 if (!wire_use_elidable.count(chunk.wire))
314 wire_use_elidable[chunk.wire] = true;
315 else
316 wire_use_elidable[chunk.wire] = false;
317 }
318 }
319
320 bool is_elidable(const RTLIL::Wire *wire) const
321 {
322 if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire))
323 return wire_def_elidable.at(wire) && wire_use_elidable.at(wire);
324 return false;
325 }
326
327 // Connections
328 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
329 {
330 add_defs(node, conn.first, /*is_ff=*/false, /*elidable=*/true);
331 add_uses(node, conn.second);
332 }
333
334 Node *add_node(const RTLIL::SigSig &conn)
335 {
336 Node *node = new Node;
337 node->type = Node::Type::CONNECT;
338 node->connect = conn;
339 nodes.push_back(node);
340 add_connect_defs_uses(node, conn);
341 return node;
342 }
343
344 // Cells
345 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
346 {
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
352 //
353 // wire<1> i_tmp;
354 // cell->p_i = i_tmp.curr;
355 // cell->eval();
356 // i_tmp.next = cell->p_o.curr;
357 //
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
361 //
362 // value<1> i_tmp;
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
365 // cell->eval();
366 //
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn : cell->connections())
374 if (cell->output(conn.first))
375 if (is_cxxrtl_sync_port(cell, conn.first)) {
376 // See note regarding elidability below.
377 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false);
378 }
379 }
380
381 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
382 {
383 for (auto conn : cell->connections()) {
384 if (cell->output(conn.first)) {
385 if (is_elidable_cell(cell->type))
386 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/true);
387 else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
388 add_defs(node, conn.second, /*is_ff=*/true, /*elidable=*/false);
389 else if (is_internal_cell(cell->type))
390 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false);
391 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
392 // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
396 // the infrastructure required to elide outputs of cells with many of them.
397 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false);
398 }
399 }
400 if (cell->input(conn.first))
401 add_uses(node, conn.second);
402 }
403 }
404
405 Node *add_node(const RTLIL::Cell *cell)
406 {
407 log_assert(cell->known());
408
409 bool has_fully_sync_outputs = false;
410 for (auto conn : cell->connections())
411 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
412 has_fully_sync_outputs = true;
413 break;
414 }
415 if (has_fully_sync_outputs) {
416 Node *node = new Node;
417 node->type = Node::Type::CELL_SYNC;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_sync_defs(node, cell);
421 }
422
423 Node *node = new Node;
424 node->type = Node::Type::CELL_EVAL;
425 node->cell = cell;
426 nodes.push_back(node);
427 add_cell_eval_defs_uses(node, cell);
428 return node;
429 }
430
431 // Processes
432 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
433 {
434 for (auto &action : case_->actions) {
435 add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false);
436 add_uses(node, action.second);
437 }
438 for (auto sub_switch : case_->switches) {
439 add_uses(node, sub_switch->signal);
440 for (auto sub_case : sub_switch->cases) {
441 for (auto &compare : sub_case->compare)
442 add_uses(node, compare);
443 add_case_defs_uses(node, sub_case);
444 }
445 }
446 }
447
448 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
449 {
450 add_case_defs_uses(node, &process->root_case);
451 for (auto sync : process->syncs)
452 for (auto action : sync->actions) {
453 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
454 add_defs(node, action.first, /*is_ff=*/true, /*elidable=*/false);
455 else
456 add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false);
457 add_uses(node, action.second);
458 }
459 }
460
461 Node *add_node(const RTLIL::Process *process)
462 {
463 Node *node = new Node;
464 node->type = Node::Type::PROCESS;
465 node->process = process;
466 nodes.push_back(node);
467 add_process_defs_uses(node, process);
468 return node;
469 }
470 };
471
472 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
473 {
474 std::vector<std::string> result;
475 size_t prev = 0;
476 while (true) {
477 size_t curr = str.find_first_of(sep, prev);
478 if (curr == std::string::npos) {
479 std::string part = str.substr(prev);
480 if (!part.empty()) result.push_back(part);
481 break;
482 } else {
483 std::string part = str.substr(prev, curr - prev);
484 if (!part.empty()) result.push_back(part);
485 prev = curr + 1;
486 }
487 }
488 return result;
489 }
490
491 std::string escape_cxx_string(const std::string &input)
492 {
493 std::string output = "\"";
494 for (auto c : input) {
495 if (::isprint(c)) {
496 if (c == '\\')
497 output.push_back('\\');
498 output.push_back(c);
499 } else {
500 char l = c & 0xf, h = (c >> 4) & 0xf;
501 output.append("\\x");
502 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
503 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
504 }
505 }
506 output.push_back('"');
507 if (output.find('\0') != std::string::npos) {
508 output.insert(0, "std::string {");
509 output.append(stringf(", %zu}", input.size()));
510 }
511 return output;
512 }
513
514 template<class T>
515 std::string get_hdl_name(T *object)
516 {
517 if (object->has_attribute(ID::hdlname))
518 return object->get_string_attribute(ID::hdlname);
519 else
520 return object->name.str().substr(1);
521 }
522
523 struct CxxrtlWorker {
524 bool split_intf = false;
525 std::string intf_filename;
526 std::string design_ns = "cxxrtl_design";
527 std::ostream *impl_f = nullptr;
528 std::ostream *intf_f = nullptr;
529
530 bool run_hierarchy = false;
531 bool run_flatten = false;
532 bool run_proc = false;
533
534 bool unbuffer_internal = false;
535 bool unbuffer_public = false;
536 bool localize_internal = false;
537 bool localize_public = false;
538 bool elide_internal = false;
539 bool elide_public = false;
540
541 bool debug_info = false;
542
543 std::ostringstream f;
544 std::string indent;
545 int temporary = 0;
546
547 dict<const RTLIL::Module*, SigMap> sigmaps;
548 pool<const RTLIL::Wire*> edge_wires;
549 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
550 pool<const RTLIL::Memory*> writable_memories;
551 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
552 dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
553 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
554 pool<const RTLIL::Wire*> unbuffered_wires;
555 pool<const RTLIL::Wire*> localized_wires;
556 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
557 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
558 dict<RTLIL::SigBit, bool> bit_has_state;
559 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
560 dict<const RTLIL::Module*, bool> eval_converges;
561
562 void inc_indent() {
563 indent += "\t";
564 }
565 void dec_indent() {
566 indent.resize(indent.size() - 1);
567 }
568
569 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
570 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
571 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
572 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
573 // 1. All generated identifiers start with `_`.
574 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
575 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
576 // 2. An underscore is escaped with another underscore, i.e. `__`.
577 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
578 std::string mangle_name(const RTLIL::IdString &name)
579 {
580 std::string mangled;
581 bool first = true;
582 for (char c : name.str()) {
583 if (first) {
584 first = false;
585 if (c == '\\')
586 mangled += "p_";
587 else if (c == '$')
588 mangled += "i_";
589 else
590 log_assert(false);
591 } else {
592 if (isalnum(c)) {
593 mangled += c;
594 } else if (c == '_') {
595 mangled += "__";
596 } else {
597 char l = c & 0xf, h = (c >> 4) & 0xf;
598 mangled += '_';
599 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
600 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
601 mangled += '_';
602 }
603 }
604 }
605 return mangled;
606 }
607
608 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
609 {
610 // Class namespace.
611 if (is_blackbox)
612 return "bb_" + mangle_name(name);
613 return mangle_name(name);
614 }
615
616 std::string mangle_memory_name(const RTLIL::IdString &name)
617 {
618 // Class member namespace.
619 return "memory_" + mangle_name(name);
620 }
621
622 std::string mangle_cell_name(const RTLIL::IdString &name)
623 {
624 // Class member namespace.
625 return "cell_" + mangle_name(name);
626 }
627
628 std::string mangle_wire_name(const RTLIL::IdString &name)
629 {
630 // Class member namespace.
631 return mangle_name(name);
632 }
633
634 std::string mangle(const RTLIL::Module *module)
635 {
636 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
637 }
638
639 std::string mangle(const RTLIL::Memory *memory)
640 {
641 return mangle_memory_name(memory->name);
642 }
643
644 std::string mangle(const RTLIL::Cell *cell)
645 {
646 return mangle_cell_name(cell->name);
647 }
648
649 std::string mangle(const RTLIL::Wire *wire)
650 {
651 return mangle_wire_name(wire->name);
652 }
653
654 std::string mangle(RTLIL::SigBit sigbit)
655 {
656 log_assert(sigbit.wire != NULL);
657 if (sigbit.wire->width == 1)
658 return mangle(sigbit.wire);
659 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
660 }
661
662 std::vector<std::string> template_param_names(const RTLIL::Module *module)
663 {
664 if (!module->has_attribute(ID(cxxrtl_template)))
665 return {};
666
667 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
668 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
669
670 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
671 for (const auto &param_name : param_names) {
672 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
673 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
674 // in both Verilog and C++, anyway.)
675 if (!isupper(param_name[0]))
676 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
677 "which does not start with an uppercase letter.\n",
678 log_id(module), param_name.c_str());
679 }
680 return param_names;
681 }
682
683 std::string template_params(const RTLIL::Module *module, bool is_decl)
684 {
685 std::vector<std::string> param_names = template_param_names(module);
686 if (param_names.empty())
687 return "";
688
689 std::string params = "<";
690 bool first = true;
691 for (const auto &param_name : param_names) {
692 if (!first)
693 params += ", ";
694 first = false;
695 if (is_decl)
696 params += "size_t ";
697 params += param_name;
698 }
699 params += ">";
700 return params;
701 }
702
703 std::string template_args(const RTLIL::Cell *cell)
704 {
705 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
706 log_assert(cell_module != nullptr);
707 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
708 return "";
709
710 std::vector<std::string> param_names = template_param_names(cell_module);
711 if (param_names.empty())
712 return "";
713
714 std::string params = "<";
715 bool first = true;
716 for (const auto &param_name : param_names) {
717 if (!first)
718 params += ", ";
719 first = false;
720 params += "/*" + param_name + "=*/";
721 RTLIL::IdString id_param_name = '\\' + param_name;
722 if (!cell->hasParam(id_param_name))
723 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
724 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
725 RTLIL::Const param_value = cell->getParam(id_param_name);
726 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
727 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
728 "is not a positive integer.\n",
729 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
730 params += std::to_string(cell->getParam(id_param_name).as_int());
731 }
732 params += ">";
733 return params;
734 }
735
736 std::string fresh_temporary()
737 {
738 return stringf("tmp_%d", temporary++);
739 }
740
741 void dump_attrs(const RTLIL::AttrObject *object)
742 {
743 for (auto attr : object->attributes) {
744 f << indent << "// " << attr.first.str() << ": ";
745 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
746 f << attr.second.decode_string();
747 } else {
748 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
749 }
750 f << "\n";
751 }
752 }
753
754 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
755 {
756 const int CHUNK_SIZE = 32;
757 f << "{";
758 while (width > 0) {
759 int chunk_width = min(width, CHUNK_SIZE);
760 uint32_t chunk = data.extract(offset, chunk_width).as_int();
761 if (fixed_width)
762 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
763 else
764 f << stringf("%#xu", chunk);
765 if (width > CHUNK_SIZE)
766 f << ',';
767 offset += CHUNK_SIZE;
768 width -= CHUNK_SIZE;
769 }
770 f << "}";
771 }
772
773 void dump_const_init(const RTLIL::Const &data)
774 {
775 dump_const_init(data, data.size());
776 }
777
778 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
779 {
780 f << "value<" << width << ">";
781 dump_const_init(data, width, offset, fixed_width);
782 }
783
784 void dump_const(const RTLIL::Const &data)
785 {
786 dump_const(data, data.size());
787 }
788
789 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs)
790 {
791 if (chunk.wire == NULL) {
792 dump_const(chunk.data, chunk.width, chunk.offset);
793 return false;
794 } else {
795 if (elided_wires.count(chunk.wire)) {
796 log_assert(!is_lhs);
797 const FlowGraph::Node &node = elided_wires[chunk.wire];
798 switch (node.type) {
799 case FlowGraph::Node::Type::CONNECT:
800 dump_connect_elided(node.connect);
801 break;
802 case FlowGraph::Node::Type::CELL_EVAL:
803 log_assert(is_elidable_cell(node.cell->type));
804 dump_cell_elided(node.cell);
805 break;
806 default:
807 log_assert(false);
808 }
809 } else if (unbuffered_wires[chunk.wire]) {
810 f << mangle(chunk.wire);
811 } else {
812 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
813 }
814 if (chunk.width == chunk.wire->width && chunk.offset == 0)
815 return false;
816 else if (chunk.width == 1)
817 f << ".slice<" << chunk.offset << ">()";
818 else
819 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
820 return true;
821 }
822 }
823
824 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs)
825 {
826 if (sig.empty()) {
827 f << "value<0>()";
828 return false;
829 } else if (sig.is_chunk()) {
830 return dump_sigchunk(sig.as_chunk(), is_lhs);
831 } else {
832 dump_sigchunk(*sig.chunks().rbegin(), is_lhs);
833 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
834 f << ".concat(";
835 dump_sigchunk(*it, is_lhs);
836 f << ")";
837 }
838 return true;
839 }
840 }
841
842 void dump_sigspec_lhs(const RTLIL::SigSpec &sig)
843 {
844 dump_sigspec(sig, /*is_lhs=*/true);
845 }
846
847 void dump_sigspec_rhs(const RTLIL::SigSpec &sig)
848 {
849 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
850 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
851 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
852 // type conversion, but only if the expression needs it.
853 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false);
854 if (is_complex)
855 f << ".val()";
856 }
857
858 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
859 {
860 for (auto chunk : sig.chunks()) {
861 if (!chunk.wire || !elided_wires.count(chunk.wire))
862 continue;
863
864 const FlowGraph::Node &node = elided_wires[chunk.wire];
865 switch (node.type) {
866 case FlowGraph::Node::Type::CONNECT:
867 collect_connect(node.connect, cells);
868 break;
869 case FlowGraph::Node::Type::CELL_EVAL:
870 collect_cell_eval(node.cell, cells);
871 break;
872 default:
873 log_assert(false);
874 }
875 }
876 }
877
878 void dump_connect_elided(const RTLIL::SigSig &conn)
879 {
880 dump_sigspec_rhs(conn.second);
881 }
882
883 bool is_connect_elided(const RTLIL::SigSig &conn)
884 {
885 return conn.first.is_wire() && elided_wires.count(conn.first.as_wire());
886 }
887
888 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
889 {
890 if (!is_connect_elided(conn))
891 return;
892
893 collect_sigspec_rhs(conn.second, cells);
894 }
895
896 void dump_connect(const RTLIL::SigSig &conn)
897 {
898 if (is_connect_elided(conn))
899 return;
900
901 f << indent << "// connection\n";
902 f << indent;
903 dump_sigspec_lhs(conn.first);
904 f << " = ";
905 dump_connect_elided(conn);
906 f << ";\n";
907 }
908
909 void dump_cell_sync(const RTLIL::Cell *cell)
910 {
911 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
912 f << indent << "// cell " << cell->name.str() << " syncs\n";
913 for (auto conn : cell->connections())
914 if (cell->output(conn.first))
915 if (is_cxxrtl_sync_port(cell, conn.first)) {
916 f << indent;
917 dump_sigspec_lhs(conn.second);
918 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
919 }
920 }
921
922 void dump_cell_elided(const RTLIL::Cell *cell)
923 {
924 // Unary cells
925 if (is_unary_cell(cell->type)) {
926 f << cell->type.substr(1);
927 if (is_extending_cell(cell->type))
928 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
929 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
930 dump_sigspec_rhs(cell->getPort(ID::A));
931 f << ")";
932 // Binary cells
933 } else if (is_binary_cell(cell->type)) {
934 f << cell->type.substr(1);
935 if (is_extending_cell(cell->type))
936 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
937 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
938 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
939 dump_sigspec_rhs(cell->getPort(ID::A));
940 f << ", ";
941 dump_sigspec_rhs(cell->getPort(ID::B));
942 f << ")";
943 // Muxes
944 } else if (cell->type == ID($mux)) {
945 f << "(";
946 dump_sigspec_rhs(cell->getPort(ID::S));
947 f << " ? ";
948 dump_sigspec_rhs(cell->getPort(ID::B));
949 f << " : ";
950 dump_sigspec_rhs(cell->getPort(ID::A));
951 f << ")";
952 // Parallel (one-hot) muxes
953 } else if (cell->type == ID($pmux)) {
954 int width = cell->getParam(ID::WIDTH).as_int();
955 int s_width = cell->getParam(ID::S_WIDTH).as_int();
956 for (int part = 0; part < s_width; part++) {
957 f << "(";
958 dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
959 f << " ? ";
960 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
961 f << " : ";
962 }
963 dump_sigspec_rhs(cell->getPort(ID::A));
964 for (int part = 0; part < s_width; part++) {
965 f << ")";
966 }
967 // Concats
968 } else if (cell->type == ID($concat)) {
969 dump_sigspec_rhs(cell->getPort(ID::B));
970 f << ".concat(";
971 dump_sigspec_rhs(cell->getPort(ID::A));
972 f << ").val()";
973 // Slices
974 } else if (cell->type == ID($slice)) {
975 dump_sigspec_rhs(cell->getPort(ID::A));
976 f << ".slice<";
977 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
978 f << ",";
979 f << cell->getParam(ID::OFFSET).as_int();
980 f << ">().val()";
981 } else {
982 log_assert(false);
983 }
984 }
985
986 bool is_cell_elided(const RTLIL::Cell *cell)
987 {
988 return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
989 elided_wires.count(cell->getPort(ID::Y).as_wire());
990 }
991
992 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
993 {
994 if (!is_cell_elided(cell))
995 return;
996
997 cells.push_back(cell->name);
998 for (auto port : cell->connections())
999 if (port.first != ID::Y)
1000 collect_sigspec_rhs(port.second, cells);
1001 }
1002
1003 void dump_cell_eval(const RTLIL::Cell *cell)
1004 {
1005 if (is_cell_elided(cell))
1006 return;
1007 if (cell->type == ID($meminit))
1008 return; // Handled elsewhere.
1009
1010 std::vector<RTLIL::IdString> elided_cells;
1011 if (is_elidable_cell(cell->type)) {
1012 for (auto port : cell->connections())
1013 if (port.first != ID::Y)
1014 collect_sigspec_rhs(port.second, elided_cells);
1015 }
1016 if (elided_cells.empty()) {
1017 dump_attrs(cell);
1018 f << indent << "// cell " << cell->name.str() << "\n";
1019 } else {
1020 f << indent << "// cells";
1021 for (auto elided_cell : elided_cells)
1022 f << " " << elided_cell.str();
1023 f << "\n";
1024 }
1025
1026 // Elidable cells
1027 if (is_elidable_cell(cell->type)) {
1028 f << indent;
1029 dump_sigspec_lhs(cell->getPort(ID::Y));
1030 f << " = ";
1031 dump_cell_elided(cell);
1032 f << ";\n";
1033 // Flip-flops
1034 } else if (is_ff_cell(cell->type)) {
1035 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1036 // Edge-sensitive logic
1037 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1038 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1039 if (clk_bit.wire) {
1040 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1041 << mangle(clk_bit) << ") {\n";
1042 } else {
1043 f << indent << "if (false) {\n";
1044 }
1045 inc_indent();
1046 if (cell->hasPort(ID::EN)) {
1047 f << indent << "if (";
1048 dump_sigspec_rhs(cell->getPort(ID::EN));
1049 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1050 inc_indent();
1051 }
1052 f << indent;
1053 dump_sigspec_lhs(cell->getPort(ID::Q));
1054 f << " = ";
1055 dump_sigspec_rhs(cell->getPort(ID::D));
1056 f << ";\n";
1057 if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
1058 dec_indent();
1059 f << indent << "}\n";
1060 }
1061 if (cell->hasPort(ID::SRST)) {
1062 f << indent << "if (";
1063 dump_sigspec_rhs(cell->getPort(ID::SRST));
1064 f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
1065 inc_indent();
1066 f << indent;
1067 dump_sigspec_lhs(cell->getPort(ID::Q));
1068 f << " = ";
1069 dump_const(cell->getParam(ID::SRST_VALUE));
1070 f << ";\n";
1071 dec_indent();
1072 f << indent << "}\n";
1073 }
1074 if (cell->hasPort(ID::EN) && cell->type == ID($sdffce)) {
1075 dec_indent();
1076 f << indent << "}\n";
1077 }
1078 dec_indent();
1079 f << indent << "}\n";
1080 } else if (cell->hasPort(ID::EN)) {
1081 // Level-sensitive logic
1082 f << indent << "if (";
1083 dump_sigspec_rhs(cell->getPort(ID::EN));
1084 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1085 inc_indent();
1086 f << indent;
1087 dump_sigspec_lhs(cell->getPort(ID::Q));
1088 f << " = ";
1089 dump_sigspec_rhs(cell->getPort(ID::D));
1090 f << ";\n";
1091 dec_indent();
1092 f << indent << "}\n";
1093 }
1094 if (cell->hasPort(ID::ARST)) {
1095 // Asynchronous reset (entire coarse cell at once)
1096 f << indent << "if (";
1097 dump_sigspec_rhs(cell->getPort(ID::ARST));
1098 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1099 inc_indent();
1100 f << indent;
1101 dump_sigspec_lhs(cell->getPort(ID::Q));
1102 f << " = ";
1103 dump_const(cell->getParam(ID::ARST_VALUE));
1104 f << ";\n";
1105 dec_indent();
1106 f << indent << "}\n";
1107 }
1108 if (cell->hasPort(ID::SET)) {
1109 // Asynchronous set (for individual bits)
1110 f << indent;
1111 dump_sigspec_lhs(cell->getPort(ID::Q));
1112 f << " = ";
1113 dump_sigspec_lhs(cell->getPort(ID::Q));
1114 f << ".update(";
1115 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1116 f << ", ";
1117 dump_sigspec_rhs(cell->getPort(ID::SET));
1118 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1119 }
1120 if (cell->hasPort(ID::CLR)) {
1121 // Asynchronous clear (for individual bits; priority over set)
1122 f << indent;
1123 dump_sigspec_lhs(cell->getPort(ID::Q));
1124 f << " = ";
1125 dump_sigspec_lhs(cell->getPort(ID::Q));
1126 f << ".update(";
1127 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1128 f << ", ";
1129 dump_sigspec_rhs(cell->getPort(ID::CLR));
1130 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1131 }
1132 // Memory ports
1133 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1134 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1135 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1136 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1137 if (clk_bit.wire) {
1138 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1139 << mangle(clk_bit) << ") {\n";
1140 } else {
1141 f << indent << "if (false) {\n";
1142 }
1143 inc_indent();
1144 }
1145 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1146 std::string valid_index_temp = fresh_temporary();
1147 f << indent << "auto " << valid_index_temp << " = memory_index(";
1148 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1149 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1150 if (cell->type == ID($memrd)) {
1151 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1152 if (has_enable) {
1153 f << indent << "if (";
1154 dump_sigspec_rhs(cell->getPort(ID::EN));
1155 f << ") {\n";
1156 inc_indent();
1157 }
1158 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1159 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1160 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DNDEBUG not
1161 // just for release builds, but also to make sure the simulator (which is presumably embedded in some
1162 // larger program) will never crash the code that calls into it.
1163 //
1164 // If assertions are disabled, out of bounds reads are defined to return zero.
1165 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1166 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1167 inc_indent();
1168 if (writable_memories[memory]) {
1169 std::string lhs_temp = fresh_temporary();
1170 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1171 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1172 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1173 if (!memwr_cells.empty()) {
1174 std::string addr_temp = fresh_temporary();
1175 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1176 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1177 f << ";\n";
1178 std::sort(memwr_cells.begin(), memwr_cells.end(),
1179 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1180 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1181 });
1182 for (auto memwr_cell : memwr_cells) {
1183 f << indent << "if (" << addr_temp << " == ";
1184 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1185 f << ") {\n";
1186 inc_indent();
1187 f << indent << lhs_temp << " = " << lhs_temp;
1188 f << ".update(";
1189 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1190 f << ", ";
1191 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1192 f << ");\n";
1193 dec_indent();
1194 f << indent << "}\n";
1195 }
1196 }
1197 f << indent;
1198 dump_sigspec_lhs(cell->getPort(ID::DATA));
1199 f << " = " << lhs_temp << ";\n";
1200 } else {
1201 f << indent;
1202 dump_sigspec_lhs(cell->getPort(ID::DATA));
1203 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1204 }
1205 dec_indent();
1206 f << indent << "} else {\n";
1207 inc_indent();
1208 f << indent;
1209 dump_sigspec_lhs(cell->getPort(ID::DATA));
1210 f << " = value<" << memory->width << "> {};\n";
1211 dec_indent();
1212 f << indent << "}\n";
1213 if (has_enable) {
1214 dec_indent();
1215 f << indent << "}\n";
1216 }
1217 } else /*if (cell->type == ID($memwr))*/ {
1218 log_assert(writable_memories[memory]);
1219 // See above for rationale of having both the assert and the condition.
1220 //
1221 // If assertions are disabled, out of bounds writes are defined to do nothing.
1222 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1223 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1224 inc_indent();
1225 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1226 dump_sigspec_rhs(cell->getPort(ID::DATA));
1227 f << ", ";
1228 dump_sigspec_rhs(cell->getPort(ID::EN));
1229 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1230 dec_indent();
1231 f << indent << "}\n";
1232 }
1233 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1234 dec_indent();
1235 f << indent << "}\n";
1236 }
1237 // Internal cells
1238 } else if (is_internal_cell(cell->type)) {
1239 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1240 // User cells
1241 } else {
1242 log_assert(cell->known());
1243 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1244 for (auto conn : cell->connections())
1245 if (cell->input(conn.first) && !cell->output(conn.first)) {
1246 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = ";
1247 dump_sigspec_rhs(conn.second);
1248 f << ";\n";
1249 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1250 // Until we have proper clock tree detection, this really awful hack that opportunistically
1251 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1252 // be if only one clock edge was simulated by replacing:
1253 // top.p_clk = value<1>{0u}; top.step();
1254 // top.p_clk = value<1>{1u}; top.step();
1255 // with:
1256 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1257 // Don't rely on this; it will be removed without warning.
1258 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1259 if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) {
1260 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1261 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1262 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1263 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1264 }
1265 }
1266 }
1267 } else if (cell->input(conn.first)) {
1268 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = ";
1269 dump_sigspec_rhs(conn.second);
1270 f << ";\n";
1271 }
1272 auto assign_from_outputs = [&](bool cell_converged) {
1273 for (auto conn : cell->connections()) {
1274 if (cell->output(conn.first)) {
1275 if (conn.second.empty())
1276 continue; // ignore disconnected ports
1277 if (is_cxxrtl_sync_port(cell, conn.first))
1278 continue; // fully sync ports are handled in CELL_SYNC nodes
1279 f << indent;
1280 dump_sigspec_lhs(conn.second);
1281 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1282 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1283 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1284 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1285 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1286 // and consider the fate of the localized wires that used to be output ports.)
1287 //
1288 // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell
1289 // (which may be late bound) will converge immediately. Because of this, the choice between using .curr
1290 // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime.
1291 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1292 f << ".next;\n";
1293 else
1294 f << ".curr;\n";
1295 }
1296 }
1297 };
1298 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1299 inc_indent();
1300 assign_from_outputs(/*cell_converged=*/true);
1301 dec_indent();
1302 f << indent << "} else {\n";
1303 inc_indent();
1304 f << indent << "converged = false;\n";
1305 assign_from_outputs(/*cell_converged=*/false);
1306 dec_indent();
1307 f << indent << "}\n";
1308 }
1309 }
1310
1311 void dump_assign(const RTLIL::SigSig &sigsig)
1312 {
1313 f << indent;
1314 dump_sigspec_lhs(sigsig.first);
1315 f << " = ";
1316 dump_sigspec_rhs(sigsig.second);
1317 f << ";\n";
1318 }
1319
1320 void dump_case_rule(const RTLIL::CaseRule *rule)
1321 {
1322 for (auto action : rule->actions)
1323 dump_assign(action);
1324 for (auto switch_ : rule->switches)
1325 dump_switch_rule(switch_);
1326 }
1327
1328 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1329 {
1330 // The switch attributes are printed before the switch condition is captured.
1331 dump_attrs(rule);
1332 std::string signal_temp = fresh_temporary();
1333 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1334 dump_sigspec(rule->signal, /*is_lhs=*/false);
1335 f << ";\n";
1336
1337 bool first = true;
1338 for (auto case_ : rule->cases) {
1339 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1340 dump_attrs(rule);
1341 f << indent;
1342 if (!first)
1343 f << "} else ";
1344 first = false;
1345 if (!case_->compare.empty()) {
1346 f << "if (";
1347 bool first = true;
1348 for (auto &compare : case_->compare) {
1349 if (!first)
1350 f << " || ";
1351 first = false;
1352 if (compare.is_fully_def()) {
1353 f << signal_temp << " == ";
1354 dump_sigspec(compare, /*is_lhs=*/false);
1355 } else if (compare.is_fully_const()) {
1356 RTLIL::Const compare_mask, compare_value;
1357 for (auto bit : compare.as_const()) {
1358 switch (bit) {
1359 case RTLIL::S0:
1360 case RTLIL::S1:
1361 compare_mask.bits.push_back(RTLIL::S1);
1362 compare_value.bits.push_back(bit);
1363 break;
1364
1365 case RTLIL::Sx:
1366 case RTLIL::Sz:
1367 case RTLIL::Sa:
1368 compare_mask.bits.push_back(RTLIL::S0);
1369 compare_value.bits.push_back(RTLIL::S0);
1370 break;
1371
1372 default:
1373 log_assert(false);
1374 }
1375 }
1376 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1377 dump_const(compare_mask);
1378 f << ") == ";
1379 dump_const(compare_value);
1380 } else {
1381 log_assert(false);
1382 }
1383 }
1384 f << ") ";
1385 }
1386 f << "{\n";
1387 inc_indent();
1388 dump_case_rule(case_);
1389 dec_indent();
1390 }
1391 f << indent << "}\n";
1392 }
1393
1394 void dump_process(const RTLIL::Process *proc)
1395 {
1396 dump_attrs(proc);
1397 f << indent << "// process " << proc->name.str() << "\n";
1398 // The case attributes (for root case) are always empty.
1399 log_assert(proc->root_case.attributes.empty());
1400 dump_case_rule(&proc->root_case);
1401 for (auto sync : proc->syncs) {
1402 RTLIL::SigBit sync_bit;
1403 if (!sync->signal.empty()) {
1404 sync_bit = sync->signal[0];
1405 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1406 }
1407
1408 pool<std::string> events;
1409 switch (sync->type) {
1410 case RTLIL::STp:
1411 log_assert(sync_bit.wire != nullptr);
1412 events.insert("posedge_" + mangle(sync_bit));
1413 break;
1414 case RTLIL::STn:
1415 log_assert(sync_bit.wire != nullptr);
1416 events.insert("negedge_" + mangle(sync_bit));
1417 break;
1418 case RTLIL::STe:
1419 log_assert(sync_bit.wire != nullptr);
1420 events.insert("posedge_" + mangle(sync_bit));
1421 events.insert("negedge_" + mangle(sync_bit));
1422 break;
1423
1424 case RTLIL::STa:
1425 events.insert("true");
1426 break;
1427
1428 case RTLIL::ST0:
1429 case RTLIL::ST1:
1430 case RTLIL::STg:
1431 case RTLIL::STi:
1432 log_assert(false);
1433 }
1434 if (!events.empty()) {
1435 f << indent << "if (";
1436 bool first = true;
1437 for (auto &event : events) {
1438 if (!first)
1439 f << " || ";
1440 first = false;
1441 f << event;
1442 }
1443 f << ") {\n";
1444 inc_indent();
1445 for (auto action : sync->actions)
1446 dump_assign(action);
1447 dec_indent();
1448 f << indent << "}\n";
1449 }
1450 }
1451 }
1452
1453 void dump_wire(const RTLIL::Wire *wire, bool is_local_context)
1454 {
1455 if (elided_wires.count(wire))
1456 return;
1457
1458 if (localized_wires[wire] && is_local_context) {
1459 dump_attrs(wire);
1460 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1461 }
1462 if (!localized_wires[wire] && !is_local_context) {
1463 std::string width;
1464 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1465 width = wire->get_string_attribute(ID(cxxrtl_width));
1466 } else {
1467 width = std::to_string(wire->width);
1468 }
1469
1470 dump_attrs(wire);
1471 f << indent;
1472 if (wire->port_input && wire->port_output)
1473 f << "/*inout*/ ";
1474 else if (wire->port_input)
1475 f << "/*input*/ ";
1476 else if (wire->port_output)
1477 f << "/*output*/ ";
1478 f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1479 if (wire->has_attribute(ID::init)) {
1480 f << " ";
1481 dump_const_init(wire->attributes.at(ID::init));
1482 }
1483 f << ";\n";
1484 if (edge_wires[wire]) {
1485 if (unbuffered_wires[wire]) {
1486 f << indent << "value<" << width << "> prev_" << mangle(wire);
1487 if (wire->has_attribute(ID::init)) {
1488 f << " ";
1489 dump_const_init(wire->attributes.at(ID::init));
1490 }
1491 f << ";\n";
1492 }
1493 for (auto edge_type : edge_types) {
1494 if (edge_type.first.wire == wire) {
1495 std::string prev, next;
1496 if (unbuffered_wires[wire]) {
1497 prev = "prev_" + mangle(edge_type.first.wire);
1498 next = mangle(edge_type.first.wire);
1499 } else {
1500 prev = mangle(edge_type.first.wire) + ".curr";
1501 next = mangle(edge_type.first.wire) + ".next";
1502 }
1503 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1504 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1505 if (edge_type.second != RTLIL::STn) {
1506 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1507 inc_indent();
1508 f << indent << "return !" << prev << " && " << next << ";\n";
1509 dec_indent();
1510 f << indent << "}\n";
1511 }
1512 if (edge_type.second != RTLIL::STp) {
1513 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1514 inc_indent();
1515 f << indent << "return " << prev << " && !" << next << ";\n";
1516 dec_indent();
1517 f << indent << "}\n";
1518 }
1519 }
1520 }
1521 }
1522 }
1523 }
1524
1525 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1526 {
1527 vector<const RTLIL::Cell*> init_cells;
1528 for (auto cell : module->cells())
1529 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1530 init_cells.push_back(cell);
1531
1532 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1533 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1534 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1535 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1536 });
1537
1538 dump_attrs(memory);
1539 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1540 << " { " << memory->size << "u";
1541 if (init_cells.empty()) {
1542 f << " };\n";
1543 } else {
1544 f << ",\n";
1545 inc_indent();
1546 for (auto cell : init_cells) {
1547 dump_attrs(cell);
1548 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1549 size_t width = cell->getParam(ID::WIDTH).as_int();
1550 size_t words = cell->getParam(ID::WORDS).as_int();
1551 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1552 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1553 inc_indent();
1554 for (size_t n = 0; n < words; n++) {
1555 if (n % 4 == 0)
1556 f << "\n" << indent;
1557 else
1558 f << " ";
1559 dump_const(data, width, n * width, /*fixed_width=*/true);
1560 f << ",";
1561 }
1562 dec_indent();
1563 f << "\n" << indent << "}},\n";
1564 }
1565 dec_indent();
1566 f << indent << "};\n";
1567 }
1568 }
1569
1570 void dump_eval_method(RTLIL::Module *module)
1571 {
1572 inc_indent();
1573 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1574 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1575 for (auto wire : module->wires()) {
1576 if (edge_wires[wire]) {
1577 for (auto edge_type : edge_types) {
1578 if (edge_type.first.wire == wire) {
1579 if (edge_type.second != RTLIL::STn) {
1580 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1581 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1582 }
1583 if (edge_type.second != RTLIL::STp) {
1584 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1585 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1586 }
1587 }
1588 }
1589 }
1590 }
1591 for (auto wire : module->wires())
1592 dump_wire(wire, /*is_local_context=*/true);
1593 for (auto node : schedule[module]) {
1594 switch (node.type) {
1595 case FlowGraph::Node::Type::CONNECT:
1596 dump_connect(node.connect);
1597 break;
1598 case FlowGraph::Node::Type::CELL_SYNC:
1599 dump_cell_sync(node.cell);
1600 break;
1601 case FlowGraph::Node::Type::CELL_EVAL:
1602 dump_cell_eval(node.cell);
1603 break;
1604 case FlowGraph::Node::Type::PROCESS:
1605 dump_process(node.process);
1606 break;
1607 }
1608 }
1609 }
1610 f << indent << "return converged;\n";
1611 dec_indent();
1612 }
1613
1614 void dump_commit_method(RTLIL::Module *module)
1615 {
1616 inc_indent();
1617 f << indent << "bool changed = false;\n";
1618 for (auto wire : module->wires()) {
1619 if (elided_wires.count(wire))
1620 continue;
1621 if (unbuffered_wires[wire]) {
1622 if (edge_wires[wire])
1623 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1624 continue;
1625 }
1626 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1627 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1628 }
1629 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1630 for (auto memory : module->memories) {
1631 if (!writable_memories[memory.second])
1632 continue;
1633 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1634 }
1635 for (auto cell : module->cells()) {
1636 if (is_internal_cell(cell->type))
1637 continue;
1638 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1639 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1640 }
1641 }
1642 f << indent << "return changed;\n";
1643 dec_indent();
1644 }
1645
1646 void dump_debug_info_method(RTLIL::Module *module)
1647 {
1648 size_t count_public_wires = 0;
1649 size_t count_const_wires = 0;
1650 size_t count_alias_wires = 0;
1651 size_t count_member_wires = 0;
1652 size_t count_skipped_wires = 0;
1653 size_t count_driven_sync = 0;
1654 size_t count_driven_comb = 0;
1655 size_t count_undriven = 0;
1656 size_t count_mixed_driver = 0;
1657 inc_indent();
1658 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1659 for (auto wire : module->wires()) {
1660 if (wire->name[0] != '\\')
1661 continue;
1662 if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
1663 continue;
1664 count_public_wires++;
1665 if (debug_const_wires.count(wire)) {
1666 // Wire tied to a constant
1667 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1668 dump_const(debug_const_wires[wire]);
1669 f << ";\n";
1670 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1671 f << ", debug_item(const_" << mangle(wire) << ", ";
1672 f << wire->start_offset << "));\n";
1673 count_const_wires++;
1674 } else if (debug_alias_wires.count(wire)) {
1675 // Alias of a member wire
1676 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1677 f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
1678 f << wire->start_offset << "));\n";
1679 count_alias_wires++;
1680 } else if (!localized_wires.count(wire)) {
1681 // Member wire
1682 std::vector<std::string> flags;
1683
1684 if (wire->port_input && wire->port_output)
1685 flags.push_back("INOUT");
1686 else if (wire->port_input)
1687 flags.push_back("INPUT");
1688 else if (wire->port_output)
1689 flags.push_back("OUTPUT");
1690
1691 bool has_driven_sync = false;
1692 bool has_driven_comb = false;
1693 bool has_undriven = false;
1694 SigSpec sig(wire);
1695 for (auto bit : sig.bits())
1696 if (!bit_has_state.count(bit))
1697 has_undriven = true;
1698 else if (bit_has_state[bit])
1699 has_driven_sync = true;
1700 else
1701 has_driven_comb = true;
1702 if (has_driven_sync)
1703 flags.push_back("DRIVEN_SYNC");
1704 if (has_driven_sync && !has_driven_comb && !has_undriven)
1705 count_driven_sync++;
1706 if (has_driven_comb)
1707 flags.push_back("DRIVEN_COMB");
1708 if (!has_driven_sync && has_driven_comb && !has_undriven)
1709 count_driven_comb++;
1710 if (has_undriven)
1711 flags.push_back("UNDRIVEN");
1712 if (!has_driven_sync && !has_driven_comb && has_undriven)
1713 count_undriven++;
1714 if (has_driven_sync + has_driven_comb + has_undriven > 1)
1715 count_mixed_driver++;
1716
1717 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1718 f << ", debug_item(" << mangle(wire) << ", ";
1719 f << wire->start_offset;
1720 bool first = true;
1721 for (auto flag : flags) {
1722 if (first) {
1723 first = false;
1724 f << ", ";
1725 } else {
1726 f << "|";
1727 }
1728 f << "debug_item::" << flag;
1729 }
1730 f << "));\n";
1731 count_member_wires++;
1732 } else {
1733 count_skipped_wires++;
1734 }
1735 }
1736 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1737 for (auto &memory_it : module->memories) {
1738 if (memory_it.first[0] != '\\')
1739 continue;
1740 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1741 f << ", debug_item(" << mangle(memory_it.second) << ", ";
1742 f << memory_it.second->start_offset << "));\n";
1743 }
1744 for (auto cell : module->cells()) {
1745 if (is_internal_cell(cell->type))
1746 continue;
1747 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1748 f << indent << mangle(cell) << access << "debug_info(items, ";
1749 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1750 }
1751 }
1752 dec_indent();
1753
1754 log_debug("Debug information statistics for module `%s':\n", log_id(module));
1755 log_debug(" Public wires: %zu, of which:\n", count_public_wires);
1756 log_debug(" Const wires: %zu\n", count_const_wires);
1757 log_debug(" Alias wires: %zu\n", count_alias_wires);
1758 log_debug(" Member wires: %zu, of which:\n", count_member_wires);
1759 log_debug(" Driven sync: %zu\n", count_driven_sync);
1760 log_debug(" Driven comb: %zu\n", count_driven_comb);
1761 log_debug(" Undriven: %zu\n", count_undriven);
1762 log_debug(" Mixed driver: %zu\n", count_mixed_driver);
1763 log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
1764 }
1765
1766 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1767 {
1768 if (metadata_map.empty()) {
1769 f << "metadata_map()";
1770 return;
1771 }
1772 f << "metadata_map({\n";
1773 inc_indent();
1774 for (auto metadata_item : metadata_map) {
1775 if (!metadata_item.first.begins_with("\\"))
1776 continue;
1777 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1778 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1779 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1780 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1781 f << escape_cxx_string(metadata_item.second.decode_string());
1782 } else {
1783 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1784 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1785 f << "u";
1786 }
1787 f << " },\n";
1788 }
1789 dec_indent();
1790 f << indent << "})";
1791 }
1792
1793 void dump_module_intf(RTLIL::Module *module)
1794 {
1795 dump_attrs(module);
1796 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1797 if (module->has_attribute(ID(cxxrtl_template)))
1798 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1799 f << indent << "struct " << mangle(module) << " : public module {\n";
1800 inc_indent();
1801 for (auto wire : module->wires()) {
1802 if (wire->port_id != 0)
1803 dump_wire(wire, /*is_local_context=*/false);
1804 }
1805 f << "\n";
1806 f << indent << "bool eval() override {\n";
1807 dump_eval_method(module);
1808 f << indent << "}\n";
1809 f << "\n";
1810 f << indent << "bool commit() override {\n";
1811 dump_commit_method(module);
1812 f << indent << "}\n";
1813 f << "\n";
1814 if (debug_info) {
1815 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1816 dump_debug_info_method(module);
1817 f << indent << "}\n";
1818 f << "\n";
1819 }
1820 f << indent << "static std::unique_ptr<" << mangle(module);
1821 f << template_params(module, /*is_decl=*/false) << "> ";
1822 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1823 dec_indent();
1824 f << indent << "}; // struct " << mangle(module) << "\n";
1825 f << "\n";
1826 if (blackbox_specializations.count(module)) {
1827 // If templated black boxes are used, the constructor of any module which includes the black box cell
1828 // (which calls the declared but not defined in the generated code `create` function) may only be used
1829 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1830 // a forward-declared explicit specialization.
1831 //
1832 // Option (b) makes it possible to have the generated code and the black box implementation in different
1833 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1834 // a specialization for every combination of parameters the generated code may use; but since the main
1835 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1836 // be very few such combinations anyway.
1837 for (auto specialization : blackbox_specializations[module]) {
1838 f << indent << "template<>\n";
1839 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1840 f << mangle(module) << specialization << "::";
1841 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1842 f << "\n";
1843 }
1844 }
1845 } else {
1846 f << indent << "struct " << mangle(module) << " : public module {\n";
1847 inc_indent();
1848 for (auto wire : module->wires())
1849 dump_wire(wire, /*is_local_context=*/false);
1850 f << "\n";
1851 bool has_memories = false;
1852 for (auto memory : module->memories) {
1853 dump_memory(module, memory.second);
1854 has_memories = true;
1855 }
1856 if (has_memories)
1857 f << "\n";
1858 bool has_cells = false;
1859 for (auto cell : module->cells()) {
1860 if (is_internal_cell(cell->type))
1861 continue;
1862 dump_attrs(cell);
1863 RTLIL::Module *cell_module = module->design->module(cell->type);
1864 log_assert(cell_module != nullptr);
1865 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1866 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1867 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1868 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1869 dump_metadata_map(cell->parameters);
1870 f << ", ";
1871 dump_metadata_map(cell->attributes);
1872 f << ");\n";
1873 } else {
1874 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1875 }
1876 has_cells = true;
1877 }
1878 if (has_cells)
1879 f << "\n";
1880 f << indent << mangle(module) << "() {}\n";
1881 if (has_cells) {
1882 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) :\n";
1883 bool first = true;
1884 for (auto cell : module->cells()) {
1885 if (is_internal_cell(cell->type))
1886 continue;
1887 if (first) {
1888 first = false;
1889 } else {
1890 f << ",\n";
1891 }
1892 RTLIL::Module *cell_module = module->design->module(cell->type);
1893 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1894 f << indent << " " << mangle(cell) << "(std::move(other." << mangle(cell) << "))";
1895 } else {
1896 f << indent << " " << mangle(cell) << "(adopt {}, std::move(other." << mangle(cell) << "))";
1897 }
1898 }
1899 f << " {\n";
1900 inc_indent();
1901 for (auto cell : module->cells()) {
1902 if (is_internal_cell(cell->type))
1903 continue;
1904 RTLIL::Module *cell_module = module->design->module(cell->type);
1905 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
1906 f << indent << mangle(cell) << "->reset();\n";
1907 }
1908 dec_indent();
1909 f << indent << "}\n";
1910 } else {
1911 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) {}\n";
1912 }
1913 f << "\n";
1914 f << indent << "void reset() override {\n";
1915 inc_indent();
1916 f << indent << "*this = " << mangle(module) << "(adopt {}, std::move(*this));\n";
1917 dec_indent();
1918 f << indent << "}\n";
1919 f << "\n";
1920 f << indent << "bool eval() override;\n";
1921 f << indent << "bool commit() override;\n";
1922 if (debug_info)
1923 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
1924 dec_indent();
1925 f << indent << "}; // struct " << mangle(module) << "\n";
1926 f << "\n";
1927 }
1928 }
1929
1930 void dump_module_impl(RTLIL::Module *module)
1931 {
1932 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1933 return;
1934 f << indent << "bool " << mangle(module) << "::eval() {\n";
1935 dump_eval_method(module);
1936 f << indent << "}\n";
1937 f << "\n";
1938 f << indent << "bool " << mangle(module) << "::commit() {\n";
1939 dump_commit_method(module);
1940 f << indent << "}\n";
1941 f << "\n";
1942 if (debug_info) {
1943 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
1944 dump_debug_info_method(module);
1945 f << indent << "}\n";
1946 f << "\n";
1947 }
1948 }
1949
1950 void dump_design(RTLIL::Design *design)
1951 {
1952 RTLIL::Module *top_module = nullptr;
1953 std::vector<RTLIL::Module*> modules;
1954 TopoSort<RTLIL::Module*> topo_design;
1955 for (auto module : design->modules()) {
1956 if (!design->selected_module(module))
1957 continue;
1958 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1959 modules.push_back(module); // cxxrtl blackboxes first
1960 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
1961 continue;
1962 if (module->get_bool_attribute(ID::top))
1963 top_module = module;
1964
1965 topo_design.node(module);
1966 for (auto cell : module->cells()) {
1967 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
1968 continue;
1969 RTLIL::Module *cell_module = design->module(cell->type);
1970 log_assert(cell_module != nullptr);
1971 topo_design.edge(cell_module, module);
1972 }
1973 }
1974 bool no_loops = topo_design.sort();
1975 log_assert(no_loops);
1976 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
1977
1978 if (split_intf) {
1979 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
1980 std::string include_guard = design_ns + "_header";
1981 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
1982
1983 f << "#ifndef " << include_guard << "\n";
1984 f << "#define " << include_guard << "\n";
1985 f << "\n";
1986 if (top_module != nullptr && debug_info) {
1987 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
1988 f << "\n";
1989 f << "#ifdef __cplusplus\n";
1990 f << "extern \"C\" {\n";
1991 f << "#endif\n";
1992 f << "\n";
1993 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
1994 f << "\n";
1995 f << "#ifdef __cplusplus\n";
1996 f << "}\n";
1997 f << "#endif\n";
1998 f << "\n";
1999 } else {
2000 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
2001 f << "\n";
2002 }
2003 f << "#ifdef __cplusplus\n";
2004 f << "\n";
2005 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2006 f << "\n";
2007 f << "using namespace cxxrtl;\n";
2008 f << "\n";
2009 f << "namespace " << design_ns << " {\n";
2010 f << "\n";
2011 for (auto module : modules)
2012 dump_module_intf(module);
2013 f << "} // namespace " << design_ns << "\n";
2014 f << "\n";
2015 f << "#endif // __cplusplus\n";
2016 f << "\n";
2017 f << "#endif\n";
2018 *intf_f << f.str(); f.str("");
2019 }
2020
2021 if (split_intf)
2022 f << "#include \"" << intf_filename << "\"\n";
2023 else
2024 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2025 f << "\n";
2026 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
2027 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2028 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
2029 f << "#endif\n";
2030 f << "\n";
2031 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2032 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
2033 f << "#endif\n";
2034 f << "\n";
2035 f << "using namespace cxxrtl_yosys;\n";
2036 f << "\n";
2037 f << "namespace " << design_ns << " {\n";
2038 f << "\n";
2039 for (auto module : modules) {
2040 if (!split_intf)
2041 dump_module_intf(module);
2042 dump_module_impl(module);
2043 }
2044 f << "} // namespace " << design_ns << "\n";
2045 f << "\n";
2046 if (top_module != nullptr && debug_info) {
2047 f << "extern \"C\"\n";
2048 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
2049 inc_indent();
2050 std::string top_type = design_ns + "::" + mangle(top_module);
2051 f << indent << "return new _cxxrtl_toplevel { ";
2052 f << "std::unique_ptr<" << top_type << ">(new " + top_type + ")";
2053 f << " };\n";
2054 dec_indent();
2055 f << "}\n";
2056 }
2057
2058 *impl_f << f.str(); f.str("");
2059 }
2060
2061 // Edge-type sync rules require us to emit edge detectors, which require coordination between
2062 // eval and commit phases. To do this we need to collect them upfront.
2063 //
2064 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
2065 // operate at wire bit granularity; it is possible to have code similar to:
2066 // wire [3:0] clocks;
2067 // always @(posedge clocks[0]) ...
2068 // To handle this we track edge sensitivity both for wires and wire bits.
2069 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
2070 {
2071 signal = sigmap(signal);
2072 log_assert(signal.is_wire() && signal.is_bit());
2073 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
2074
2075 RTLIL::SigBit sigbit = signal[0];
2076 if (!edge_types.count(sigbit))
2077 edge_types[sigbit] = type;
2078 else if (edge_types[sigbit] != type)
2079 edge_types[sigbit] = RTLIL::STe;
2080 edge_wires.insert(signal.as_wire());
2081 }
2082
2083 void analyze_design(RTLIL::Design *design)
2084 {
2085 bool has_feedback_arcs = false;
2086 bool has_buffered_comb_wires = false;
2087
2088 for (auto module : design->modules()) {
2089 if (!design->selected_module(module))
2090 continue;
2091
2092 SigMap &sigmap = sigmaps[module];
2093 sigmap.set(module);
2094
2095 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
2096 for (auto port : module->ports) {
2097 RTLIL::Wire *wire = module->wire(port);
2098 if (wire->port_input && !wire->port_output)
2099 unbuffered_wires.insert(wire);
2100 if (wire->has_attribute(ID(cxxrtl_edge))) {
2101 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
2102 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
2103 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
2104 log_id(module), log_signal(wire));
2105
2106 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
2107 for (int i = 0; i < GetSize(wire); i++) {
2108 RTLIL::SigSpec wire_sig = wire;
2109 switch (edges[i]) {
2110 case '-': break;
2111 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
2112 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
2113 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
2114 default:
2115 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
2116 "other than '-', 'p', 'n', or 'a'.\n",
2117 log_id(module), log_signal(wire));
2118 }
2119 }
2120 }
2121 }
2122
2123 // Black boxes converge by default, since their implementations are quite unlikely to require
2124 // internal propagation of comb signals.
2125 eval_converges[module] = true;
2126 continue;
2127 }
2128
2129 FlowGraph flow;
2130
2131 for (auto conn : module->connections())
2132 flow.add_node(conn);
2133
2134 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
2135 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
2136 pool<const RTLIL::Cell*>> memwr_per_domain;
2137 for (auto cell : module->cells()) {
2138 if (!cell->known())
2139 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2140
2141 RTLIL::Module *cell_module = design->module(cell->type);
2142 if (cell_module &&
2143 cell_module->get_blackbox_attribute() &&
2144 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2145 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2146
2147 if (cell_module &&
2148 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2149 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2150 blackbox_specializations[cell_module].insert(template_args(cell));
2151
2152 FlowGraph::Node *node = flow.add_node(cell);
2153
2154 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2155 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
2156 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2157 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2158 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2159 }
2160 // Similar for memory port cells.
2161 if (cell->type.in(ID($memrd), ID($memwr))) {
2162 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2163 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2164 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2165 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2166 }
2167 memrw_cell_nodes[cell] = node;
2168 }
2169 // Optimize access to read-only memories.
2170 if (cell->type == ID($memwr))
2171 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2172 // Collect groups of memory write ports in the same domain.
2173 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2174 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2175 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2176 memwr_per_domain[{clk_bit, memory}].insert(cell);
2177 }
2178 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2179 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2180 if (cell->type.in(ID($mem)))
2181 log_assert(false);
2182 }
2183 for (auto cell : module->cells()) {
2184 // Collect groups of memory write ports read by every transparent read port.
2185 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2186 cell->getParam(ID::TRANSPARENT).as_bool()) {
2187 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2188 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2189 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2190 transparent_for[cell].insert(memwr_cell);
2191 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2192 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2193 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2194 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2195 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2196 }
2197 }
2198 }
2199
2200 for (auto proc : module->processes) {
2201 flow.add_node(proc.second);
2202
2203 for (auto sync : proc.second->syncs)
2204 switch (sync->type) {
2205 // Edge-type sync rules require pre-registration.
2206 case RTLIL::STp:
2207 case RTLIL::STn:
2208 case RTLIL::STe:
2209 register_edge_signal(sigmap, sync->signal, sync->type);
2210 break;
2211
2212 // Level-type sync rules require no special handling.
2213 case RTLIL::ST0:
2214 case RTLIL::ST1:
2215 case RTLIL::STa:
2216 break;
2217
2218 case RTLIL::STg:
2219 log_cmd_error("Global clock is not supported.\n");
2220
2221 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2222 // attribute regardless of input.
2223 case RTLIL::STi:
2224 log_assert(false);
2225 }
2226 }
2227
2228 for (auto wire : module->wires()) {
2229 if (!flow.is_elidable(wire)) continue;
2230 if (wire->port_id != 0) continue;
2231 if (wire->get_bool_attribute(ID::keep)) continue;
2232 if (wire->name.begins_with("$") && !elide_internal) continue;
2233 if (wire->name.begins_with("\\") && !elide_public) continue;
2234 if (edge_wires[wire]) continue;
2235 if (flow.wire_comb_defs[wire].size() > 1)
2236 log_cmd_error("Wire %s.%s has multiple drivers.\n", log_id(module), log_id(wire));
2237 log_assert(flow.wire_comb_defs[wire].size() == 1);
2238 elided_wires[wire] = **flow.wire_comb_defs[wire].begin();
2239 }
2240
2241 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2242 for (auto wire_comb_def : flow.wire_comb_defs)
2243 for (auto node : wire_comb_def.second)
2244 node_defs[node].insert(wire_comb_def.first);
2245
2246 Scheduler<FlowGraph::Node> scheduler;
2247 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2248 for (auto node : flow.nodes)
2249 node_map[node] = scheduler.add(node);
2250 for (auto node_def : node_defs) {
2251 auto vertex = node_map[node_def.first];
2252 for (auto wire : node_def.second)
2253 for (auto succ_node : flow.wire_uses[wire]) {
2254 auto succ_vertex = node_map[succ_node];
2255 vertex->succs.insert(succ_vertex);
2256 succ_vertex->preds.insert(vertex);
2257 }
2258 }
2259
2260 auto eval_order = scheduler.schedule();
2261 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2262 pool<const RTLIL::Wire*> feedback_wires;
2263 for (auto vertex : eval_order) {
2264 auto node = vertex->data;
2265 schedule[module].push_back(*node);
2266 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2267 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2268 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2269 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2270 evaluated.insert(node);
2271 for (auto wire : node_defs[node])
2272 for (auto succ_node : flow.wire_uses[wire])
2273 if (evaluated[succ_node]) {
2274 feedback_wires.insert(wire);
2275 // Feedback wires may never be elided because feedback requires state, but the point of elision
2276 // (and localization) is to eliminate state.
2277 elided_wires.erase(wire);
2278 }
2279 }
2280
2281 if (!feedback_wires.empty()) {
2282 has_feedback_arcs = true;
2283 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2284 for (auto wire : feedback_wires)
2285 log(" %s\n", log_id(wire));
2286 }
2287
2288 for (auto wire : module->wires()) {
2289 if (feedback_wires[wire]) continue;
2290 if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
2291 if (wire->name.begins_with("$") && !unbuffer_internal) continue;
2292 if (wire->name.begins_with("\\") && !unbuffer_public) continue;
2293 if (flow.wire_sync_defs.count(wire) > 0) continue;
2294 unbuffered_wires.insert(wire);
2295 if (edge_wires[wire]) continue;
2296 if (wire->get_bool_attribute(ID::keep)) continue;
2297 if (wire->port_input || wire->port_output) continue;
2298 if (wire->name.begins_with("$") && !localize_internal) continue;
2299 if (wire->name.begins_with("\\") && !localize_public) continue;
2300 localized_wires.insert(wire);
2301 }
2302
2303 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2304 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2305 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2306 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2307 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2308 // also require more than one delta cycle to converge.
2309 pool<const RTLIL::Wire*> buffered_comb_wires;
2310 for (auto wire : module->wires()) {
2311 if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
2312 buffered_comb_wires.insert(wire);
2313 }
2314 if (!buffered_comb_wires.empty()) {
2315 has_buffered_comb_wires = true;
2316 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2317 for (auto wire : buffered_comb_wires)
2318 log(" %s\n", log_id(wire));
2319 }
2320
2321 eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
2322
2323 for (auto item : flow.bit_has_state)
2324 bit_has_state.insert(item);
2325
2326 if (debug_info) {
2327 // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
2328 // at essentially zero additional cost.
2329 //
2330 // Note that the information collected here can't be used for optimizing the netlist: debug information queries
2331 // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
2332 for (auto wire : module->wires()) {
2333 if (wire->name[0] != '\\')
2334 continue;
2335 if (!unbuffered_wires[wire])
2336 continue;
2337 const RTLIL::Wire *wire_it = wire;
2338 while (1) {
2339 if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it]))
2340 break; // not an alias: complex def
2341 log_assert(flow.wire_comb_defs[wire_it].size() == 1);
2342 FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin();
2343 if (node->type != FlowGraph::Node::Type::CONNECT)
2344 break; // not an alias: def by cell
2345 RTLIL::SigSpec rhs_sig = node->connect.second;
2346 if (rhs_sig.is_wire()) {
2347 RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
2348 if (unbuffered_wires[rhs_wire]) {
2349 wire_it = rhs_wire; // maybe an alias
2350 } else {
2351 debug_alias_wires[wire] = rhs_wire; // is an alias
2352 break;
2353 }
2354 } else if (rhs_sig.is_fully_const()) {
2355 debug_const_wires[wire] = rhs_sig.as_const(); // is a const
2356 break;
2357 } else {
2358 break; // not an alias: complex rhs
2359 }
2360 }
2361 }
2362 }
2363 }
2364 if (has_feedback_arcs || has_buffered_comb_wires) {
2365 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2366 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2367 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2368 const char *why_pessimistic = nullptr;
2369 if (has_feedback_arcs)
2370 why_pessimistic = "feedback wires";
2371 else if (has_buffered_comb_wires)
2372 why_pessimistic = "buffered combinatorial wires";
2373 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2374 if (!run_flatten)
2375 log("Flattening may eliminate %s from the design.\n", why_pessimistic);
2376 if (!run_proc)
2377 log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic);
2378 }
2379 }
2380
2381 void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init, bool &has_packed_mem)
2382 {
2383 has_sync_init = has_packed_mem = has_top = false;
2384
2385 for (auto module : design->modules()) {
2386 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2387 continue;
2388
2389 if (!design->selected_whole_module(module))
2390 if (design->selected_module(module))
2391 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2392 if (!design->selected_module(module))
2393 continue;
2394
2395 if (module->get_bool_attribute(ID::top))
2396 has_top = true;
2397
2398 for (auto proc : module->processes)
2399 for (auto sync : proc.second->syncs)
2400 if (sync->type == RTLIL::STi)
2401 has_sync_init = true;
2402
2403 // The Mem constructor also checks for well-formedness of $meminit cells, if any.
2404 for (auto &mem : Mem::get_all_memories(module))
2405 if (mem.packed)
2406 has_packed_mem = true;
2407 }
2408 }
2409
2410 void prepare_design(RTLIL::Design *design)
2411 {
2412 bool did_anything = false;
2413 bool has_top, has_sync_init, has_packed_mem;
2414 log_push();
2415 check_design(design, has_top, has_sync_init, has_packed_mem);
2416 if (run_hierarchy && !has_top) {
2417 Pass::call(design, "hierarchy -auto-top");
2418 did_anything = true;
2419 }
2420 if (run_flatten) {
2421 Pass::call(design, "flatten");
2422 did_anything = true;
2423 }
2424 if (run_proc) {
2425 Pass::call(design, "proc");
2426 did_anything = true;
2427 } else if (has_sync_init) {
2428 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2429 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2430 Pass::call(design, "proc_prune");
2431 Pass::call(design, "proc_clean");
2432 Pass::call(design, "proc_init");
2433 did_anything = true;
2434 }
2435 if (has_packed_mem) {
2436 Pass::call(design, "memory_unpack");
2437 did_anything = true;
2438 }
2439 // Recheck the design if it was modified.
2440 if (did_anything)
2441 check_design(design, has_top, has_sync_init, has_packed_mem);
2442 log_assert(has_top && !has_sync_init && !has_packed_mem);
2443 log_pop();
2444 if (did_anything)
2445 log_spacer();
2446 analyze_design(design);
2447 }
2448 };
2449
2450 struct CxxrtlBackend : public Backend {
2451 static const int DEFAULT_OPT_LEVEL = 6;
2452 static const int OPT_LEVEL_DEBUG = 4;
2453 static const int DEFAULT_DEBUG_LEVEL = 1;
2454
2455 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2456 void help() override
2457 {
2458 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2459 log("\n");
2460 log(" write_cxxrtl [options] [filename]\n");
2461 log("\n");
2462 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2463 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2464 log("\n");
2465 log("The following driver may be used as an example for a design with a single clock\n");
2466 log("driving rising edge triggered flip-flops:\n");
2467 log("\n");
2468 log(" #include \"top.cc\"\n");
2469 log("\n");
2470 log(" int main() {\n");
2471 log(" cxxrtl_design::p_top top;\n");
2472 log(" top.step();\n");
2473 log(" while (1) {\n");
2474 log(" /* user logic */\n");
2475 log(" top.p_clk.set(false);\n");
2476 log(" top.step();\n");
2477 log(" top.p_clk.set(true);\n");
2478 log(" top.step();\n");
2479 log(" }\n");
2480 log(" }\n");
2481 log("\n");
2482 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2483 log("subject to race conditions. If, in the example above, the user logic would run\n");
2484 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2485 log("\n");
2486 log("This backend supports replacing parts of the design with black boxes implemented\n");
2487 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2488 log("and the generated code consists only of an interface and a factory function.\n");
2489 log("The driver must implement the factory function that creates an implementation of\n");
2490 log("the black box, taking into account the parameters it is instantiated with.\n");
2491 log("\n");
2492 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2493 log("a synchronous debug sink:\n");
2494 log("\n");
2495 log(" (* cxxrtl_blackbox *)\n");
2496 log(" module debug(...);\n");
2497 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2498 log(" input en;\n");
2499 log(" input [7:0] i_data;\n");
2500 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2501 log(" endmodule\n");
2502 log("\n");
2503 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2504 log("\n");
2505 log(" struct bb_p_debug : public module {\n");
2506 log(" value<1> p_clk;\n");
2507 log(" bool posedge_p_clk() const { /* ... */ }\n");
2508 log(" value<1> p_en;\n");
2509 log(" value<8> p_i_data;\n");
2510 log(" wire<8> p_o_data;\n");
2511 log("\n");
2512 log(" bool eval() override;\n");
2513 log(" bool commit() override;\n");
2514 log("\n");
2515 log(" static std::unique_ptr<bb_p_debug>\n");
2516 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2517 log(" };\n");
2518 log("\n");
2519 log("The `create' function must be implemented by the driver. For example, it could\n");
2520 log("always provide an implementation logging the values to standard error stream:\n");
2521 log("\n");
2522 log(" namespace cxxrtl_design {\n");
2523 log("\n");
2524 log(" struct stderr_debug : public bb_p_debug {\n");
2525 log(" bool eval() override {\n");
2526 log(" if (posedge_p_clk() && p_en)\n");
2527 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2528 log(" p_o_data.next = p_i_data;\n");
2529 log(" return bb_p_debug::eval();\n");
2530 log(" }\n");
2531 log(" };\n");
2532 log("\n");
2533 log(" std::unique_ptr<bb_p_debug>\n");
2534 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2535 log(" cxxrtl::metadata_map attributes) {\n");
2536 log(" return std::make_unique<stderr_debug>();\n");
2537 log(" }\n");
2538 log("\n");
2539 log(" }\n");
2540 log("\n");
2541 log("For complex applications of black boxes, it is possible to parameterize their\n");
2542 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2543 log("interface for a configurable width debug sink:\n");
2544 log("\n");
2545 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2546 log(" module debug(...);\n");
2547 log(" parameter WIDTH = 8;\n");
2548 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2549 log(" input en;\n");
2550 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2551 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2552 log(" endmodule\n");
2553 log("\n");
2554 log("For this parametric HDL interface, this backend will generate the following C++\n");
2555 log("interface (only the differences are shown):\n");
2556 log("\n");
2557 log(" template<size_t WIDTH>\n");
2558 log(" struct bb_p_debug : public module {\n");
2559 log(" // ...\n");
2560 log(" value<WIDTH> p_i_data;\n");
2561 log(" wire<WIDTH> p_o_data;\n");
2562 log(" // ...\n");
2563 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2564 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2565 log(" };\n");
2566 log("\n");
2567 log("The `create' function must be implemented by the driver, specialized for every\n");
2568 log("possible combination of template parameters. (Specialization is necessary to\n");
2569 log("enable separate compilation of generated code and black box implementations.)\n");
2570 log("\n");
2571 log(" template<size_t SIZE>\n");
2572 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2573 log(" // ...\n");
2574 log(" };\n");
2575 log("\n");
2576 log(" template<>\n");
2577 log(" std::unique_ptr<bb_p_debug<8>>\n");
2578 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2579 log(" cxxrtl::metadata_map attributes) {\n");
2580 log(" return std::make_unique<stderr_debug<8>>();\n");
2581 log(" }\n");
2582 log("\n");
2583 log("The following attributes are recognized by this backend:\n");
2584 log("\n");
2585 log(" cxxrtl_blackbox\n");
2586 log(" only valid on modules. if specified, the module contents are ignored,\n");
2587 log(" and the generated code includes only the module interface and a factory\n");
2588 log(" function, which will be called to instantiate the module.\n");
2589 log("\n");
2590 log(" cxxrtl_edge\n");
2591 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2592 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2593 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2594 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2595 log("\n");
2596 log(" cxxrtl_template\n");
2597 log(" only valid on black boxes. must contain a space separated sequence of\n");
2598 log(" identifiers that have a corresponding black box parameters. for each\n");
2599 log(" of them, the generated code includes a `size_t` template parameter.\n");
2600 log("\n");
2601 log(" cxxrtl_width\n");
2602 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2603 log(" is directly inserted into generated code.\n");
2604 log("\n");
2605 log(" cxxrtl_comb, cxxrtl_sync\n");
2606 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2607 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2608 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2609 log(" if neither is specified, the output will be pessimistically treated as\n");
2610 log(" driven by both combinatorial and synchronous logic.\n");
2611 log("\n");
2612 log("The following options are supported by this backend:\n");
2613 log("\n");
2614 log(" -header\n");
2615 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2616 log(" if specified, the backend must be called with a filename, and filename\n");
2617 log(" of the interface is derived from filename of the implementation.\n");
2618 log(" otherwise, interface and implementation are generated together.\n");
2619 log("\n");
2620 log(" -namespace <ns-name>\n");
2621 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2622 log(" \"cxxrtl_design\" is used.\n");
2623 log("\n");
2624 log(" -nohierarchy\n");
2625 log(" use design hierarchy as-is. in most designs, a top module should be\n");
2626 log(" present as it is exposed through the C API and has unbuffered outputs\n");
2627 log(" for improved performance; it will be determined automatically if absent.\n");
2628 log("\n");
2629 log(" -noflatten\n");
2630 log(" don't flatten the design. fully flattened designs can evaluate within\n");
2631 log(" one delta cycle if they have no combinatorial feedback.\n");
2632 log(" note that the debug interface and waveform dumps use full hierarchical\n");
2633 log(" names for all wires even in flattened designs.\n");
2634 log("\n");
2635 log(" -noproc\n");
2636 log(" don't convert processes to netlists. in most designs, converting\n");
2637 log(" processes significantly improves evaluation performance at the cost of\n");
2638 log(" slight increase in compilation time.\n");
2639 log("\n");
2640 log(" -O <level>\n");
2641 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2642 log(" levels dramatically decrease compile and run time, and highest level\n");
2643 log(" possible for a design should be used.\n");
2644 log("\n");
2645 log(" -O0\n");
2646 log(" no optimization.\n");
2647 log("\n");
2648 log(" -O1\n");
2649 log(" localize internal wires if possible.\n");
2650 log("\n");
2651 log(" -O2\n");
2652 log(" like -O1, and unbuffer internal wires if possible.\n");
2653 log("\n");
2654 log(" -O3\n");
2655 log(" like -O2, and elide internal wires if possible.\n");
2656 log("\n");
2657 log(" -O4\n");
2658 log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
2659 log("\n");
2660 log(" -O5\n");
2661 log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
2662 log("\n");
2663 log(" -O6\n");
2664 log(" like -O5, and elide public wires not marked (*keep*) if possible.\n");
2665 log("\n");
2666 log(" -Og\n");
2667 log(" highest optimization level that provides debug information for all\n");
2668 log(" public wires. currently, alias for -O%d.\n", OPT_LEVEL_DEBUG);
2669 log("\n");
2670 log(" -g <level>\n");
2671 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2672 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2673 log("\n");
2674 log(" -g0\n");
2675 log(" no debug information.\n");
2676 log("\n");
2677 log(" -g1\n");
2678 log(" debug information for non-optimized public wires. this also makes it\n");
2679 log(" possible to use the C API.\n");
2680 log("\n");
2681 }
2682
2683 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
2684 {
2685 bool nohierarchy = false;
2686 bool noflatten = false;
2687 bool noproc = false;
2688 int opt_level = DEFAULT_OPT_LEVEL;
2689 int debug_level = DEFAULT_DEBUG_LEVEL;
2690 CxxrtlWorker worker;
2691
2692 log_header(design, "Executing CXXRTL backend.\n");
2693
2694 size_t argidx;
2695 for (argidx = 1; argidx < args.size(); argidx++)
2696 {
2697 if (args[argidx] == "-nohierarchy") {
2698 nohierarchy = true;
2699 continue;
2700 }
2701 if (args[argidx] == "-noflatten") {
2702 noflatten = true;
2703 continue;
2704 }
2705 if (args[argidx] == "-noproc") {
2706 noproc = true;
2707 continue;
2708 }
2709 if (args[argidx] == "-Og") {
2710 opt_level = OPT_LEVEL_DEBUG;
2711 continue;
2712 }
2713 if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
2714 argidx++;
2715 opt_level = OPT_LEVEL_DEBUG;
2716 continue;
2717 }
2718 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2719 opt_level = std::stoi(args[++argidx]);
2720 continue;
2721 }
2722 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2723 opt_level = std::stoi(args[argidx].substr(2));
2724 continue;
2725 }
2726 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2727 debug_level = std::stoi(args[++argidx]);
2728 continue;
2729 }
2730 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2731 debug_level = std::stoi(args[argidx].substr(2));
2732 continue;
2733 }
2734 if (args[argidx] == "-header") {
2735 worker.split_intf = true;
2736 continue;
2737 }
2738 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2739 worker.design_ns = args[++argidx];
2740 continue;
2741 }
2742 break;
2743 }
2744 extra_args(f, filename, args, argidx);
2745
2746 worker.run_hierarchy = !nohierarchy;
2747 worker.run_flatten = !noflatten;
2748 worker.run_proc = !noproc;
2749 switch (opt_level) {
2750 // the highest level here must match DEFAULT_OPT_LEVEL
2751 case 6:
2752 worker.elide_public = true;
2753 YS_FALLTHROUGH
2754 case 5:
2755 worker.localize_public = true;
2756 YS_FALLTHROUGH
2757 case 4:
2758 worker.unbuffer_public = true;
2759 YS_FALLTHROUGH
2760 case 3:
2761 worker.elide_internal = true;
2762 YS_FALLTHROUGH
2763 case 2:
2764 worker.localize_internal = true;
2765 YS_FALLTHROUGH
2766 case 1:
2767 worker.unbuffer_internal = true;
2768 YS_FALLTHROUGH
2769 case 0:
2770 break;
2771 default:
2772 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2773 }
2774 switch (debug_level) {
2775 // the highest level here must match DEFAULT_DEBUG_LEVEL
2776 case 1:
2777 worker.debug_info = true;
2778 YS_FALLTHROUGH
2779 case 0:
2780 break;
2781 default:
2782 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2783 }
2784
2785 std::ofstream intf_f;
2786 if (worker.split_intf) {
2787 if (filename == "<stdout>")
2788 log_cmd_error("Option -header must be used with a filename.\n");
2789
2790 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2791 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2792 if (intf_f.fail())
2793 log_cmd_error("Can't open file `%s' for writing: %s\n",
2794 worker.intf_filename.c_str(), strerror(errno));
2795
2796 worker.intf_f = &intf_f;
2797 }
2798 worker.impl_f = f;
2799
2800 worker.prepare_design(design);
2801 worker.dump_design(design);
2802 }
2803 } CxxrtlBackend;
2804
2805 PRIVATE_NAMESPACE_END