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cxxrtl: make alias analysis outlining-aware.
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/mem.h"
26 #include "kernel/log.h"
27
28 USING_YOSYS_NAMESPACE
29 PRIVATE_NAMESPACE_BEGIN
30
31 // [[CITE]]
32 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
33 // Information Processing Letters, Vol. 47, pp 319-323, 1993
34 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
35
36 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
37 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
38 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
39 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
40 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
41 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
42 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
43 template<class T>
44 struct Scheduler {
45 struct Vertex {
46 T *data;
47 Vertex *prev, *next;
48 pool<Vertex*, hash_ptr_ops> preds, succs;
49
50 Vertex() : data(NULL), prev(this), next(this) {}
51 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
52
53 bool empty() const
54 {
55 log_assert(data == NULL);
56 if (next == this) {
57 log_assert(prev == next);
58 return true;
59 }
60 return false;
61 }
62
63 void link(Vertex *list)
64 {
65 log_assert(prev == NULL && next == NULL);
66 next = list;
67 prev = list->prev;
68 list->prev->next = this;
69 list->prev = this;
70 }
71
72 void unlink()
73 {
74 log_assert(prev->next == this && next->prev == this);
75 prev->next = next;
76 next->prev = prev;
77 next = prev = NULL;
78 }
79
80 int delta() const
81 {
82 return succs.size() - preds.size();
83 }
84 };
85
86 std::vector<Vertex*> vertices;
87 Vertex *sources = new Vertex;
88 Vertex *sinks = new Vertex;
89 dict<int, Vertex*> bins;
90
91 ~Scheduler()
92 {
93 delete sources;
94 delete sinks;
95 for (auto bin : bins)
96 delete bin.second;
97 for (auto vertex : vertices)
98 delete vertex;
99 }
100
101 Vertex *add(T *data)
102 {
103 Vertex *vertex = new Vertex(data);
104 vertices.push_back(vertex);
105 return vertex;
106 }
107
108 void relink(Vertex *vertex)
109 {
110 if (vertex->succs.empty())
111 vertex->link(sinks);
112 else if (vertex->preds.empty())
113 vertex->link(sources);
114 else {
115 int delta = vertex->delta();
116 if (!bins.count(delta))
117 bins[delta] = new Vertex;
118 vertex->link(bins[delta]);
119 }
120 }
121
122 Vertex *remove(Vertex *vertex)
123 {
124 vertex->unlink();
125 for (auto pred : vertex->preds) {
126 if (pred == vertex)
127 continue;
128 log_assert(pred->succs[vertex]);
129 pred->unlink();
130 pred->succs.erase(vertex);
131 relink(pred);
132 }
133 for (auto succ : vertex->succs) {
134 if (succ == vertex)
135 continue;
136 log_assert(succ->preds[vertex]);
137 succ->unlink();
138 succ->preds.erase(vertex);
139 relink(succ);
140 }
141 vertex->preds.clear();
142 vertex->succs.clear();
143 return vertex;
144 }
145
146 std::vector<Vertex*> schedule()
147 {
148 std::vector<Vertex*> s1, s2r;
149 for (auto vertex : vertices)
150 relink(vertex);
151 bool bins_empty = false;
152 while (!(sinks->empty() && sources->empty() && bins_empty)) {
153 while (!sinks->empty())
154 s2r.push_back(remove(sinks->next));
155 while (!sources->empty())
156 s1.push_back(remove(sources->next));
157 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
158 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
159 // naive implementation of find-max-key.
160 bins_empty = true;
161 bins.template sort<std::greater<int>>();
162 for (auto bin : bins) {
163 if (!bin.second->empty()) {
164 bins_empty = false;
165 s1.push_back(remove(bin.second->next));
166 break;
167 }
168 }
169 }
170 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
171 return s1;
172 }
173 };
174
175 bool is_unary_cell(RTLIL::IdString type)
176 {
177 return type.in(
178 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
179 ID($pos), ID($neg));
180 }
181
182 bool is_binary_cell(RTLIL::IdString type)
183 {
184 return type.in(
185 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
186 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
187 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
188 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
189 }
190
191 bool is_extending_cell(RTLIL::IdString type)
192 {
193 return !type.in(
194 ID($logic_not), ID($logic_and), ID($logic_or),
195 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
196 }
197
198 bool is_inlinable_cell(RTLIL::IdString type)
199 {
200 return is_unary_cell(type) || is_binary_cell(type) || type.in(
201 ID($mux), ID($concat), ID($slice), ID($pmux));
202 }
203
204 bool is_ff_cell(RTLIL::IdString type)
205 {
206 return type.in(
207 ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
208 ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
209 ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
210 }
211
212 bool is_internal_cell(RTLIL::IdString type)
213 {
214 return !type.isPublic() && !type.begins_with("$paramod");
215 }
216
217 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
218 {
219 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
220 log_assert(cell_module != nullptr);
221 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
222 }
223
224 enum class CxxrtlPortType {
225 UNKNOWN = 0, // or mixed comb/sync
226 COMB = 1,
227 SYNC = 2,
228 };
229
230 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
231 {
232 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
233 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
234 return CxxrtlPortType::UNKNOWN;
235 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
236 log_assert(cell_output_wire != nullptr);
237 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
238 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
239 if (is_comb && is_sync)
240 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
241 log_id(cell_module), log_signal(cell_output_wire));
242 else if (is_comb)
243 return CxxrtlPortType::COMB;
244 else if (is_sync)
245 return CxxrtlPortType::SYNC;
246 return CxxrtlPortType::UNKNOWN;
247 }
248
249 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
250 {
251 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
252 }
253
254 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
255 {
256 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
257 }
258
259 struct FlowGraph {
260 struct Node {
261 enum class Type {
262 CONNECT,
263 CELL_SYNC,
264 CELL_EVAL,
265 PROCESS
266 };
267
268 Type type;
269 RTLIL::SigSig connect = {};
270 const RTLIL::Cell *cell = NULL;
271 const RTLIL::Process *process = NULL;
272 };
273
274 std::vector<Node*> nodes;
275 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
276 dict<const RTLIL::Wire*, bool> wire_def_inlinable, wire_use_inlinable;
277 dict<RTLIL::SigBit, bool> bit_has_state;
278
279 ~FlowGraph()
280 {
281 for (auto node : nodes)
282 delete node;
283 }
284
285 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool inlinable)
286 {
287 for (auto chunk : sig.chunks())
288 if (chunk.wire) {
289 if (is_ff) {
290 // A sync def means that a wire holds design state because it is driven directly by
291 // a flip-flop output. Such a wire can never be unbuffered.
292 wire_sync_defs[chunk.wire].insert(node);
293 } else {
294 // A comb def means that a wire doesn't hold design state. It might still be connected,
295 // indirectly, to a flip-flop output.
296 wire_comb_defs[chunk.wire].insert(node);
297 }
298 }
299 for (auto bit : sig.bits())
300 bit_has_state[bit] |= is_ff;
301 // Only comb defs of an entire wire in the right order can be inlined.
302 if (!is_ff && sig.is_wire())
303 wire_def_inlinable[sig.as_wire()] = inlinable;
304 }
305
306 void add_uses(Node *node, const RTLIL::SigSpec &sig)
307 {
308 for (auto chunk : sig.chunks())
309 if (chunk.wire) {
310 wire_uses[chunk.wire].insert(node);
311 // Only a single use of an entire wire in the right order can be inlined.
312 // (But the use can include other chunks.)
313 if (!wire_use_inlinable.count(chunk.wire))
314 wire_use_inlinable[chunk.wire] = true;
315 else
316 wire_use_inlinable[chunk.wire] = false;
317 }
318 }
319
320 bool is_inlinable(const RTLIL::Wire *wire) const
321 {
322 if (wire_def_inlinable.count(wire) && wire_use_inlinable.count(wire))
323 return wire_def_inlinable.at(wire) && wire_use_inlinable.at(wire);
324 return false;
325 }
326
327 // Connections
328 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
329 {
330 add_defs(node, conn.first, /*is_ff=*/false, /*inlinable=*/true);
331 add_uses(node, conn.second);
332 }
333
334 Node *add_node(const RTLIL::SigSig &conn)
335 {
336 Node *node = new Node;
337 node->type = Node::Type::CONNECT;
338 node->connect = conn;
339 nodes.push_back(node);
340 add_connect_defs_uses(node, conn);
341 return node;
342 }
343
344 // Cells
345 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
346 {
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
352 //
353 // wire<1> i_tmp;
354 // cell->p_i = i_tmp.curr;
355 // cell->eval();
356 // i_tmp.next = cell->p_o.curr;
357 //
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
361 //
362 // value<1> i_tmp;
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
365 // cell->eval();
366 //
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn : cell->connections())
374 if (cell->output(conn.first))
375 if (is_cxxrtl_sync_port(cell, conn.first)) {
376 // See note regarding inlinability below.
377 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
378 }
379 }
380
381 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
382 {
383 for (auto conn : cell->connections()) {
384 if (cell->output(conn.first)) {
385 if (is_inlinable_cell(cell->type))
386 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/true);
387 else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
388 add_defs(node, conn.second, /*is_ff=*/true, /*inlinable=*/false);
389 else if (is_internal_cell(cell->type))
390 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
391 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
392 // Although at first it looks like outputs of user-defined cells may always be inlined, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in inlining. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be inlined, but should be rare in practical designs and don't justify
396 // the infrastructure required to inline outputs of cells with many of them.
397 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
398 }
399 }
400 if (cell->input(conn.first))
401 add_uses(node, conn.second);
402 }
403 }
404
405 Node *add_node(const RTLIL::Cell *cell)
406 {
407 log_assert(cell->known());
408
409 bool has_fully_sync_outputs = false;
410 for (auto conn : cell->connections())
411 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
412 has_fully_sync_outputs = true;
413 break;
414 }
415 if (has_fully_sync_outputs) {
416 Node *node = new Node;
417 node->type = Node::Type::CELL_SYNC;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_sync_defs(node, cell);
421 }
422
423 Node *node = new Node;
424 node->type = Node::Type::CELL_EVAL;
425 node->cell = cell;
426 nodes.push_back(node);
427 add_cell_eval_defs_uses(node, cell);
428 return node;
429 }
430
431 // Processes
432 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
433 {
434 for (auto &action : case_->actions) {
435 add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
436 add_uses(node, action.second);
437 }
438 for (auto sub_switch : case_->switches) {
439 add_uses(node, sub_switch->signal);
440 for (auto sub_case : sub_switch->cases) {
441 for (auto &compare : sub_case->compare)
442 add_uses(node, compare);
443 add_case_defs_uses(node, sub_case);
444 }
445 }
446 }
447
448 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
449 {
450 add_case_defs_uses(node, &process->root_case);
451 for (auto sync : process->syncs)
452 for (auto action : sync->actions) {
453 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
454 add_defs(node, action.first, /*is_ff=*/true, /*inlinable=*/false);
455 else
456 add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
457 add_uses(node, action.second);
458 }
459 }
460
461 Node *add_node(const RTLIL::Process *process)
462 {
463 Node *node = new Node;
464 node->type = Node::Type::PROCESS;
465 node->process = process;
466 nodes.push_back(node);
467 add_process_defs_uses(node, process);
468 return node;
469 }
470 };
471
472 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
473 {
474 std::vector<std::string> result;
475 size_t prev = 0;
476 while (true) {
477 size_t curr = str.find_first_of(sep, prev);
478 if (curr == std::string::npos) {
479 std::string part = str.substr(prev);
480 if (!part.empty()) result.push_back(part);
481 break;
482 } else {
483 std::string part = str.substr(prev, curr - prev);
484 if (!part.empty()) result.push_back(part);
485 prev = curr + 1;
486 }
487 }
488 return result;
489 }
490
491 std::string escape_cxx_string(const std::string &input)
492 {
493 std::string output = "\"";
494 for (auto c : input) {
495 if (::isprint(c)) {
496 if (c == '\\')
497 output.push_back('\\');
498 output.push_back(c);
499 } else {
500 char l = c & 0xf, h = (c >> 4) & 0xf;
501 output.append("\\x");
502 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
503 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
504 }
505 }
506 output.push_back('"');
507 if (output.find('\0') != std::string::npos) {
508 output.insert(0, "std::string {");
509 output.append(stringf(", %zu}", input.size()));
510 }
511 return output;
512 }
513
514 template<class T>
515 std::string get_hdl_name(T *object)
516 {
517 if (object->has_attribute(ID::hdlname))
518 return object->get_string_attribute(ID::hdlname);
519 else
520 return object->name.str().substr(1);
521 }
522
523 struct CxxrtlWorker {
524 bool split_intf = false;
525 std::string intf_filename;
526 std::string design_ns = "cxxrtl_design";
527 std::ostream *impl_f = nullptr;
528 std::ostream *intf_f = nullptr;
529
530 bool run_hierarchy = false;
531 bool run_flatten = false;
532 bool run_proc = false;
533
534 bool unbuffer_internal = false;
535 bool unbuffer_public = false;
536 bool localize_internal = false;
537 bool localize_public = false;
538 bool inline_internal = false;
539 bool inline_public = false;
540
541 bool debug_info = false;
542 bool debug_alias = false;
543 bool debug_eval = false;
544
545 std::ostringstream f;
546 std::string indent;
547 int temporary = 0;
548
549 dict<const RTLIL::Module*, SigMap> sigmaps;
550 pool<const RTLIL::Wire*> edge_wires;
551 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
552 pool<const RTLIL::Memory*> writable_memories;
553 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
554 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
555 pool<const RTLIL::Wire*> unbuffered_wires;
556 pool<const RTLIL::Wire*> localized_wires;
557 dict<const RTLIL::Wire*, FlowGraph::Node> inlined_wires;
558 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
559 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
560 pool<const RTLIL::Wire*> debug_outlined_wires;
561 dict<RTLIL::SigBit, bool> bit_has_state;
562 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
563 dict<const RTLIL::Module*, bool> eval_converges;
564
565 void inc_indent() {
566 indent += "\t";
567 }
568 void dec_indent() {
569 indent.resize(indent.size() - 1);
570 }
571
572 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
573 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
574 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
575 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
576 // 1. All generated identifiers start with `_`.
577 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
578 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
579 // 2. An underscore is escaped with another underscore, i.e. `__`.
580 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
581 std::string mangle_name(const RTLIL::IdString &name)
582 {
583 std::string mangled;
584 bool first = true;
585 for (char c : name.str()) {
586 if (first) {
587 first = false;
588 if (c == '\\')
589 mangled += "p_";
590 else if (c == '$')
591 mangled += "i_";
592 else
593 log_assert(false);
594 } else {
595 if (isalnum(c)) {
596 mangled += c;
597 } else if (c == '_') {
598 mangled += "__";
599 } else {
600 char l = c & 0xf, h = (c >> 4) & 0xf;
601 mangled += '_';
602 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
603 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
604 mangled += '_';
605 }
606 }
607 }
608 return mangled;
609 }
610
611 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
612 {
613 // Class namespace.
614 if (is_blackbox)
615 return "bb_" + mangle_name(name);
616 return mangle_name(name);
617 }
618
619 std::string mangle_memory_name(const RTLIL::IdString &name)
620 {
621 // Class member namespace.
622 return "memory_" + mangle_name(name);
623 }
624
625 std::string mangle_cell_name(const RTLIL::IdString &name)
626 {
627 // Class member namespace.
628 return "cell_" + mangle_name(name);
629 }
630
631 std::string mangle_wire_name(const RTLIL::IdString &name)
632 {
633 // Class member namespace.
634 return mangle_name(name);
635 }
636
637 std::string mangle(const RTLIL::Module *module)
638 {
639 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
640 }
641
642 std::string mangle(const RTLIL::Memory *memory)
643 {
644 return mangle_memory_name(memory->name);
645 }
646
647 std::string mangle(const RTLIL::Cell *cell)
648 {
649 return mangle_cell_name(cell->name);
650 }
651
652 std::string mangle(const RTLIL::Wire *wire)
653 {
654 return mangle_wire_name(wire->name);
655 }
656
657 std::string mangle(RTLIL::SigBit sigbit)
658 {
659 log_assert(sigbit.wire != NULL);
660 if (sigbit.wire->width == 1)
661 return mangle(sigbit.wire);
662 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
663 }
664
665 std::vector<std::string> template_param_names(const RTLIL::Module *module)
666 {
667 if (!module->has_attribute(ID(cxxrtl_template)))
668 return {};
669
670 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
671 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
672
673 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
674 for (const auto &param_name : param_names) {
675 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
676 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
677 // in both Verilog and C++, anyway.)
678 if (!isupper(param_name[0]))
679 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
680 "which does not start with an uppercase letter.\n",
681 log_id(module), param_name.c_str());
682 }
683 return param_names;
684 }
685
686 std::string template_params(const RTLIL::Module *module, bool is_decl)
687 {
688 std::vector<std::string> param_names = template_param_names(module);
689 if (param_names.empty())
690 return "";
691
692 std::string params = "<";
693 bool first = true;
694 for (const auto &param_name : param_names) {
695 if (!first)
696 params += ", ";
697 first = false;
698 if (is_decl)
699 params += "size_t ";
700 params += param_name;
701 }
702 params += ">";
703 return params;
704 }
705
706 std::string template_args(const RTLIL::Cell *cell)
707 {
708 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
709 log_assert(cell_module != nullptr);
710 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
711 return "";
712
713 std::vector<std::string> param_names = template_param_names(cell_module);
714 if (param_names.empty())
715 return "";
716
717 std::string params = "<";
718 bool first = true;
719 for (const auto &param_name : param_names) {
720 if (!first)
721 params += ", ";
722 first = false;
723 params += "/*" + param_name + "=*/";
724 RTLIL::IdString id_param_name = '\\' + param_name;
725 if (!cell->hasParam(id_param_name))
726 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
727 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
728 RTLIL::Const param_value = cell->getParam(id_param_name);
729 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
730 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
731 "is not a positive integer.\n",
732 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
733 params += std::to_string(cell->getParam(id_param_name).as_int());
734 }
735 params += ">";
736 return params;
737 }
738
739 std::string fresh_temporary()
740 {
741 return stringf("tmp_%d", temporary++);
742 }
743
744 void dump_attrs(const RTLIL::AttrObject *object)
745 {
746 for (auto attr : object->attributes) {
747 f << indent << "// " << attr.first.str() << ": ";
748 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
749 f << attr.second.decode_string();
750 } else {
751 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
752 }
753 f << "\n";
754 }
755 }
756
757 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
758 {
759 const int CHUNK_SIZE = 32;
760 f << "{";
761 while (width > 0) {
762 int chunk_width = min(width, CHUNK_SIZE);
763 uint32_t chunk = data.extract(offset, chunk_width).as_int();
764 if (fixed_width)
765 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
766 else
767 f << stringf("%#xu", chunk);
768 if (width > CHUNK_SIZE)
769 f << ',';
770 offset += CHUNK_SIZE;
771 width -= CHUNK_SIZE;
772 }
773 f << "}";
774 }
775
776 void dump_const_init(const RTLIL::Const &data)
777 {
778 dump_const_init(data, data.size());
779 }
780
781 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
782 {
783 f << "value<" << width << ">";
784 dump_const_init(data, width, offset, fixed_width);
785 }
786
787 void dump_const(const RTLIL::Const &data)
788 {
789 dump_const(data, data.size());
790 }
791
792 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs, bool for_debug = false)
793 {
794 if (chunk.wire == NULL) {
795 dump_const(chunk.data, chunk.width, chunk.offset);
796 return false;
797 } else {
798 if (inlined_wires.count(chunk.wire) && (!for_debug || !debug_outlined_wires[chunk.wire])) {
799 log_assert(!is_lhs);
800 const FlowGraph::Node &node = inlined_wires[chunk.wire];
801 switch (node.type) {
802 case FlowGraph::Node::Type::CONNECT:
803 dump_connect_expr(node.connect, for_debug);
804 break;
805 case FlowGraph::Node::Type::CELL_EVAL:
806 log_assert(is_inlinable_cell(node.cell->type));
807 dump_cell_expr(node.cell, for_debug);
808 break;
809 default:
810 log_assert(false);
811 }
812 } else if (unbuffered_wires[chunk.wire]) {
813 f << mangle(chunk.wire);
814 } else {
815 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
816 }
817 if (chunk.width == chunk.wire->width && chunk.offset == 0)
818 return false;
819 else if (chunk.width == 1)
820 f << ".slice<" << chunk.offset << ">()";
821 else
822 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
823 return true;
824 }
825 }
826
827 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs, bool for_debug = false)
828 {
829 if (sig.empty()) {
830 f << "value<0>()";
831 return false;
832 } else if (sig.is_chunk()) {
833 return dump_sigchunk(sig.as_chunk(), is_lhs, for_debug);
834 } else {
835 dump_sigchunk(*sig.chunks().rbegin(), is_lhs, for_debug);
836 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
837 f << ".concat(";
838 dump_sigchunk(*it, is_lhs, for_debug);
839 f << ")";
840 }
841 return true;
842 }
843 }
844
845 void dump_sigspec_lhs(const RTLIL::SigSpec &sig, bool for_debug = false)
846 {
847 dump_sigspec(sig, /*is_lhs=*/true, for_debug);
848 }
849
850 void dump_sigspec_rhs(const RTLIL::SigSpec &sig, bool for_debug = false)
851 {
852 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
853 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
854 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
855 // type conversion, but only if the expression needs it.
856 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false, for_debug);
857 if (is_complex)
858 f << ".val()";
859 }
860
861 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
862 {
863 for (auto chunk : sig.chunks()) {
864 if (!chunk.wire || !inlined_wires.count(chunk.wire))
865 continue;
866
867 const FlowGraph::Node &node = inlined_wires[chunk.wire];
868 switch (node.type) {
869 case FlowGraph::Node::Type::CONNECT:
870 collect_connect(node.connect, cells);
871 break;
872 case FlowGraph::Node::Type::CELL_EVAL:
873 collect_cell_eval(node.cell, cells);
874 break;
875 default:
876 log_assert(false);
877 }
878 }
879 }
880
881 void dump_connect_expr(const RTLIL::SigSig &conn, bool for_debug = false)
882 {
883 dump_sigspec_rhs(conn.second, for_debug);
884 }
885
886 bool is_connect_inlined(const RTLIL::SigSig &conn)
887 {
888 return conn.first.is_wire() && inlined_wires.count(conn.first.as_wire());
889 }
890
891 bool is_connect_outlined(const RTLIL::SigSig &conn)
892 {
893 for (auto chunk : conn.first.chunks())
894 if (debug_outlined_wires.count(chunk.wire))
895 return true;
896 return false;
897 }
898
899 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
900 {
901 if (!is_connect_inlined(conn))
902 return;
903
904 collect_sigspec_rhs(conn.second, cells);
905 }
906
907 void dump_connect(const RTLIL::SigSig &conn, bool for_debug = false)
908 {
909 if (!for_debug && is_connect_inlined(conn))
910 return;
911 if (for_debug && !is_connect_outlined(conn))
912 return;
913
914 f << indent << "// connection\n";
915 f << indent;
916 dump_sigspec_lhs(conn.first, for_debug);
917 f << " = ";
918 dump_connect_expr(conn, for_debug);
919 f << ";\n";
920 }
921
922 void dump_cell_sync(const RTLIL::Cell *cell)
923 {
924 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
925 f << indent << "// cell " << cell->name.str() << " syncs\n";
926 for (auto conn : cell->connections())
927 if (cell->output(conn.first))
928 if (is_cxxrtl_sync_port(cell, conn.first)) {
929 f << indent;
930 dump_sigspec_lhs(conn.second);
931 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
932 }
933 }
934
935 void dump_cell_expr(const RTLIL::Cell *cell, bool for_debug = false)
936 {
937 // Unary cells
938 if (is_unary_cell(cell->type)) {
939 f << cell->type.substr(1);
940 if (is_extending_cell(cell->type))
941 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
942 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
943 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
944 f << ")";
945 // Binary cells
946 } else if (is_binary_cell(cell->type)) {
947 f << cell->type.substr(1);
948 if (is_extending_cell(cell->type))
949 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
950 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
951 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
952 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
953 f << ", ";
954 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
955 f << ")";
956 // Muxes
957 } else if (cell->type == ID($mux)) {
958 f << "(";
959 dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
960 f << " ? ";
961 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
962 f << " : ";
963 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
964 f << ")";
965 // Parallel (one-hot) muxes
966 } else if (cell->type == ID($pmux)) {
967 int width = cell->getParam(ID::WIDTH).as_int();
968 int s_width = cell->getParam(ID::S_WIDTH).as_int();
969 for (int part = 0; part < s_width; part++) {
970 f << "(";
971 dump_sigspec_rhs(cell->getPort(ID::S).extract(part), for_debug);
972 f << " ? ";
973 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width), for_debug);
974 f << " : ";
975 }
976 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
977 for (int part = 0; part < s_width; part++) {
978 f << ")";
979 }
980 // Concats
981 } else if (cell->type == ID($concat)) {
982 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
983 f << ".concat(";
984 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
985 f << ").val()";
986 // Slices
987 } else if (cell->type == ID($slice)) {
988 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
989 f << ".slice<";
990 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
991 f << ",";
992 f << cell->getParam(ID::OFFSET).as_int();
993 f << ">().val()";
994 } else {
995 log_assert(false);
996 }
997 }
998
999 bool is_cell_inlined(const RTLIL::Cell *cell)
1000 {
1001 return is_inlinable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
1002 inlined_wires.count(cell->getPort(ID::Y).as_wire());
1003 }
1004
1005 bool is_cell_outlined(const RTLIL::Cell *cell)
1006 {
1007 if (is_internal_cell(cell->type))
1008 for (auto conn : cell->connections())
1009 if (cell->output(conn.first))
1010 for (auto chunk : conn.second.chunks())
1011 if (debug_outlined_wires.count(chunk.wire))
1012 return true;
1013 return false;
1014 }
1015
1016 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
1017 {
1018 if (!is_cell_inlined(cell))
1019 return;
1020
1021 cells.push_back(cell->name);
1022 for (auto port : cell->connections())
1023 if (port.first != ID::Y)
1024 collect_sigspec_rhs(port.second, cells);
1025 }
1026
1027 void dump_cell_eval(const RTLIL::Cell *cell, bool for_debug = false)
1028 {
1029 if (!for_debug && is_cell_inlined(cell))
1030 return;
1031 if (for_debug && !is_cell_outlined(cell))
1032 return;
1033 if (cell->type == ID($meminit))
1034 return; // Handled elsewhere.
1035
1036 std::vector<RTLIL::IdString> inlined_cells;
1037 if (is_inlinable_cell(cell->type)) {
1038 for (auto port : cell->connections())
1039 if (port.first != ID::Y)
1040 collect_sigspec_rhs(port.second, inlined_cells);
1041 }
1042 if (inlined_cells.empty()) {
1043 dump_attrs(cell);
1044 f << indent << "// cell " << cell->name.str() << "\n";
1045 } else {
1046 f << indent << "// cells";
1047 for (auto inlined_cell : inlined_cells)
1048 f << " " << inlined_cell.str();
1049 f << "\n";
1050 }
1051
1052 // Elidable cells
1053 if (is_inlinable_cell(cell->type)) {
1054 f << indent;
1055 dump_sigspec_lhs(cell->getPort(ID::Y), for_debug);
1056 f << " = ";
1057 dump_cell_expr(cell, for_debug);
1058 f << ";\n";
1059 // Flip-flops
1060 } else if (is_ff_cell(cell->type)) {
1061 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1062 // Edge-sensitive logic
1063 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1064 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1065 if (clk_bit.wire) {
1066 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1067 << mangle(clk_bit) << ") {\n";
1068 } else {
1069 f << indent << "if (false) {\n";
1070 }
1071 inc_indent();
1072 if (cell->hasPort(ID::EN)) {
1073 f << indent << "if (";
1074 dump_sigspec_rhs(cell->getPort(ID::EN));
1075 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1076 inc_indent();
1077 }
1078 f << indent;
1079 dump_sigspec_lhs(cell->getPort(ID::Q));
1080 f << " = ";
1081 dump_sigspec_rhs(cell->getPort(ID::D));
1082 f << ";\n";
1083 if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
1084 dec_indent();
1085 f << indent << "}\n";
1086 }
1087 if (cell->hasPort(ID::SRST)) {
1088 f << indent << "if (";
1089 dump_sigspec_rhs(cell->getPort(ID::SRST));
1090 f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
1091 inc_indent();
1092 f << indent;
1093 dump_sigspec_lhs(cell->getPort(ID::Q));
1094 f << " = ";
1095 dump_const(cell->getParam(ID::SRST_VALUE));
1096 f << ";\n";
1097 dec_indent();
1098 f << indent << "}\n";
1099 }
1100 if (cell->hasPort(ID::EN) && cell->type == ID($sdffce)) {
1101 dec_indent();
1102 f << indent << "}\n";
1103 }
1104 dec_indent();
1105 f << indent << "}\n";
1106 } else if (cell->hasPort(ID::EN)) {
1107 // Level-sensitive logic
1108 f << indent << "if (";
1109 dump_sigspec_rhs(cell->getPort(ID::EN));
1110 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1111 inc_indent();
1112 f << indent;
1113 dump_sigspec_lhs(cell->getPort(ID::Q));
1114 f << " = ";
1115 dump_sigspec_rhs(cell->getPort(ID::D));
1116 f << ";\n";
1117 dec_indent();
1118 f << indent << "}\n";
1119 }
1120 if (cell->hasPort(ID::ARST)) {
1121 // Asynchronous reset (entire coarse cell at once)
1122 f << indent << "if (";
1123 dump_sigspec_rhs(cell->getPort(ID::ARST));
1124 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1125 inc_indent();
1126 f << indent;
1127 dump_sigspec_lhs(cell->getPort(ID::Q));
1128 f << " = ";
1129 dump_const(cell->getParam(ID::ARST_VALUE));
1130 f << ";\n";
1131 dec_indent();
1132 f << indent << "}\n";
1133 }
1134 if (cell->hasPort(ID::SET)) {
1135 // Asynchronous set (for individual bits)
1136 f << indent;
1137 dump_sigspec_lhs(cell->getPort(ID::Q));
1138 f << " = ";
1139 dump_sigspec_lhs(cell->getPort(ID::Q));
1140 f << ".update(";
1141 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1142 f << ", ";
1143 dump_sigspec_rhs(cell->getPort(ID::SET));
1144 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1145 }
1146 if (cell->hasPort(ID::CLR)) {
1147 // Asynchronous clear (for individual bits; priority over set)
1148 f << indent;
1149 dump_sigspec_lhs(cell->getPort(ID::Q));
1150 f << " = ";
1151 dump_sigspec_lhs(cell->getPort(ID::Q));
1152 f << ".update(";
1153 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1154 f << ", ";
1155 dump_sigspec_rhs(cell->getPort(ID::CLR));
1156 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1157 }
1158 // Memory ports
1159 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1160 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1161 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1162 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1163 if (clk_bit.wire) {
1164 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1165 << mangle(clk_bit) << ") {\n";
1166 } else {
1167 f << indent << "if (false) {\n";
1168 }
1169 inc_indent();
1170 }
1171 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1172 std::string valid_index_temp = fresh_temporary();
1173 f << indent << "auto " << valid_index_temp << " = memory_index(";
1174 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1175 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1176 if (cell->type == ID($memrd)) {
1177 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1178 if (has_enable) {
1179 f << indent << "if (";
1180 dump_sigspec_rhs(cell->getPort(ID::EN));
1181 f << ") {\n";
1182 inc_indent();
1183 }
1184 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1185 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1186 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DCXXRTL_NDEBUG
1187 // not only for release builds, but also to make sure the simulator (which is presumably embedded in some
1188 // larger program) will never crash the code that calls into it.
1189 //
1190 // If assertions are disabled, out of bounds reads are defined to return zero.
1191 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1192 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1193 inc_indent();
1194 if (writable_memories[memory]) {
1195 std::string lhs_temp = fresh_temporary();
1196 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1197 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1198 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1199 if (!memwr_cells.empty()) {
1200 std::string addr_temp = fresh_temporary();
1201 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1202 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1203 f << ";\n";
1204 std::sort(memwr_cells.begin(), memwr_cells.end(),
1205 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1206 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1207 });
1208 for (auto memwr_cell : memwr_cells) {
1209 f << indent << "if (" << addr_temp << " == ";
1210 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1211 f << ") {\n";
1212 inc_indent();
1213 f << indent << lhs_temp << " = " << lhs_temp;
1214 f << ".update(";
1215 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1216 f << ", ";
1217 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1218 f << ");\n";
1219 dec_indent();
1220 f << indent << "}\n";
1221 }
1222 }
1223 f << indent;
1224 dump_sigspec_lhs(cell->getPort(ID::DATA));
1225 f << " = " << lhs_temp << ";\n";
1226 } else {
1227 f << indent;
1228 dump_sigspec_lhs(cell->getPort(ID::DATA));
1229 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1230 }
1231 dec_indent();
1232 f << indent << "} else {\n";
1233 inc_indent();
1234 f << indent;
1235 dump_sigspec_lhs(cell->getPort(ID::DATA));
1236 f << " = value<" << memory->width << "> {};\n";
1237 dec_indent();
1238 f << indent << "}\n";
1239 if (has_enable) {
1240 dec_indent();
1241 f << indent << "}\n";
1242 }
1243 } else /*if (cell->type == ID($memwr))*/ {
1244 log_assert(writable_memories[memory]);
1245 // See above for rationale of having both the assert and the condition.
1246 //
1247 // If assertions are disabled, out of bounds writes are defined to do nothing.
1248 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1249 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1250 inc_indent();
1251 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1252 dump_sigspec_rhs(cell->getPort(ID::DATA));
1253 f << ", ";
1254 dump_sigspec_rhs(cell->getPort(ID::EN));
1255 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1256 dec_indent();
1257 f << indent << "}\n";
1258 }
1259 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1260 dec_indent();
1261 f << indent << "}\n";
1262 }
1263 // Internal cells
1264 } else if (is_internal_cell(cell->type)) {
1265 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1266 // User cells
1267 } else {
1268 log_assert(cell->known());
1269 bool buffered_inputs = false;
1270 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1271 for (auto conn : cell->connections())
1272 if (cell->input(conn.first)) {
1273 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1274 log_assert(cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire());
1275 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1276 f << indent << mangle(cell) << access << mangle_wire_name(conn.first);
1277 if (!is_cxxrtl_blackbox_cell(cell) && !unbuffered_wires[cell_module_wire]) {
1278 buffered_inputs = true;
1279 f << ".next";
1280 }
1281 f << " = ";
1282 dump_sigspec_rhs(conn.second);
1283 f << ";\n";
1284 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1285 // Until we have proper clock tree detection, this really awful hack that opportunistically
1286 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1287 // be if only one clock edge was simulated by replacing:
1288 // top.p_clk = value<1>{0u}; top.step();
1289 // top.p_clk = value<1>{1u}; top.step();
1290 // with:
1291 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1292 // Don't rely on this; it will be removed without warning.
1293 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1294 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1295 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1296 }
1297 }
1298 }
1299 auto assign_from_outputs = [&](bool cell_converged) {
1300 for (auto conn : cell->connections()) {
1301 if (cell->output(conn.first)) {
1302 if (conn.second.empty())
1303 continue; // ignore disconnected ports
1304 if (is_cxxrtl_sync_port(cell, conn.first))
1305 continue; // fully sync ports are handled in CELL_SYNC nodes
1306 f << indent;
1307 dump_sigspec_lhs(conn.second);
1308 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1309 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1310 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1311 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1312 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1313 // and consider the fate of the localized wires that used to be output ports.)
1314 //
1315 // It is not possible to know apriori whether the cell (which may be late bound) will converge immediately.
1316 // Because of this, the choice between using .curr (appropriate for buffered outputs) and .next (appropriate
1317 // for unbuffered outputs) is made at runtime.
1318 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1319 f << ".next;\n";
1320 else
1321 f << ".curr;\n";
1322 }
1323 }
1324 };
1325 if (buffered_inputs) {
1326 // If we have any buffered inputs, there's no chance of converging immediately.
1327 f << indent << mangle(cell) << access << "eval();\n";
1328 f << indent << "converged = false;\n";
1329 assign_from_outputs(/*cell_converged=*/false);
1330 } else {
1331 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1332 inc_indent();
1333 assign_from_outputs(/*cell_converged=*/true);
1334 dec_indent();
1335 f << indent << "} else {\n";
1336 inc_indent();
1337 f << indent << "converged = false;\n";
1338 assign_from_outputs(/*cell_converged=*/false);
1339 dec_indent();
1340 f << indent << "}\n";
1341 }
1342 }
1343 }
1344
1345 void dump_assign(const RTLIL::SigSig &sigsig)
1346 {
1347 f << indent;
1348 dump_sigspec_lhs(sigsig.first);
1349 f << " = ";
1350 dump_sigspec_rhs(sigsig.second);
1351 f << ";\n";
1352 }
1353
1354 void dump_case_rule(const RTLIL::CaseRule *rule)
1355 {
1356 for (auto action : rule->actions)
1357 dump_assign(action);
1358 for (auto switch_ : rule->switches)
1359 dump_switch_rule(switch_);
1360 }
1361
1362 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1363 {
1364 // The switch attributes are printed before the switch condition is captured.
1365 dump_attrs(rule);
1366 std::string signal_temp = fresh_temporary();
1367 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1368 dump_sigspec(rule->signal, /*is_lhs=*/false);
1369 f << ";\n";
1370
1371 bool first = true;
1372 for (auto case_ : rule->cases) {
1373 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1374 dump_attrs(rule);
1375 f << indent;
1376 if (!first)
1377 f << "} else ";
1378 first = false;
1379 if (!case_->compare.empty()) {
1380 f << "if (";
1381 bool first = true;
1382 for (auto &compare : case_->compare) {
1383 if (!first)
1384 f << " || ";
1385 first = false;
1386 if (compare.is_fully_def()) {
1387 f << signal_temp << " == ";
1388 dump_sigspec(compare, /*is_lhs=*/false);
1389 } else if (compare.is_fully_const()) {
1390 RTLIL::Const compare_mask, compare_value;
1391 for (auto bit : compare.as_const()) {
1392 switch (bit) {
1393 case RTLIL::S0:
1394 case RTLIL::S1:
1395 compare_mask.bits.push_back(RTLIL::S1);
1396 compare_value.bits.push_back(bit);
1397 break;
1398
1399 case RTLIL::Sx:
1400 case RTLIL::Sz:
1401 case RTLIL::Sa:
1402 compare_mask.bits.push_back(RTLIL::S0);
1403 compare_value.bits.push_back(RTLIL::S0);
1404 break;
1405
1406 default:
1407 log_assert(false);
1408 }
1409 }
1410 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1411 dump_const(compare_mask);
1412 f << ") == ";
1413 dump_const(compare_value);
1414 } else {
1415 log_assert(false);
1416 }
1417 }
1418 f << ") ";
1419 }
1420 f << "{\n";
1421 inc_indent();
1422 dump_case_rule(case_);
1423 dec_indent();
1424 }
1425 f << indent << "}\n";
1426 }
1427
1428 void dump_process(const RTLIL::Process *proc)
1429 {
1430 dump_attrs(proc);
1431 f << indent << "// process " << proc->name.str() << "\n";
1432 // The case attributes (for root case) are always empty.
1433 log_assert(proc->root_case.attributes.empty());
1434 dump_case_rule(&proc->root_case);
1435 for (auto sync : proc->syncs) {
1436 RTLIL::SigBit sync_bit;
1437 if (!sync->signal.empty()) {
1438 sync_bit = sync->signal[0];
1439 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1440 }
1441
1442 pool<std::string> events;
1443 switch (sync->type) {
1444 case RTLIL::STp:
1445 log_assert(sync_bit.wire != nullptr);
1446 events.insert("posedge_" + mangle(sync_bit));
1447 break;
1448 case RTLIL::STn:
1449 log_assert(sync_bit.wire != nullptr);
1450 events.insert("negedge_" + mangle(sync_bit));
1451 break;
1452 case RTLIL::STe:
1453 log_assert(sync_bit.wire != nullptr);
1454 events.insert("posedge_" + mangle(sync_bit));
1455 events.insert("negedge_" + mangle(sync_bit));
1456 break;
1457
1458 case RTLIL::STa:
1459 events.insert("true");
1460 break;
1461
1462 case RTLIL::ST0:
1463 case RTLIL::ST1:
1464 case RTLIL::STg:
1465 case RTLIL::STi:
1466 log_assert(false);
1467 }
1468 if (!events.empty()) {
1469 f << indent << "if (";
1470 bool first = true;
1471 for (auto &event : events) {
1472 if (!first)
1473 f << " || ";
1474 first = false;
1475 f << event;
1476 }
1477 f << ") {\n";
1478 inc_indent();
1479 for (auto action : sync->actions)
1480 dump_assign(action);
1481 dec_indent();
1482 f << indent << "}\n";
1483 }
1484 }
1485 }
1486
1487 void dump_wire(const RTLIL::Wire *wire, bool is_local)
1488 {
1489 if (is_local && localized_wires[wire] && !inlined_wires.count(wire)) {
1490 dump_attrs(wire);
1491 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1492 }
1493 if (!is_local && !localized_wires[wire]) {
1494 std::string width;
1495 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1496 width = wire->get_string_attribute(ID(cxxrtl_width));
1497 } else {
1498 width = std::to_string(wire->width);
1499 }
1500
1501 dump_attrs(wire);
1502 f << indent;
1503 if (wire->port_input && wire->port_output)
1504 f << "/*inout*/ ";
1505 else if (wire->port_input)
1506 f << "/*input*/ ";
1507 else if (wire->port_output)
1508 f << "/*output*/ ";
1509 f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1510 if (wire->has_attribute(ID::init)) {
1511 f << " ";
1512 dump_const_init(wire->attributes.at(ID::init));
1513 }
1514 f << ";\n";
1515 if (edge_wires[wire]) {
1516 if (unbuffered_wires[wire]) {
1517 f << indent << "value<" << width << "> prev_" << mangle(wire);
1518 if (wire->has_attribute(ID::init)) {
1519 f << " ";
1520 dump_const_init(wire->attributes.at(ID::init));
1521 }
1522 f << ";\n";
1523 }
1524 for (auto edge_type : edge_types) {
1525 if (edge_type.first.wire == wire) {
1526 std::string prev, next;
1527 if (unbuffered_wires[wire]) {
1528 prev = "prev_" + mangle(edge_type.first.wire);
1529 next = mangle(edge_type.first.wire);
1530 } else {
1531 prev = mangle(edge_type.first.wire) + ".curr";
1532 next = mangle(edge_type.first.wire) + ".next";
1533 }
1534 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1535 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1536 if (edge_type.second != RTLIL::STn) {
1537 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1538 inc_indent();
1539 f << indent << "return !" << prev << " && " << next << ";\n";
1540 dec_indent();
1541 f << indent << "}\n";
1542 }
1543 if (edge_type.second != RTLIL::STp) {
1544 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1545 inc_indent();
1546 f << indent << "return " << prev << " && !" << next << ";\n";
1547 dec_indent();
1548 f << indent << "}\n";
1549 }
1550 }
1551 }
1552 }
1553 }
1554 }
1555
1556 void dump_debug_wire(const RTLIL::Wire *wire, bool is_local)
1557 {
1558 if (!debug_outlined_wires[wire])
1559 return;
1560
1561 bool is_outlined_member = wire->name.isPublic() &&
1562 !(debug_const_wires.count(wire) || debug_alias_wires.count(wire));
1563 if (is_local && !is_outlined_member) {
1564 dump_attrs(wire);
1565 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1566 }
1567 if (!is_local && is_outlined_member) {
1568 dump_attrs(wire);
1569 f << indent << "/*outline*/ value<" << wire->width << "> " << mangle(wire) << ";\n";
1570 }
1571 }
1572
1573 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1574 {
1575 vector<const RTLIL::Cell*> init_cells;
1576 for (auto cell : module->cells())
1577 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1578 init_cells.push_back(cell);
1579
1580 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1581 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1582 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1583 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1584 });
1585
1586 dump_attrs(memory);
1587 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1588 << " { " << memory->size << "u";
1589 if (init_cells.empty()) {
1590 f << " };\n";
1591 } else {
1592 f << ",\n";
1593 inc_indent();
1594 for (auto cell : init_cells) {
1595 dump_attrs(cell);
1596 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1597 size_t width = cell->getParam(ID::WIDTH).as_int();
1598 size_t words = cell->getParam(ID::WORDS).as_int();
1599 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1600 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1601 inc_indent();
1602 for (size_t n = 0; n < words; n++) {
1603 if (n % 4 == 0)
1604 f << "\n" << indent;
1605 else
1606 f << " ";
1607 dump_const(data, width, n * width, /*fixed_width=*/true);
1608 f << ",";
1609 }
1610 dec_indent();
1611 f << "\n" << indent << "}},\n";
1612 }
1613 dec_indent();
1614 f << indent << "};\n";
1615 }
1616 }
1617
1618 void dump_eval_method(RTLIL::Module *module)
1619 {
1620 inc_indent();
1621 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1622 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1623 for (auto wire : module->wires()) {
1624 if (edge_wires[wire]) {
1625 for (auto edge_type : edge_types) {
1626 if (edge_type.first.wire == wire) {
1627 if (edge_type.second != RTLIL::STn) {
1628 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1629 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1630 }
1631 if (edge_type.second != RTLIL::STp) {
1632 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1633 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1634 }
1635 }
1636 }
1637 }
1638 }
1639 for (auto wire : module->wires())
1640 dump_wire(wire, /*is_local=*/true);
1641 for (auto node : schedule[module]) {
1642 switch (node.type) {
1643 case FlowGraph::Node::Type::CONNECT:
1644 dump_connect(node.connect);
1645 break;
1646 case FlowGraph::Node::Type::CELL_SYNC:
1647 dump_cell_sync(node.cell);
1648 break;
1649 case FlowGraph::Node::Type::CELL_EVAL:
1650 dump_cell_eval(node.cell);
1651 break;
1652 case FlowGraph::Node::Type::PROCESS:
1653 dump_process(node.process);
1654 break;
1655 }
1656 }
1657 }
1658 f << indent << "return converged;\n";
1659 dec_indent();
1660 }
1661
1662 void dump_debug_eval_method(RTLIL::Module *module)
1663 {
1664 inc_indent();
1665 for (auto wire : module->wires())
1666 dump_debug_wire(wire, /*is_local=*/true);
1667 for (auto node : schedule[module]) {
1668 switch (node.type) {
1669 case FlowGraph::Node::Type::CONNECT:
1670 dump_connect(node.connect, /*for_debug=*/true);
1671 break;
1672 case FlowGraph::Node::Type::CELL_EVAL:
1673 dump_cell_eval(node.cell, /*for_debug=*/true);
1674 break;
1675 case FlowGraph::Node::Type::CELL_SYNC:
1676 case FlowGraph::Node::Type::PROCESS:
1677 break;
1678 }
1679 }
1680 dec_indent();
1681 }
1682
1683 void dump_commit_method(RTLIL::Module *module)
1684 {
1685 inc_indent();
1686 f << indent << "bool changed = false;\n";
1687 for (auto wire : module->wires()) {
1688 if (inlined_wires.count(wire))
1689 continue;
1690 if (unbuffered_wires[wire]) {
1691 if (edge_wires[wire])
1692 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1693 continue;
1694 }
1695 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1696 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1697 }
1698 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1699 for (auto memory : module->memories) {
1700 if (!writable_memories[memory.second])
1701 continue;
1702 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1703 }
1704 for (auto cell : module->cells()) {
1705 if (is_internal_cell(cell->type))
1706 continue;
1707 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1708 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1709 }
1710 }
1711 f << indent << "return changed;\n";
1712 dec_indent();
1713 }
1714
1715 void dump_debug_info_method(RTLIL::Module *module)
1716 {
1717 size_t count_public_wires = 0;
1718 size_t count_const_wires = 0;
1719 size_t count_alias_wires = 0;
1720 size_t count_inline_wires = 0;
1721 size_t count_member_wires = 0;
1722 size_t count_skipped_wires = 0;
1723 size_t count_driven_sync = 0;
1724 size_t count_driven_comb = 0;
1725 size_t count_undriven = 0;
1726 size_t count_mixed_driver = 0;
1727 inc_indent();
1728 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1729 for (auto wire : module->wires()) {
1730 if (!wire->name.isPublic())
1731 continue;
1732 if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
1733 continue;
1734 count_public_wires++;
1735 if (debug_const_wires.count(wire)) {
1736 // Wire tied to a constant
1737 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1738 dump_const(debug_const_wires[wire]);
1739 f << ";\n";
1740 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1741 f << ", debug_item(const_" << mangle(wire) << ", ";
1742 f << wire->start_offset << "));\n";
1743 count_const_wires++;
1744 } else if (debug_alias_wires.count(wire)) {
1745 // Alias of a member wire
1746 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1747 f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
1748 f << wire->start_offset << "));\n";
1749 count_alias_wires++;
1750 } else if (debug_outlined_wires.count(wire)) {
1751 // Inlined but rematerializable wire
1752 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1753 f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", ";
1754 f << wire->start_offset << "));\n";
1755 count_inline_wires++;
1756 } else if (!localized_wires.count(wire)) {
1757 // Member wire
1758 std::vector<std::string> flags;
1759
1760 if (wire->port_input && wire->port_output)
1761 flags.push_back("INOUT");
1762 else if (wire->port_input)
1763 flags.push_back("INPUT");
1764 else if (wire->port_output)
1765 flags.push_back("OUTPUT");
1766
1767 bool has_driven_sync = false;
1768 bool has_driven_comb = false;
1769 bool has_undriven = false;
1770 SigSpec sig(wire);
1771 for (auto bit : sig.bits())
1772 if (!bit_has_state.count(bit))
1773 has_undriven = true;
1774 else if (bit_has_state[bit])
1775 has_driven_sync = true;
1776 else
1777 has_driven_comb = true;
1778 if (has_driven_sync)
1779 flags.push_back("DRIVEN_SYNC");
1780 if (has_driven_sync && !has_driven_comb && !has_undriven)
1781 count_driven_sync++;
1782 if (has_driven_comb)
1783 flags.push_back("DRIVEN_COMB");
1784 if (!has_driven_sync && has_driven_comb && !has_undriven)
1785 count_driven_comb++;
1786 if (has_undriven)
1787 flags.push_back("UNDRIVEN");
1788 if (!has_driven_sync && !has_driven_comb && has_undriven)
1789 count_undriven++;
1790 if (has_driven_sync + has_driven_comb + has_undriven > 1)
1791 count_mixed_driver++;
1792
1793 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1794 f << ", debug_item(" << mangle(wire) << ", ";
1795 f << wire->start_offset;
1796 bool first = true;
1797 for (auto flag : flags) {
1798 if (first) {
1799 first = false;
1800 f << ", ";
1801 } else {
1802 f << "|";
1803 }
1804 f << "debug_item::" << flag;
1805 }
1806 f << "));\n";
1807 count_member_wires++;
1808 } else {
1809 // Localized or inlined wire with no debug information
1810 count_skipped_wires++;
1811 }
1812 }
1813 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1814 for (auto &memory_it : module->memories) {
1815 if (!memory_it.first.isPublic())
1816 continue;
1817 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1818 f << ", debug_item(" << mangle(memory_it.second) << ", ";
1819 f << memory_it.second->start_offset << "));\n";
1820 }
1821 for (auto cell : module->cells()) {
1822 if (is_internal_cell(cell->type))
1823 continue;
1824 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1825 f << indent << mangle(cell) << access << "debug_info(items, ";
1826 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1827 }
1828 }
1829 dec_indent();
1830
1831 log_debug("Debug information statistics for module `%s':\n", log_id(module));
1832 log_debug(" Public wires: %zu, of which:\n", count_public_wires);
1833 log_debug(" Member wires: %zu, of which:\n", count_member_wires);
1834 log_debug(" Driven sync: %zu\n", count_driven_sync);
1835 log_debug(" Driven comb: %zu\n", count_driven_comb);
1836 log_debug(" Mixed driver: %zu\n", count_mixed_driver);
1837 log_debug(" Undriven: %zu\n", count_undriven);
1838 log_debug(" Inline wires: %zu\n", count_inline_wires);
1839 log_debug(" Alias wires: %zu\n", count_alias_wires);
1840 log_debug(" Const wires: %zu\n", count_const_wires);
1841 log_debug(" Other wires: %zu%s\n", count_skipped_wires,
1842 count_skipped_wires > 0 ? " (debug information unavailable)" : "");
1843 }
1844
1845 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1846 {
1847 if (metadata_map.empty()) {
1848 f << "metadata_map()";
1849 return;
1850 }
1851 f << "metadata_map({\n";
1852 inc_indent();
1853 for (auto metadata_item : metadata_map) {
1854 if (!metadata_item.first.begins_with("\\"))
1855 continue;
1856 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1857 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1858 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1859 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1860 f << escape_cxx_string(metadata_item.second.decode_string());
1861 } else {
1862 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1863 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1864 f << "u";
1865 }
1866 f << " },\n";
1867 }
1868 dec_indent();
1869 f << indent << "})";
1870 }
1871
1872 void dump_module_intf(RTLIL::Module *module)
1873 {
1874 dump_attrs(module);
1875 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1876 if (module->has_attribute(ID(cxxrtl_template)))
1877 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1878 f << indent << "struct " << mangle(module) << " : public module {\n";
1879 inc_indent();
1880 for (auto wire : module->wires()) {
1881 if (wire->port_id != 0)
1882 dump_wire(wire, /*is_local=*/false);
1883 }
1884 f << "\n";
1885 f << indent << "bool eval() override {\n";
1886 dump_eval_method(module);
1887 f << indent << "}\n";
1888 f << "\n";
1889 f << indent << "bool commit() override {\n";
1890 dump_commit_method(module);
1891 f << indent << "}\n";
1892 f << "\n";
1893 if (debug_info) {
1894 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1895 dump_debug_info_method(module);
1896 f << indent << "}\n";
1897 f << "\n";
1898 }
1899 f << indent << "static std::unique_ptr<" << mangle(module);
1900 f << template_params(module, /*is_decl=*/false) << "> ";
1901 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1902 dec_indent();
1903 f << indent << "}; // struct " << mangle(module) << "\n";
1904 f << "\n";
1905 if (blackbox_specializations.count(module)) {
1906 // If templated black boxes are used, the constructor of any module which includes the black box cell
1907 // (which calls the declared but not defined in the generated code `create` function) may only be used
1908 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1909 // a forward-declared explicit specialization.
1910 //
1911 // Option (b) makes it possible to have the generated code and the black box implementation in different
1912 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1913 // a specialization for every combination of parameters the generated code may use; but since the main
1914 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1915 // be very few such combinations anyway.
1916 for (auto specialization : blackbox_specializations[module]) {
1917 f << indent << "template<>\n";
1918 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1919 f << mangle(module) << specialization << "::";
1920 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1921 f << "\n";
1922 }
1923 }
1924 } else {
1925 f << indent << "struct " << mangle(module) << " : public module {\n";
1926 inc_indent();
1927 for (auto wire : module->wires())
1928 dump_wire(wire, /*is_local=*/false);
1929 for (auto wire : module->wires())
1930 dump_debug_wire(wire, /*is_local=*/false);
1931 bool has_memories = false;
1932 for (auto memory : module->memories) {
1933 dump_memory(module, memory.second);
1934 has_memories = true;
1935 }
1936 if (has_memories)
1937 f << "\n";
1938 bool has_cells = false;
1939 for (auto cell : module->cells()) {
1940 if (is_internal_cell(cell->type))
1941 continue;
1942 dump_attrs(cell);
1943 RTLIL::Module *cell_module = module->design->module(cell->type);
1944 log_assert(cell_module != nullptr);
1945 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1946 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1947 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1948 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1949 dump_metadata_map(cell->parameters);
1950 f << ", ";
1951 dump_metadata_map(cell->attributes);
1952 f << ");\n";
1953 } else {
1954 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1955 }
1956 has_cells = true;
1957 }
1958 if (has_cells)
1959 f << "\n";
1960 f << indent << mangle(module) << "() {}\n";
1961 if (has_cells) {
1962 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) :\n";
1963 bool first = true;
1964 for (auto cell : module->cells()) {
1965 if (is_internal_cell(cell->type))
1966 continue;
1967 if (first) {
1968 first = false;
1969 } else {
1970 f << ",\n";
1971 }
1972 RTLIL::Module *cell_module = module->design->module(cell->type);
1973 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1974 f << indent << " " << mangle(cell) << "(std::move(other." << mangle(cell) << "))";
1975 } else {
1976 f << indent << " " << mangle(cell) << "(adopt {}, std::move(other." << mangle(cell) << "))";
1977 }
1978 }
1979 f << " {\n";
1980 inc_indent();
1981 for (auto cell : module->cells()) {
1982 if (is_internal_cell(cell->type))
1983 continue;
1984 RTLIL::Module *cell_module = module->design->module(cell->type);
1985 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
1986 f << indent << mangle(cell) << "->reset();\n";
1987 }
1988 dec_indent();
1989 f << indent << "}\n";
1990 } else {
1991 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) {}\n";
1992 }
1993 f << "\n";
1994 f << indent << "void reset() override {\n";
1995 inc_indent();
1996 f << indent << "*this = " << mangle(module) << "(adopt {}, std::move(*this));\n";
1997 dec_indent();
1998 f << indent << "}\n";
1999 f << "\n";
2000 f << indent << "bool eval() override;\n";
2001 f << indent << "bool commit() override;\n";
2002 if (debug_info) {
2003 if (debug_eval) {
2004 f << "\n";
2005 f << indent << "void debug_eval();\n";
2006 for (auto wire : module->wires())
2007 if (debug_outlined_wires.count(wire)) {
2008 f << indent << "debug_outline debug_eval_outline { std::bind(&"
2009 << mangle(module) << "::debug_eval, this) };\n";
2010 break;
2011 }
2012 }
2013 f << "\n";
2014 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
2015 }
2016 dec_indent();
2017 f << indent << "}; // struct " << mangle(module) << "\n";
2018 f << "\n";
2019 }
2020 }
2021
2022 void dump_module_impl(RTLIL::Module *module)
2023 {
2024 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
2025 return;
2026 f << indent << "bool " << mangle(module) << "::eval() {\n";
2027 dump_eval_method(module);
2028 f << indent << "}\n";
2029 f << "\n";
2030 f << indent << "bool " << mangle(module) << "::commit() {\n";
2031 dump_commit_method(module);
2032 f << indent << "}\n";
2033 f << "\n";
2034 if (debug_info) {
2035 if (debug_eval) {
2036 f << indent << "void " << mangle(module) << "::debug_eval() {\n";
2037 dump_debug_eval_method(module);
2038 f << indent << "}\n";
2039 f << "\n";
2040 }
2041 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
2042 dump_debug_info_method(module);
2043 f << indent << "}\n";
2044 f << "\n";
2045 }
2046 }
2047
2048 void dump_design(RTLIL::Design *design)
2049 {
2050 RTLIL::Module *top_module = nullptr;
2051 std::vector<RTLIL::Module*> modules;
2052 TopoSort<RTLIL::Module*> topo_design;
2053 for (auto module : design->modules()) {
2054 if (!design->selected_module(module))
2055 continue;
2056 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
2057 modules.push_back(module); // cxxrtl blackboxes first
2058 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
2059 continue;
2060 if (module->get_bool_attribute(ID::top))
2061 top_module = module;
2062
2063 topo_design.node(module);
2064 for (auto cell : module->cells()) {
2065 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
2066 continue;
2067 RTLIL::Module *cell_module = design->module(cell->type);
2068 log_assert(cell_module != nullptr);
2069 topo_design.edge(cell_module, module);
2070 }
2071 }
2072 bool no_loops = topo_design.sort();
2073 log_assert(no_loops);
2074 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
2075
2076 if (split_intf) {
2077 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
2078 std::string include_guard = design_ns + "_header";
2079 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
2080
2081 f << "#ifndef " << include_guard << "\n";
2082 f << "#define " << include_guard << "\n";
2083 f << "\n";
2084 if (top_module != nullptr && debug_info) {
2085 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
2086 f << "\n";
2087 f << "#ifdef __cplusplus\n";
2088 f << "extern \"C\" {\n";
2089 f << "#endif\n";
2090 f << "\n";
2091 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
2092 f << "\n";
2093 f << "#ifdef __cplusplus\n";
2094 f << "}\n";
2095 f << "#endif\n";
2096 f << "\n";
2097 } else {
2098 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
2099 f << "\n";
2100 }
2101 f << "#ifdef __cplusplus\n";
2102 f << "\n";
2103 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2104 f << "\n";
2105 f << "using namespace cxxrtl;\n";
2106 f << "\n";
2107 f << "namespace " << design_ns << " {\n";
2108 f << "\n";
2109 for (auto module : modules)
2110 dump_module_intf(module);
2111 f << "} // namespace " << design_ns << "\n";
2112 f << "\n";
2113 f << "#endif // __cplusplus\n";
2114 f << "\n";
2115 f << "#endif\n";
2116 *intf_f << f.str(); f.str("");
2117 }
2118
2119 if (split_intf)
2120 f << "#include \"" << intf_filename << "\"\n";
2121 else
2122 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2123 f << "\n";
2124 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
2125 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2126 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
2127 f << "#endif\n";
2128 f << "\n";
2129 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2130 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
2131 f << "#endif\n";
2132 f << "\n";
2133 f << "using namespace cxxrtl_yosys;\n";
2134 f << "\n";
2135 f << "namespace " << design_ns << " {\n";
2136 f << "\n";
2137 for (auto module : modules) {
2138 if (!split_intf)
2139 dump_module_intf(module);
2140 dump_module_impl(module);
2141 }
2142 f << "} // namespace " << design_ns << "\n";
2143 f << "\n";
2144 if (top_module != nullptr && debug_info) {
2145 f << "extern \"C\"\n";
2146 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
2147 inc_indent();
2148 std::string top_type = design_ns + "::" + mangle(top_module);
2149 f << indent << "return new _cxxrtl_toplevel { ";
2150 f << "std::unique_ptr<" << top_type << ">(new " + top_type + ")";
2151 f << " };\n";
2152 dec_indent();
2153 f << "}\n";
2154 }
2155
2156 *impl_f << f.str(); f.str("");
2157 }
2158
2159 // Edge-type sync rules require us to emit edge detectors, which require coordination between
2160 // eval and commit phases. To do this we need to collect them upfront.
2161 //
2162 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
2163 // operate at wire bit granularity; it is possible to have code similar to:
2164 // wire [3:0] clocks;
2165 // always @(posedge clocks[0]) ...
2166 // To handle this we track edge sensitivity both for wires and wire bits.
2167 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
2168 {
2169 signal = sigmap(signal);
2170 log_assert(signal.is_wire() && signal.is_bit());
2171 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
2172
2173 RTLIL::SigBit sigbit = signal[0];
2174 if (!edge_types.count(sigbit))
2175 edge_types[sigbit] = type;
2176 else if (edge_types[sigbit] != type)
2177 edge_types[sigbit] = RTLIL::STe;
2178 edge_wires.insert(signal.as_wire());
2179 }
2180
2181 void analyze_design(RTLIL::Design *design)
2182 {
2183 bool has_feedback_arcs = false;
2184 bool has_buffered_comb_wires = false;
2185
2186 for (auto module : design->modules()) {
2187 if (!design->selected_module(module))
2188 continue;
2189
2190 SigMap &sigmap = sigmaps[module];
2191 sigmap.set(module);
2192
2193 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
2194 for (auto port : module->ports) {
2195 RTLIL::Wire *wire = module->wire(port);
2196 if (wire->port_input && !wire->port_output)
2197 unbuffered_wires.insert(wire);
2198 if (wire->has_attribute(ID(cxxrtl_edge))) {
2199 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
2200 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
2201 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
2202 log_id(module), log_signal(wire));
2203
2204 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
2205 for (int i = 0; i < GetSize(wire); i++) {
2206 RTLIL::SigSpec wire_sig = wire;
2207 switch (edges[i]) {
2208 case '-': break;
2209 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
2210 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
2211 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
2212 default:
2213 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
2214 "other than '-', 'p', 'n', or 'a'.\n",
2215 log_id(module), log_signal(wire));
2216 }
2217 }
2218 }
2219 }
2220
2221 // Black boxes converge by default, since their implementations are quite unlikely to require
2222 // internal propagation of comb signals.
2223 eval_converges[module] = true;
2224 continue;
2225 }
2226
2227 FlowGraph flow;
2228
2229 for (auto conn : module->connections())
2230 flow.add_node(conn);
2231
2232 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
2233 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
2234 pool<const RTLIL::Cell*>> memwr_per_domain;
2235 for (auto cell : module->cells()) {
2236 if (!cell->known())
2237 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2238
2239 RTLIL::Module *cell_module = design->module(cell->type);
2240 if (cell_module &&
2241 cell_module->get_blackbox_attribute() &&
2242 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2243 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2244
2245 if (cell_module &&
2246 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2247 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2248 blackbox_specializations[cell_module].insert(template_args(cell));
2249
2250 FlowGraph::Node *node = flow.add_node(cell);
2251
2252 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2253 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
2254 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2255 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2256 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2257 }
2258 // Similar for memory port cells.
2259 if (cell->type.in(ID($memrd), ID($memwr))) {
2260 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2261 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2262 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2263 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2264 }
2265 memrw_cell_nodes[cell] = node;
2266 }
2267 // Optimize access to read-only memories.
2268 if (cell->type == ID($memwr))
2269 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2270 // Collect groups of memory write ports in the same domain.
2271 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2272 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2273 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2274 memwr_per_domain[{clk_bit, memory}].insert(cell);
2275 }
2276 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2277 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2278 if (cell->type.in(ID($mem)))
2279 log_assert(false);
2280 }
2281 for (auto cell : module->cells()) {
2282 // Collect groups of memory write ports read by every transparent read port.
2283 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2284 cell->getParam(ID::TRANSPARENT).as_bool()) {
2285 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2286 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2287 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2288 transparent_for[cell].insert(memwr_cell);
2289 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2290 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2291 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2292 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2293 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2294 }
2295 }
2296 }
2297
2298 for (auto proc : module->processes) {
2299 flow.add_node(proc.second);
2300
2301 for (auto sync : proc.second->syncs)
2302 switch (sync->type) {
2303 // Edge-type sync rules require pre-registration.
2304 case RTLIL::STp:
2305 case RTLIL::STn:
2306 case RTLIL::STe:
2307 register_edge_signal(sigmap, sync->signal, sync->type);
2308 break;
2309
2310 // Level-type sync rules require no special handling.
2311 case RTLIL::ST0:
2312 case RTLIL::ST1:
2313 case RTLIL::STa:
2314 break;
2315
2316 case RTLIL::STg:
2317 log_cmd_error("Global clock is not supported.\n");
2318
2319 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2320 // attribute regardless of input.
2321 case RTLIL::STi:
2322 log_assert(false);
2323 }
2324 }
2325
2326 for (auto wire : module->wires()) {
2327 if (!flow.is_inlinable(wire)) continue;
2328 if (wire->port_id != 0) continue;
2329 if (wire->get_bool_attribute(ID::keep)) continue;
2330 if (wire->name.begins_with("$") && !inline_internal) continue;
2331 if (wire->name.begins_with("\\") && !inline_public) continue;
2332 if (edge_wires[wire]) continue;
2333 if (flow.wire_comb_defs[wire].size() > 1)
2334 log_cmd_error("Wire %s.%s has multiple drivers.\n", log_id(module), log_id(wire));
2335 log_assert(flow.wire_comb_defs[wire].size() == 1);
2336 inlined_wires[wire] = **flow.wire_comb_defs[wire].begin();
2337 }
2338
2339 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2340 for (auto wire_comb_def : flow.wire_comb_defs)
2341 for (auto node : wire_comb_def.second)
2342 node_defs[node].insert(wire_comb_def.first);
2343
2344 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_uses;
2345 for (auto wire_use : flow.wire_uses)
2346 for (auto node : wire_use.second)
2347 node_uses[node].insert(wire_use.first);
2348
2349 Scheduler<FlowGraph::Node> scheduler;
2350 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2351 for (auto node : flow.nodes)
2352 node_map[node] = scheduler.add(node);
2353 for (auto node_def : node_defs) {
2354 auto vertex = node_map[node_def.first];
2355 for (auto wire : node_def.second)
2356 for (auto succ_node : flow.wire_uses[wire]) {
2357 auto succ_vertex = node_map[succ_node];
2358 vertex->succs.insert(succ_vertex);
2359 succ_vertex->preds.insert(vertex);
2360 }
2361 }
2362
2363 auto eval_order = scheduler.schedule();
2364 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2365 pool<const RTLIL::Wire*> feedback_wires;
2366 for (auto vertex : eval_order) {
2367 auto node = vertex->data;
2368 schedule[module].push_back(*node);
2369 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2370 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2371 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2372 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2373 evaluated.insert(node);
2374 for (auto wire : node_defs[node])
2375 for (auto succ_node : flow.wire_uses[wire])
2376 if (evaluated[succ_node]) {
2377 feedback_wires.insert(wire);
2378 // Feedback wires may never be inlined because feedback requires state, but the point of
2379 // inlining (and localization) is to eliminate state.
2380 inlined_wires.erase(wire);
2381 }
2382 }
2383
2384 if (!feedback_wires.empty()) {
2385 has_feedback_arcs = true;
2386 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2387 for (auto wire : feedback_wires)
2388 log(" %s\n", log_id(wire));
2389 }
2390
2391 for (auto wire : module->wires()) {
2392 if (feedback_wires[wire]) continue;
2393 if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
2394 if (wire->name.begins_with("$") && !unbuffer_internal) continue;
2395 if (wire->name.begins_with("\\") && !unbuffer_public) continue;
2396 if (flow.wire_sync_defs.count(wire) > 0) continue;
2397 unbuffered_wires.insert(wire);
2398 if (edge_wires[wire]) continue;
2399 if (wire->get_bool_attribute(ID::keep)) continue;
2400 if (wire->port_input || wire->port_output) continue;
2401 if (wire->name.begins_with("$") && !localize_internal) continue;
2402 if (wire->name.begins_with("\\") && !localize_public) continue;
2403 localized_wires.insert(wire);
2404 }
2405
2406 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2407 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2408 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2409 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2410 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2411 // also require more than one delta cycle to converge.
2412 pool<const RTLIL::Wire*> buffered_comb_wires;
2413 for (auto wire : module->wires()) {
2414 if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
2415 buffered_comb_wires.insert(wire);
2416 }
2417 if (!buffered_comb_wires.empty()) {
2418 has_buffered_comb_wires = true;
2419 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2420 for (auto wire : buffered_comb_wires)
2421 log(" %s\n", log_id(wire));
2422 }
2423
2424 eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
2425
2426 for (auto item : flow.bit_has_state)
2427 bit_has_state.insert(item);
2428
2429 if (debug_info && debug_eval) {
2430 // Find wires that can be be outlined, i.e. whose values can be always recovered from
2431 // the values of other wires. (This is the inverse of inlining--any wire that can be
2432 // inlined can also be outlined.) Although this may seem strictly less efficient, since
2433 // such values are computed at least twice, second-order effects make outlining useful.
2434 pool<const RTLIL::Wire*> worklist, visited;
2435 for (auto wire : module->wires()) {
2436 if (!wire->name.isPublic())
2437 continue;
2438 worklist.insert(wire);
2439 }
2440 while (!worklist.empty()) {
2441 const RTLIL::Wire *wire = worklist.pop();
2442 visited.insert(wire);
2443 if (!localized_wires.count(wire) && !inlined_wires.count(wire))
2444 continue; // member wire, doesn't need outlining
2445 if (wire->name.isPublic() || !inlined_wires.count(wire))
2446 debug_outlined_wires.insert(wire); // allow outlining of internal wires only
2447 for (auto node : flow.wire_comb_defs[wire])
2448 for (auto node_use : node_uses[node])
2449 if (!visited.count(node_use))
2450 worklist.insert(node_use);
2451 }
2452 }
2453 if (debug_info && debug_alias) {
2454 // Find wires that alias other wires or are tied to a constant. Both of these cases are
2455 // directly expressible in the debug information, improving coverage at zero cost.
2456 for (auto wire : module->wires()) {
2457 if (!wire->name.isPublic())
2458 continue;
2459 const RTLIL::Wire *cursor = wire;
2460 RTLIL::SigSpec alias_of;
2461 while (1) {
2462 if (!(flow.wire_def_inlinable.count(cursor) && flow.wire_def_inlinable[cursor]))
2463 break; // not an alias: complex def
2464 log_assert(flow.wire_comb_defs[cursor].size() == 1);
2465 FlowGraph::Node *node = *flow.wire_comb_defs[cursor].begin();
2466 if (node->type != FlowGraph::Node::Type::CONNECT)
2467 break; // not an alias: def by cell
2468 RTLIL::SigSpec rhs_sig = node->connect.second;
2469 if (rhs_sig.is_fully_const()) {
2470 alias_of = rhs_sig; // alias of const
2471 break;
2472 } else if (rhs_sig.is_wire()) {
2473 RTLIL::Wire *rhs_wire = rhs_sig.as_wire(); // possible alias of wire
2474 if (rhs_wire->port_input && !rhs_wire->port_output) {
2475 alias_of = rhs_wire; // alias of input
2476 break;
2477 } else if (!localized_wires.count(rhs_wire) && !inlined_wires.count(rhs_wire)) {
2478 alias_of = rhs_wire; // alias of member
2479 break;
2480 } else {
2481 if (rhs_wire->name.isPublic() && debug_outlined_wires.count(rhs_wire))
2482 alias_of = rhs_wire; // alias of either outline or another alias
2483 cursor = rhs_wire; // keep looking
2484 }
2485 } else {
2486 break; // not an alias: complex rhs
2487 }
2488 }
2489 if (alias_of.empty()) {
2490 continue;
2491 } else if (alias_of.is_fully_const()) {
2492 debug_const_wires[wire] = alias_of.as_const();
2493 } else if (alias_of.is_wire()) {
2494 debug_alias_wires[wire] = alias_of.as_wire();
2495 } else log_abort();
2496 if (inlined_wires.count(wire))
2497 debug_outlined_wires.erase(wire);
2498 }
2499 }
2500 }
2501 if (has_feedback_arcs || has_buffered_comb_wires) {
2502 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2503 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2504 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2505 const char *why_pessimistic = nullptr;
2506 if (has_feedback_arcs)
2507 why_pessimistic = "feedback wires";
2508 else if (has_buffered_comb_wires)
2509 why_pessimistic = "buffered combinatorial wires";
2510 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2511 if (!run_flatten)
2512 log("Flattening may eliminate %s from the design.\n", why_pessimistic);
2513 if (!run_proc)
2514 log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic);
2515 }
2516 }
2517
2518 void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init, bool &has_packed_mem)
2519 {
2520 has_sync_init = has_packed_mem = has_top = false;
2521
2522 for (auto module : design->modules()) {
2523 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2524 continue;
2525
2526 if (!design->selected_whole_module(module))
2527 if (design->selected_module(module))
2528 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2529 if (!design->selected_module(module))
2530 continue;
2531
2532 if (module->get_bool_attribute(ID::top))
2533 has_top = true;
2534
2535 for (auto proc : module->processes)
2536 for (auto sync : proc.second->syncs)
2537 if (sync->type == RTLIL::STi)
2538 has_sync_init = true;
2539
2540 // The Mem constructor also checks for well-formedness of $meminit cells, if any.
2541 for (auto &mem : Mem::get_all_memories(module))
2542 if (mem.packed)
2543 has_packed_mem = true;
2544 }
2545 }
2546
2547 void prepare_design(RTLIL::Design *design)
2548 {
2549 bool did_anything = false;
2550 bool has_top, has_sync_init, has_packed_mem;
2551 log_push();
2552 check_design(design, has_top, has_sync_init, has_packed_mem);
2553 if (run_hierarchy && !has_top) {
2554 Pass::call(design, "hierarchy -auto-top");
2555 did_anything = true;
2556 }
2557 if (run_flatten) {
2558 Pass::call(design, "flatten");
2559 did_anything = true;
2560 }
2561 if (run_proc) {
2562 Pass::call(design, "proc");
2563 did_anything = true;
2564 } else if (has_sync_init) {
2565 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2566 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2567 Pass::call(design, "proc_prune");
2568 Pass::call(design, "proc_clean");
2569 Pass::call(design, "proc_init");
2570 did_anything = true;
2571 }
2572 if (has_packed_mem) {
2573 Pass::call(design, "memory_unpack");
2574 did_anything = true;
2575 }
2576 // Recheck the design if it was modified.
2577 if (did_anything)
2578 check_design(design, has_top, has_sync_init, has_packed_mem);
2579 log_assert(has_top && !has_sync_init && !has_packed_mem);
2580 log_pop();
2581 if (did_anything)
2582 log_spacer();
2583 analyze_design(design);
2584 }
2585 };
2586
2587 struct CxxrtlBackend : public Backend {
2588 static const int DEFAULT_OPT_LEVEL = 6;
2589 static const int DEFAULT_DEBUG_LEVEL = 3;
2590
2591 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2592 void help() override
2593 {
2594 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2595 log("\n");
2596 log(" write_cxxrtl [options] [filename]\n");
2597 log("\n");
2598 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2599 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2600 log("\n");
2601 log("The following driver may be used as an example for a design with a single clock\n");
2602 log("driving rising edge triggered flip-flops:\n");
2603 log("\n");
2604 log(" #include \"top.cc\"\n");
2605 log("\n");
2606 log(" int main() {\n");
2607 log(" cxxrtl_design::p_top top;\n");
2608 log(" top.step();\n");
2609 log(" while (1) {\n");
2610 log(" /* user logic */\n");
2611 log(" top.p_clk.set(false);\n");
2612 log(" top.step();\n");
2613 log(" top.p_clk.set(true);\n");
2614 log(" top.step();\n");
2615 log(" }\n");
2616 log(" }\n");
2617 log("\n");
2618 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2619 log("subject to race conditions. If, in the example above, the user logic would run\n");
2620 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2621 log("\n");
2622 log("This backend supports replacing parts of the design with black boxes implemented\n");
2623 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2624 log("and the generated code consists only of an interface and a factory function.\n");
2625 log("The driver must implement the factory function that creates an implementation of\n");
2626 log("the black box, taking into account the parameters it is instantiated with.\n");
2627 log("\n");
2628 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2629 log("a synchronous debug sink:\n");
2630 log("\n");
2631 log(" (* cxxrtl_blackbox *)\n");
2632 log(" module debug(...);\n");
2633 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2634 log(" input en;\n");
2635 log(" input [7:0] i_data;\n");
2636 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2637 log(" endmodule\n");
2638 log("\n");
2639 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2640 log("\n");
2641 log(" struct bb_p_debug : public module {\n");
2642 log(" value<1> p_clk;\n");
2643 log(" bool posedge_p_clk() const { /* ... */ }\n");
2644 log(" value<1> p_en;\n");
2645 log(" value<8> p_i_data;\n");
2646 log(" wire<8> p_o_data;\n");
2647 log("\n");
2648 log(" bool eval() override;\n");
2649 log(" bool commit() override;\n");
2650 log("\n");
2651 log(" static std::unique_ptr<bb_p_debug>\n");
2652 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2653 log(" };\n");
2654 log("\n");
2655 log("The `create' function must be implemented by the driver. For example, it could\n");
2656 log("always provide an implementation logging the values to standard error stream:\n");
2657 log("\n");
2658 log(" namespace cxxrtl_design {\n");
2659 log("\n");
2660 log(" struct stderr_debug : public bb_p_debug {\n");
2661 log(" bool eval() override {\n");
2662 log(" if (posedge_p_clk() && p_en)\n");
2663 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2664 log(" p_o_data.next = p_i_data;\n");
2665 log(" return bb_p_debug::eval();\n");
2666 log(" }\n");
2667 log(" };\n");
2668 log("\n");
2669 log(" std::unique_ptr<bb_p_debug>\n");
2670 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2671 log(" cxxrtl::metadata_map attributes) {\n");
2672 log(" return std::make_unique<stderr_debug>();\n");
2673 log(" }\n");
2674 log("\n");
2675 log(" }\n");
2676 log("\n");
2677 log("For complex applications of black boxes, it is possible to parameterize their\n");
2678 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2679 log("interface for a configurable width debug sink:\n");
2680 log("\n");
2681 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2682 log(" module debug(...);\n");
2683 log(" parameter WIDTH = 8;\n");
2684 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2685 log(" input en;\n");
2686 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2687 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2688 log(" endmodule\n");
2689 log("\n");
2690 log("For this parametric HDL interface, this backend will generate the following C++\n");
2691 log("interface (only the differences are shown):\n");
2692 log("\n");
2693 log(" template<size_t WIDTH>\n");
2694 log(" struct bb_p_debug : public module {\n");
2695 log(" // ...\n");
2696 log(" value<WIDTH> p_i_data;\n");
2697 log(" wire<WIDTH> p_o_data;\n");
2698 log(" // ...\n");
2699 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2700 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2701 log(" };\n");
2702 log("\n");
2703 log("The `create' function must be implemented by the driver, specialized for every\n");
2704 log("possible combination of template parameters. (Specialization is necessary to\n");
2705 log("enable separate compilation of generated code and black box implementations.)\n");
2706 log("\n");
2707 log(" template<size_t SIZE>\n");
2708 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2709 log(" // ...\n");
2710 log(" };\n");
2711 log("\n");
2712 log(" template<>\n");
2713 log(" std::unique_ptr<bb_p_debug<8>>\n");
2714 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2715 log(" cxxrtl::metadata_map attributes) {\n");
2716 log(" return std::make_unique<stderr_debug<8>>();\n");
2717 log(" }\n");
2718 log("\n");
2719 log("The following attributes are recognized by this backend:\n");
2720 log("\n");
2721 log(" cxxrtl_blackbox\n");
2722 log(" only valid on modules. if specified, the module contents are ignored,\n");
2723 log(" and the generated code includes only the module interface and a factory\n");
2724 log(" function, which will be called to instantiate the module.\n");
2725 log("\n");
2726 log(" cxxrtl_edge\n");
2727 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2728 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2729 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2730 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2731 log("\n");
2732 log(" cxxrtl_template\n");
2733 log(" only valid on black boxes. must contain a space separated sequence of\n");
2734 log(" identifiers that have a corresponding black box parameters. for each\n");
2735 log(" of them, the generated code includes a `size_t` template parameter.\n");
2736 log("\n");
2737 log(" cxxrtl_width\n");
2738 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2739 log(" is directly inserted into generated code.\n");
2740 log("\n");
2741 log(" cxxrtl_comb, cxxrtl_sync\n");
2742 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2743 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2744 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2745 log(" if neither is specified, the output will be pessimistically treated as\n");
2746 log(" driven by both combinatorial and synchronous logic.\n");
2747 log("\n");
2748 log("The following options are supported by this backend:\n");
2749 log("\n");
2750 log(" -header\n");
2751 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2752 log(" if specified, the backend must be called with a filename, and filename\n");
2753 log(" of the interface is derived from filename of the implementation.\n");
2754 log(" otherwise, interface and implementation are generated together.\n");
2755 log("\n");
2756 log(" -namespace <ns-name>\n");
2757 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2758 log(" \"cxxrtl_design\" is used.\n");
2759 log("\n");
2760 log(" -nohierarchy\n");
2761 log(" use design hierarchy as-is. in most designs, a top module should be\n");
2762 log(" present as it is exposed through the C API and has unbuffered outputs\n");
2763 log(" for improved performance; it will be determined automatically if absent.\n");
2764 log("\n");
2765 log(" -noflatten\n");
2766 log(" don't flatten the design. fully flattened designs can evaluate within\n");
2767 log(" one delta cycle if they have no combinatorial feedback.\n");
2768 log(" note that the debug interface and waveform dumps use full hierarchical\n");
2769 log(" names for all wires even in flattened designs.\n");
2770 log("\n");
2771 log(" -noproc\n");
2772 log(" don't convert processes to netlists. in most designs, converting\n");
2773 log(" processes significantly improves evaluation performance at the cost of\n");
2774 log(" slight increase in compilation time.\n");
2775 log("\n");
2776 log(" -O <level>\n");
2777 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2778 log(" levels dramatically decrease compile and run time, and highest level\n");
2779 log(" possible for a design should be used.\n");
2780 log("\n");
2781 log(" -O0\n");
2782 log(" no optimization.\n");
2783 log("\n");
2784 log(" -O1\n");
2785 log(" localize internal wires if possible.\n");
2786 log("\n");
2787 log(" -O2\n");
2788 log(" like -O1, and unbuffer internal wires if possible.\n");
2789 log("\n");
2790 log(" -O3\n");
2791 log(" like -O2, and inline internal wires if possible.\n");
2792 log("\n");
2793 log(" -O4\n");
2794 log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
2795 log("\n");
2796 log(" -O5\n");
2797 log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
2798 log("\n");
2799 log(" -O6\n");
2800 log(" like -O5, and inline public wires not marked (*keep*) if possible.\n");
2801 log("\n");
2802 log(" -g <level>\n");
2803 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2804 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2805 log("\n");
2806 log(" -g0\n");
2807 log(" no debug information. the C API is unavailable.\n");
2808 log("\n");
2809 log(" -g1\n");
2810 log(" debug information for member public wires only. this is the bare minimum\n");
2811 log(" necessary to access all design state. enables the C API.\n");
2812 log("\n");
2813 log(" -g2\n");
2814 log(" like -g1, and include debug information for public wires that are tied\n");
2815 log(" to a constant or another public wire.\n");
2816 log("\n");
2817 log(" -g3\n");
2818 log(" like -g2, and compute debug information on demand for all public wires\n");
2819 log(" that were optimized out.\n");
2820 log("\n");
2821 }
2822
2823 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
2824 {
2825 bool nohierarchy = false;
2826 bool noflatten = false;
2827 bool noproc = false;
2828 int opt_level = DEFAULT_OPT_LEVEL;
2829 int debug_level = DEFAULT_DEBUG_LEVEL;
2830 CxxrtlWorker worker;
2831
2832 log_header(design, "Executing CXXRTL backend.\n");
2833
2834 size_t argidx;
2835 for (argidx = 1; argidx < args.size(); argidx++)
2836 {
2837 if (args[argidx] == "-nohierarchy") {
2838 nohierarchy = true;
2839 continue;
2840 }
2841 if (args[argidx] == "-noflatten") {
2842 noflatten = true;
2843 continue;
2844 }
2845 if (args[argidx] == "-noproc") {
2846 noproc = true;
2847 continue;
2848 }
2849 if (args[argidx] == "-Og") {
2850 log_warning("The `-Og` option has been removed. Use `-g3` instead for complete "
2851 "design coverage regardless of optimization level.\n");
2852 continue;
2853 }
2854 if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
2855 argidx++;
2856 log_warning("The `-Og` option has been removed. Use `-g3` instead for complete "
2857 "design coverage regardless of optimization level.\n");
2858 continue;
2859 }
2860 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2861 opt_level = std::stoi(args[++argidx]);
2862 continue;
2863 }
2864 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2865 opt_level = std::stoi(args[argidx].substr(2));
2866 continue;
2867 }
2868 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2869 debug_level = std::stoi(args[++argidx]);
2870 continue;
2871 }
2872 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2873 debug_level = std::stoi(args[argidx].substr(2));
2874 continue;
2875 }
2876 if (args[argidx] == "-header") {
2877 worker.split_intf = true;
2878 continue;
2879 }
2880 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2881 worker.design_ns = args[++argidx];
2882 continue;
2883 }
2884 break;
2885 }
2886 extra_args(f, filename, args, argidx);
2887
2888 worker.run_hierarchy = !nohierarchy;
2889 worker.run_flatten = !noflatten;
2890 worker.run_proc = !noproc;
2891 switch (opt_level) {
2892 // the highest level here must match DEFAULT_OPT_LEVEL
2893 case 6:
2894 worker.inline_public = true;
2895 YS_FALLTHROUGH
2896 case 5:
2897 worker.localize_public = true;
2898 YS_FALLTHROUGH
2899 case 4:
2900 worker.unbuffer_public = true;
2901 YS_FALLTHROUGH
2902 case 3:
2903 worker.inline_internal = true;
2904 YS_FALLTHROUGH
2905 case 2:
2906 worker.localize_internal = true;
2907 YS_FALLTHROUGH
2908 case 1:
2909 worker.unbuffer_internal = true;
2910 YS_FALLTHROUGH
2911 case 0:
2912 break;
2913 default:
2914 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2915 }
2916 switch (debug_level) {
2917 // the highest level here must match DEFAULT_DEBUG_LEVEL
2918 case 3:
2919 worker.debug_eval = true;
2920 YS_FALLTHROUGH
2921 case 2:
2922 worker.debug_alias = true;
2923 YS_FALLTHROUGH
2924 case 1:
2925 worker.debug_info = true;
2926 YS_FALLTHROUGH
2927 case 0:
2928 break;
2929 default:
2930 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2931 }
2932
2933 std::ofstream intf_f;
2934 if (worker.split_intf) {
2935 if (filename == "<stdout>")
2936 log_cmd_error("Option -header must be used with a filename.\n");
2937
2938 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2939 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2940 if (intf_f.fail())
2941 log_cmd_error("Can't open file `%s' for writing: %s\n",
2942 worker.intf_filename.c_str(), strerror(errno));
2943
2944 worker.intf_f = &intf_f;
2945 }
2946 worker.impl_f = f;
2947
2948 worker.prepare_design(design);
2949 worker.dump_design(design);
2950 }
2951 } CxxrtlBackend;
2952
2953 PRIVATE_NAMESPACE_END