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cxxrtl: fix format of hdlnames.
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/log.h"
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 // [[CITE]]
31 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
32 // Information Processing Letters, Vol. 47, pp 319-323, 1993
33 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
34
35 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
36 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
37 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
38 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
39 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
40 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
41 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
42 template<class T>
43 struct Scheduler {
44 struct Vertex {
45 T *data;
46 Vertex *prev, *next;
47 pool<Vertex*, hash_ptr_ops> preds, succs;
48
49 Vertex() : data(NULL), prev(this), next(this) {}
50 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
51
52 bool empty() const
53 {
54 log_assert(data == NULL);
55 if (next == this) {
56 log_assert(prev == next);
57 return true;
58 }
59 return false;
60 }
61
62 void link(Vertex *list)
63 {
64 log_assert(prev == NULL && next == NULL);
65 next = list;
66 prev = list->prev;
67 list->prev->next = this;
68 list->prev = this;
69 }
70
71 void unlink()
72 {
73 log_assert(prev->next == this && next->prev == this);
74 prev->next = next;
75 next->prev = prev;
76 next = prev = NULL;
77 }
78
79 int delta() const
80 {
81 return succs.size() - preds.size();
82 }
83 };
84
85 std::vector<Vertex*> vertices;
86 Vertex *sources = new Vertex;
87 Vertex *sinks = new Vertex;
88 dict<int, Vertex*> bins;
89
90 ~Scheduler()
91 {
92 delete sources;
93 delete sinks;
94 for (auto bin : bins)
95 delete bin.second;
96 for (auto vertex : vertices)
97 delete vertex;
98 }
99
100 Vertex *add(T *data)
101 {
102 Vertex *vertex = new Vertex(data);
103 vertices.push_back(vertex);
104 return vertex;
105 }
106
107 void relink(Vertex *vertex)
108 {
109 if (vertex->succs.empty())
110 vertex->link(sinks);
111 else if (vertex->preds.empty())
112 vertex->link(sources);
113 else {
114 int delta = vertex->delta();
115 if (!bins.count(delta))
116 bins[delta] = new Vertex;
117 vertex->link(bins[delta]);
118 }
119 }
120
121 Vertex *remove(Vertex *vertex)
122 {
123 vertex->unlink();
124 for (auto pred : vertex->preds) {
125 if (pred == vertex)
126 continue;
127 log_assert(pred->succs[vertex]);
128 pred->unlink();
129 pred->succs.erase(vertex);
130 relink(pred);
131 }
132 for (auto succ : vertex->succs) {
133 if (succ == vertex)
134 continue;
135 log_assert(succ->preds[vertex]);
136 succ->unlink();
137 succ->preds.erase(vertex);
138 relink(succ);
139 }
140 vertex->preds.clear();
141 vertex->succs.clear();
142 return vertex;
143 }
144
145 std::vector<Vertex*> schedule()
146 {
147 std::vector<Vertex*> s1, s2r;
148 for (auto vertex : vertices)
149 relink(vertex);
150 bool bins_empty = false;
151 while (!(sinks->empty() && sources->empty() && bins_empty)) {
152 while (!sinks->empty())
153 s2r.push_back(remove(sinks->next));
154 while (!sources->empty())
155 s1.push_back(remove(sources->next));
156 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
157 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
158 // naive implementation of find-max-key.
159 bins_empty = true;
160 bins.template sort<std::greater<int>>();
161 for (auto bin : bins) {
162 if (!bin.second->empty()) {
163 bins_empty = false;
164 s1.push_back(remove(bin.second->next));
165 break;
166 }
167 }
168 }
169 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
170 return s1;
171 }
172 };
173
174 bool is_input_wire(const RTLIL::Wire *wire)
175 {
176 return wire->port_input && !wire->port_output;
177 }
178
179 bool is_unary_cell(RTLIL::IdString type)
180 {
181 return type.in(
182 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
183 ID($pos), ID($neg));
184 }
185
186 bool is_binary_cell(RTLIL::IdString type)
187 {
188 return type.in(
189 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
190 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
191 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
192 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
193 }
194
195 bool is_elidable_cell(RTLIL::IdString type)
196 {
197 return is_unary_cell(type) || is_binary_cell(type) || type.in(
198 ID($mux), ID($concat), ID($slice));
199 }
200
201 bool is_sync_ff_cell(RTLIL::IdString type)
202 {
203 return type.in(
204 ID($dff), ID($dffe));
205 }
206
207 bool is_ff_cell(RTLIL::IdString type)
208 {
209 return is_sync_ff_cell(type) || type.in(
210 ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
211 }
212
213 bool is_internal_cell(RTLIL::IdString type)
214 {
215 return type[0] == '$' && !type.begins_with("$paramod");
216 }
217
218 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
219 {
220 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
221 log_assert(cell_module != nullptr);
222 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
223 }
224
225 enum class CxxrtlPortType {
226 UNKNOWN = 0, // or mixed comb/sync
227 COMB = 1,
228 SYNC = 2,
229 };
230
231 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
232 {
233 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
234 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
235 return CxxrtlPortType::UNKNOWN;
236 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
237 log_assert(cell_output_wire != nullptr);
238 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
239 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
240 if (is_comb && is_sync)
241 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
242 log_id(cell_module), log_signal(cell_output_wire));
243 else if (is_comb)
244 return CxxrtlPortType::COMB;
245 else if (is_sync)
246 return CxxrtlPortType::SYNC;
247 return CxxrtlPortType::UNKNOWN;
248 }
249
250 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
251 {
252 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
253 }
254
255 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
256 {
257 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
258 }
259
260 struct FlowGraph {
261 struct Node {
262 enum class Type {
263 CONNECT,
264 CELL_SYNC,
265 CELL_EVAL,
266 PROCESS
267 };
268
269 Type type;
270 RTLIL::SigSig connect = {};
271 const RTLIL::Cell *cell = NULL;
272 const RTLIL::Process *process = NULL;
273 };
274
275 std::vector<Node*> nodes;
276 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
277 dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
278
279 ~FlowGraph()
280 {
281 for (auto node : nodes)
282 delete node;
283 }
284
285 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool fully_sync, bool elidable)
286 {
287 for (auto chunk : sig.chunks())
288 if (chunk.wire) {
289 if (fully_sync)
290 wire_sync_defs[chunk.wire].insert(node);
291 else
292 wire_comb_defs[chunk.wire].insert(node);
293 }
294 // Only comb defs of an entire wire in the right order can be elided.
295 if (!fully_sync && sig.is_wire())
296 wire_def_elidable[sig.as_wire()] = elidable;
297 }
298
299 void add_uses(Node *node, const RTLIL::SigSpec &sig)
300 {
301 for (auto chunk : sig.chunks())
302 if (chunk.wire) {
303 wire_uses[chunk.wire].insert(node);
304 // Only a single use of an entire wire in the right order can be elided.
305 // (But the use can include other chunks.)
306 if (!wire_use_elidable.count(chunk.wire))
307 wire_use_elidable[chunk.wire] = true;
308 else
309 wire_use_elidable[chunk.wire] = false;
310 }
311 }
312
313 bool is_elidable(const RTLIL::Wire *wire) const
314 {
315 if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire))
316 return wire_def_elidable.at(wire) && wire_use_elidable.at(wire);
317 return false;
318 }
319
320 // Connections
321 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
322 {
323 add_defs(node, conn.first, /*fully_sync=*/false, /*elidable=*/true);
324 add_uses(node, conn.second);
325 }
326
327 Node *add_node(const RTLIL::SigSig &conn)
328 {
329 Node *node = new Node;
330 node->type = Node::Type::CONNECT;
331 node->connect = conn;
332 nodes.push_back(node);
333 add_connect_defs_uses(node, conn);
334 return node;
335 }
336
337 // Cells
338 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
339 {
340 // To understand why this node type is necessary and why it produces comb defs, consider a cell
341 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
342 // not result in a feedback arc because the output is synchronous. However, a naive implementation
343 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
344 // would not be able to immediately converge...
345 //
346 // wire<1> i_tmp;
347 // cell->p_i = i_tmp.curr;
348 // cell->eval();
349 // i_tmp.next = cell->p_o.curr;
350 //
351 // ... since the wire connecting the input and output ports would not be localizable. To solve
352 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
353 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
354 //
355 // value<1> i_tmp;
356 // i_tmp = cell->p_o.curr;
357 // cell->p_i = i_tmp;
358 // cell->eval();
359 //
360 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
361 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
362 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
363 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
364 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
365 // and the left-hand side has a comb def.
366 for (auto conn : cell->connections())
367 if (cell->output(conn.first))
368 if (is_cxxrtl_sync_port(cell, conn.first)) {
369 // See note regarding elidability below.
370 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
371 }
372 }
373
374 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
375 {
376 for (auto conn : cell->connections()) {
377 if (cell->output(conn.first)) {
378 if (is_elidable_cell(cell->type))
379 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/true);
380 else if (is_sync_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
381 add_defs(node, conn.second, /*fully_sync=*/true, /*elidable=*/false);
382 else if (is_internal_cell(cell->type))
383 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
384 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
385 // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
386 // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
387 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
388 // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
389 // the infrastructure required to elide outputs of cells with many of them.
390 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
391 }
392 }
393 if (cell->input(conn.first))
394 add_uses(node, conn.second);
395 }
396 }
397
398 Node *add_node(const RTLIL::Cell *cell)
399 {
400 log_assert(cell->known());
401
402 bool has_fully_sync_outputs = false;
403 for (auto conn : cell->connections())
404 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
405 has_fully_sync_outputs = true;
406 break;
407 }
408 if (has_fully_sync_outputs) {
409 Node *node = new Node;
410 node->type = Node::Type::CELL_SYNC;
411 node->cell = cell;
412 nodes.push_back(node);
413 add_cell_sync_defs(node, cell);
414 }
415
416 Node *node = new Node;
417 node->type = Node::Type::CELL_EVAL;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_eval_defs_uses(node, cell);
421 return node;
422 }
423
424 // Processes
425 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
426 {
427 for (auto &action : case_->actions) {
428 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
429 add_uses(node, action.second);
430 }
431 for (auto sub_switch : case_->switches) {
432 add_uses(node, sub_switch->signal);
433 for (auto sub_case : sub_switch->cases) {
434 for (auto &compare : sub_case->compare)
435 add_uses(node, compare);
436 add_case_defs_uses(node, sub_case);
437 }
438 }
439 }
440
441 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
442 {
443 add_case_defs_uses(node, &process->root_case);
444 for (auto sync : process->syncs)
445 for (auto action : sync->actions) {
446 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
447 add_defs(node, action.first, /*is_sync=*/true, /*elidable=*/false);
448 else
449 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
450 add_uses(node, action.second);
451 }
452 }
453
454 Node *add_node(const RTLIL::Process *process)
455 {
456 Node *node = new Node;
457 node->type = Node::Type::PROCESS;
458 node->process = process;
459 nodes.push_back(node);
460 add_process_defs_uses(node, process);
461 return node;
462 }
463 };
464
465 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
466 {
467 std::vector<std::string> result;
468 size_t prev = 0;
469 while (true) {
470 size_t curr = str.find_first_of(sep, prev + 1);
471 if (curr > str.size())
472 curr = str.size();
473 if (curr > prev + 1)
474 result.push_back(str.substr(prev, curr - prev));
475 if (curr == str.size())
476 break;
477 prev = curr;
478 }
479 return result;
480 }
481
482 std::string escape_cxx_string(const std::string &input)
483 {
484 std::string output = "\"";
485 for (auto c : input) {
486 if (::isprint(c)) {
487 if (c == '\\')
488 output.push_back('\\');
489 output.push_back(c);
490 } else {
491 char l = c & 0xf, h = (c >> 4) & 0xf;
492 output.append("\\x");
493 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
494 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
495 }
496 }
497 output.push_back('"');
498 if (output.find('\0') != std::string::npos) {
499 output.insert(0, "std::string {");
500 output.append(stringf(", %zu}", input.size()));
501 }
502 return output;
503 }
504
505 template<class T>
506 std::string get_hdl_name(T *object)
507 {
508 if (object->has_attribute(ID::hdlname))
509 return object->get_string_attribute(ID::hdlname);
510 else
511 return object->name.str().substr(1);
512 }
513
514 struct CxxrtlWorker {
515 bool split_intf = false;
516 std::string intf_filename;
517 std::string design_ns = "cxxrtl_design";
518 std::ostream *impl_f = nullptr;
519 std::ostream *intf_f = nullptr;
520
521 bool elide_internal = false;
522 bool elide_public = false;
523 bool localize_internal = false;
524 bool localize_public = false;
525 bool run_proc_flatten = false;
526 bool max_opt_level = false;
527
528 bool debug_info = false;
529
530 std::ostringstream f;
531 std::string indent;
532 int temporary = 0;
533
534 dict<const RTLIL::Module*, SigMap> sigmaps;
535 pool<const RTLIL::Wire*> edge_wires;
536 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
537 pool<const RTLIL::Memory*> writable_memories;
538 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
539 dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
540 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
541 pool<const RTLIL::Wire*> localized_wires;
542 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
543 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
544 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
545 dict<const RTLIL::Module*, bool> eval_converges;
546
547 void inc_indent() {
548 indent += "\t";
549 }
550 void dec_indent() {
551 indent.resize(indent.size() - 1);
552 }
553
554 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
555 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
556 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
557 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
558 // 1. All generated identifiers start with `_`.
559 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
560 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
561 // 2. An underscore is escaped with another underscore, i.e. `__`.
562 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
563 std::string mangle_name(const RTLIL::IdString &name)
564 {
565 std::string mangled;
566 bool first = true;
567 for (char c : name.str()) {
568 if (first) {
569 first = false;
570 if (c == '\\')
571 mangled += "p_";
572 else if (c == '$')
573 mangled += "i_";
574 else
575 log_assert(false);
576 } else {
577 if (isalnum(c)) {
578 mangled += c;
579 } else if (c == '_') {
580 mangled += "__";
581 } else {
582 char l = c & 0xf, h = (c >> 4) & 0xf;
583 mangled += '_';
584 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
585 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
586 mangled += '_';
587 }
588 }
589 }
590 return mangled;
591 }
592
593 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
594 {
595 // Class namespace.
596 if (is_blackbox)
597 return "bb_" + mangle_name(name);
598 return mangle_name(name);
599 }
600
601 std::string mangle_memory_name(const RTLIL::IdString &name)
602 {
603 // Class member namespace.
604 return "memory_" + mangle_name(name);
605 }
606
607 std::string mangle_cell_name(const RTLIL::IdString &name)
608 {
609 // Class member namespace.
610 return "cell_" + mangle_name(name);
611 }
612
613 std::string mangle_wire_name(const RTLIL::IdString &name)
614 {
615 // Class member namespace.
616 return mangle_name(name);
617 }
618
619 std::string mangle(const RTLIL::Module *module)
620 {
621 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
622 }
623
624 std::string mangle(const RTLIL::Memory *memory)
625 {
626 return mangle_memory_name(memory->name);
627 }
628
629 std::string mangle(const RTLIL::Cell *cell)
630 {
631 return mangle_cell_name(cell->name);
632 }
633
634 std::string mangle(const RTLIL::Wire *wire)
635 {
636 return mangle_wire_name(wire->name);
637 }
638
639 std::string mangle(RTLIL::SigBit sigbit)
640 {
641 log_assert(sigbit.wire != NULL);
642 if (sigbit.wire->width == 1)
643 return mangle(sigbit.wire);
644 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
645 }
646
647 std::vector<std::string> template_param_names(const RTLIL::Module *module)
648 {
649 if (!module->has_attribute(ID(cxxrtl_template)))
650 return {};
651
652 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
653 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
654
655 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
656 for (const auto &param_name : param_names) {
657 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
658 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
659 // in both Verilog and C++, anyway.)
660 if (!isupper(param_name[0]))
661 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
662 "which does not start with an uppercase letter.\n",
663 log_id(module), param_name.c_str());
664 }
665 return param_names;
666 }
667
668 std::string template_params(const RTLIL::Module *module, bool is_decl)
669 {
670 std::vector<std::string> param_names = template_param_names(module);
671 if (param_names.empty())
672 return "";
673
674 std::string params = "<";
675 bool first = true;
676 for (const auto &param_name : param_names) {
677 if (!first)
678 params += ", ";
679 first = false;
680 if (is_decl)
681 params += "size_t ";
682 params += param_name;
683 }
684 params += ">";
685 return params;
686 }
687
688 std::string template_args(const RTLIL::Cell *cell)
689 {
690 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
691 log_assert(cell_module != nullptr);
692 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
693 return "";
694
695 std::vector<std::string> param_names = template_param_names(cell_module);
696 if (param_names.empty())
697 return "";
698
699 std::string params = "<";
700 bool first = true;
701 for (const auto &param_name : param_names) {
702 if (!first)
703 params += ", ";
704 first = false;
705 params += "/*" + param_name + "=*/";
706 RTLIL::IdString id_param_name = '\\' + param_name;
707 if (!cell->hasParam(id_param_name))
708 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
709 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
710 RTLIL::Const param_value = cell->getParam(id_param_name);
711 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
712 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
713 "is not a positive integer.\n",
714 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
715 params += std::to_string(cell->getParam(id_param_name).as_int());
716 }
717 params += ">";
718 return params;
719 }
720
721 std::string fresh_temporary()
722 {
723 return stringf("tmp_%d", temporary++);
724 }
725
726 void dump_attrs(const RTLIL::AttrObject *object)
727 {
728 for (auto attr : object->attributes) {
729 f << indent << "// " << attr.first.str() << ": ";
730 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
731 f << attr.second.decode_string();
732 } else {
733 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
734 }
735 f << "\n";
736 }
737 }
738
739 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
740 {
741 const int CHUNK_SIZE = 32;
742 f << "{";
743 while (width > 0) {
744 int chunk_width = min(width, CHUNK_SIZE);
745 uint32_t chunk = data.extract(offset, chunk_width).as_int();
746 if (fixed_width)
747 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
748 else
749 f << stringf("%#xu", chunk);
750 if (width > CHUNK_SIZE)
751 f << ',';
752 offset += CHUNK_SIZE;
753 width -= CHUNK_SIZE;
754 }
755 f << "}";
756 }
757
758 void dump_const_init(const RTLIL::Const &data)
759 {
760 dump_const_init(data, data.size());
761 }
762
763 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
764 {
765 f << "value<" << width << ">";
766 dump_const_init(data, width, offset, fixed_width);
767 }
768
769 void dump_const(const RTLIL::Const &data)
770 {
771 dump_const(data, data.size());
772 }
773
774 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs)
775 {
776 if (chunk.wire == NULL) {
777 dump_const(chunk.data, chunk.width, chunk.offset);
778 return false;
779 } else {
780 if (!is_lhs && elided_wires.count(chunk.wire)) {
781 const FlowGraph::Node &node = elided_wires[chunk.wire];
782 switch (node.type) {
783 case FlowGraph::Node::Type::CONNECT:
784 dump_connect_elided(node.connect);
785 break;
786 case FlowGraph::Node::Type::CELL_EVAL:
787 log_assert(is_elidable_cell(node.cell->type));
788 dump_cell_elided(node.cell);
789 break;
790 default:
791 log_assert(false);
792 }
793 } else if (localized_wires[chunk.wire] || is_input_wire(chunk.wire)) {
794 f << mangle(chunk.wire);
795 } else {
796 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
797 }
798 if (chunk.width == chunk.wire->width && chunk.offset == 0)
799 return false;
800 else if (chunk.width == 1)
801 f << ".slice<" << chunk.offset << ">()";
802 else
803 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
804 return true;
805 }
806 }
807
808 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs)
809 {
810 if (sig.empty()) {
811 f << "value<0>()";
812 return false;
813 } else if (sig.is_chunk()) {
814 return dump_sigchunk(sig.as_chunk(), is_lhs);
815 } else {
816 dump_sigchunk(*sig.chunks().rbegin(), is_lhs);
817 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
818 f << ".concat(";
819 dump_sigchunk(*it, is_lhs);
820 f << ")";
821 }
822 return true;
823 }
824 }
825
826 void dump_sigspec_lhs(const RTLIL::SigSpec &sig)
827 {
828 dump_sigspec(sig, /*is_lhs=*/true);
829 }
830
831 void dump_sigspec_rhs(const RTLIL::SigSpec &sig)
832 {
833 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
834 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
835 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
836 // type conversion, but only if the expression needs it.
837 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false);
838 if (is_complex)
839 f << ".val()";
840 }
841
842 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
843 {
844 for (auto chunk : sig.chunks()) {
845 if (!chunk.wire || !elided_wires.count(chunk.wire))
846 continue;
847
848 const FlowGraph::Node &node = elided_wires[chunk.wire];
849 switch (node.type) {
850 case FlowGraph::Node::Type::CONNECT:
851 collect_connect(node.connect, cells);
852 break;
853 case FlowGraph::Node::Type::CELL_EVAL:
854 collect_cell_eval(node.cell, cells);
855 break;
856 default:
857 log_assert(false);
858 }
859 }
860 }
861
862 void dump_connect_elided(const RTLIL::SigSig &conn)
863 {
864 dump_sigspec_rhs(conn.second);
865 }
866
867 bool is_connect_elided(const RTLIL::SigSig &conn)
868 {
869 return conn.first.is_wire() && elided_wires.count(conn.first.as_wire());
870 }
871
872 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
873 {
874 if (!is_connect_elided(conn))
875 return;
876
877 collect_sigspec_rhs(conn.second, cells);
878 }
879
880 void dump_connect(const RTLIL::SigSig &conn)
881 {
882 if (is_connect_elided(conn))
883 return;
884
885 f << indent << "// connection\n";
886 f << indent;
887 dump_sigspec_lhs(conn.first);
888 f << " = ";
889 dump_connect_elided(conn);
890 f << ";\n";
891 }
892
893 void dump_cell_sync(const RTLIL::Cell *cell)
894 {
895 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
896 f << indent << "// cell " << cell->name.str() << " syncs\n";
897 for (auto conn : cell->connections())
898 if (cell->output(conn.first))
899 if (is_cxxrtl_sync_port(cell, conn.first)) {
900 f << indent;
901 dump_sigspec_lhs(conn.second);
902 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
903 }
904 }
905
906 void dump_cell_elided(const RTLIL::Cell *cell)
907 {
908 // Unary cells
909 if (is_unary_cell(cell->type)) {
910 f << cell->type.substr(1) << '_' <<
911 (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
912 "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
913 dump_sigspec_rhs(cell->getPort(ID::A));
914 f << ")";
915 // Binary cells
916 } else if (is_binary_cell(cell->type)) {
917 f << cell->type.substr(1) << '_' <<
918 (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
919 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u') <<
920 "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
921 dump_sigspec_rhs(cell->getPort(ID::A));
922 f << ", ";
923 dump_sigspec_rhs(cell->getPort(ID::B));
924 f << ")";
925 // Muxes
926 } else if (cell->type == ID($mux)) {
927 f << "(";
928 dump_sigspec_rhs(cell->getPort(ID::S));
929 f << " ? ";
930 dump_sigspec_rhs(cell->getPort(ID::B));
931 f << " : ";
932 dump_sigspec_rhs(cell->getPort(ID::A));
933 f << ")";
934 // Concats
935 } else if (cell->type == ID($concat)) {
936 dump_sigspec_rhs(cell->getPort(ID::B));
937 f << ".concat(";
938 dump_sigspec_rhs(cell->getPort(ID::A));
939 f << ").val()";
940 // Slices
941 } else if (cell->type == ID($slice)) {
942 dump_sigspec_rhs(cell->getPort(ID::A));
943 f << ".slice<";
944 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
945 f << ",";
946 f << cell->getParam(ID::OFFSET).as_int();
947 f << ">().val()";
948 } else {
949 log_assert(false);
950 }
951 }
952
953 bool is_cell_elided(const RTLIL::Cell *cell)
954 {
955 return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
956 elided_wires.count(cell->getPort(ID::Y).as_wire());
957 }
958
959 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
960 {
961 if (!is_cell_elided(cell))
962 return;
963
964 cells.push_back(cell->name);
965 for (auto port : cell->connections())
966 if (port.first != ID::Y)
967 collect_sigspec_rhs(port.second, cells);
968 }
969
970 void dump_cell_eval(const RTLIL::Cell *cell)
971 {
972 if (is_cell_elided(cell))
973 return;
974 if (cell->type == ID($meminit))
975 return; // Handled elsewhere.
976
977 std::vector<RTLIL::IdString> elided_cells;
978 if (is_elidable_cell(cell->type)) {
979 for (auto port : cell->connections())
980 if (port.first != ID::Y)
981 collect_sigspec_rhs(port.second, elided_cells);
982 }
983 if (elided_cells.empty()) {
984 dump_attrs(cell);
985 f << indent << "// cell " << cell->name.str() << "\n";
986 } else {
987 f << indent << "// cells";
988 for (auto elided_cell : elided_cells)
989 f << " " << elided_cell.str();
990 f << "\n";
991 }
992
993 // Elidable cells
994 if (is_elidable_cell(cell->type)) {
995 f << indent;
996 dump_sigspec_lhs(cell->getPort(ID::Y));
997 f << " = ";
998 dump_cell_elided(cell);
999 f << ";\n";
1000 // Parallel (one-hot) muxes
1001 } else if (cell->type == ID($pmux)) {
1002 int width = cell->getParam(ID::WIDTH).as_int();
1003 int s_width = cell->getParam(ID::S_WIDTH).as_int();
1004 bool first = true;
1005 for (int part = 0; part < s_width; part++) {
1006 f << (first ? indent : " else ");
1007 first = false;
1008 f << "if (";
1009 dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
1010 f << ") {\n";
1011 inc_indent();
1012 f << indent;
1013 dump_sigspec_lhs(cell->getPort(ID::Y));
1014 f << " = ";
1015 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
1016 f << ";\n";
1017 dec_indent();
1018 f << indent << "}";
1019 }
1020 f << " else {\n";
1021 inc_indent();
1022 f << indent;
1023 dump_sigspec_lhs(cell->getPort(ID::Y));
1024 f << " = ";
1025 dump_sigspec_rhs(cell->getPort(ID::A));
1026 f << ";\n";
1027 dec_indent();
1028 f << indent << "}\n";
1029 // Flip-flops
1030 } else if (is_ff_cell(cell->type)) {
1031 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1032 // Edge-sensitive logic
1033 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1034 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1035 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1036 << mangle(clk_bit) << ") {\n";
1037 inc_indent();
1038 if (cell->type == ID($dffe)) {
1039 f << indent << "if (";
1040 dump_sigspec_rhs(cell->getPort(ID::EN));
1041 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1042 inc_indent();
1043 }
1044 f << indent;
1045 dump_sigspec_lhs(cell->getPort(ID::Q));
1046 f << " = ";
1047 dump_sigspec_rhs(cell->getPort(ID::D));
1048 f << ";\n";
1049 if (cell->type == ID($dffe)) {
1050 dec_indent();
1051 f << indent << "}\n";
1052 }
1053 dec_indent();
1054 f << indent << "}\n";
1055 } else if (cell->hasPort(ID::EN)) {
1056 // Level-sensitive logic
1057 f << indent << "if (";
1058 dump_sigspec_rhs(cell->getPort(ID::EN));
1059 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1060 inc_indent();
1061 f << indent;
1062 dump_sigspec_lhs(cell->getPort(ID::Q));
1063 f << " = ";
1064 dump_sigspec_rhs(cell->getPort(ID::D));
1065 f << ";\n";
1066 dec_indent();
1067 f << indent << "}\n";
1068 }
1069 if (cell->hasPort(ID::ARST)) {
1070 // Asynchronous reset (entire coarse cell at once)
1071 f << indent << "if (";
1072 dump_sigspec_rhs(cell->getPort(ID::ARST));
1073 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1074 inc_indent();
1075 f << indent;
1076 dump_sigspec_lhs(cell->getPort(ID::Q));
1077 f << " = ";
1078 dump_const(cell->getParam(ID::ARST_VALUE));
1079 f << ";\n";
1080 dec_indent();
1081 f << indent << "}\n";
1082 }
1083 if (cell->hasPort(ID::SET)) {
1084 // Asynchronous set (for individual bits)
1085 f << indent;
1086 dump_sigspec_lhs(cell->getPort(ID::Q));
1087 f << " = ";
1088 dump_sigspec_lhs(cell->getPort(ID::Q));
1089 f << ".update(";
1090 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1091 f << ", ";
1092 dump_sigspec_rhs(cell->getPort(ID::SET));
1093 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1094 }
1095 if (cell->hasPort(ID::CLR)) {
1096 // Asynchronous clear (for individual bits; priority over set)
1097 f << indent;
1098 dump_sigspec_lhs(cell->getPort(ID::Q));
1099 f << " = ";
1100 dump_sigspec_lhs(cell->getPort(ID::Q));
1101 f << ".update(";
1102 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1103 f << ", ";
1104 dump_sigspec_rhs(cell->getPort(ID::CLR));
1105 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1106 }
1107 // Memory ports
1108 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1109 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1110 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1111 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1112 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1113 << mangle(clk_bit) << ") {\n";
1114 inc_indent();
1115 }
1116 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1117 std::string valid_index_temp = fresh_temporary();
1118 f << indent << "auto " << valid_index_temp << " = memory_index(";
1119 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1120 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1121 if (cell->type == ID($memrd)) {
1122 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1123 if (has_enable) {
1124 f << indent << "if (";
1125 dump_sigspec_rhs(cell->getPort(ID::EN));
1126 f << ") {\n";
1127 inc_indent();
1128 }
1129 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1130 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1131 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -NDEBUG not
1132 // just for release builds, but also to make sure the simulator (which is presumably embedded in some
1133 // larger program) will never crash the code that calls into it.
1134 //
1135 // If assertions are disabled, out of bounds reads are defined to return zero.
1136 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1137 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1138 inc_indent();
1139 if (writable_memories[memory]) {
1140 std::string addr_temp = fresh_temporary();
1141 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1142 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1143 f << ";\n";
1144 std::string lhs_temp = fresh_temporary();
1145 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1146 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1147 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1148 std::sort(memwr_cells.begin(), memwr_cells.end(),
1149 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1150 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1151 });
1152 for (auto memwr_cell : memwr_cells) {
1153 f << indent << "if (" << addr_temp << " == ";
1154 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1155 f << ") {\n";
1156 inc_indent();
1157 f << indent << lhs_temp << " = " << lhs_temp;
1158 f << ".update(";
1159 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1160 f << ", ";
1161 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1162 f << ");\n";
1163 dec_indent();
1164 f << indent << "}\n";
1165 }
1166 f << indent;
1167 dump_sigspec_lhs(cell->getPort(ID::DATA));
1168 f << " = " << lhs_temp << ";\n";
1169 } else {
1170 f << indent;
1171 dump_sigspec_lhs(cell->getPort(ID::DATA));
1172 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1173 }
1174 dec_indent();
1175 f << indent << "} else {\n";
1176 inc_indent();
1177 f << indent;
1178 dump_sigspec_lhs(cell->getPort(ID::DATA));
1179 f << " = value<" << memory->width << "> {};\n";
1180 dec_indent();
1181 f << indent << "}\n";
1182 if (has_enable) {
1183 dec_indent();
1184 f << indent << "}\n";
1185 }
1186 } else /*if (cell->type == ID($memwr))*/ {
1187 log_assert(writable_memories[memory]);
1188 // See above for rationale of having both the assert and the condition.
1189 //
1190 // If assertions are disabled, out of bounds writes are defined to do nothing.
1191 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1192 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1193 inc_indent();
1194 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1195 dump_sigspec_rhs(cell->getPort(ID::DATA));
1196 f << ", ";
1197 dump_sigspec_rhs(cell->getPort(ID::EN));
1198 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1199 dec_indent();
1200 f << indent << "}\n";
1201 }
1202 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1203 dec_indent();
1204 f << indent << "}\n";
1205 }
1206 // Internal cells
1207 } else if (is_internal_cell(cell->type)) {
1208 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1209 // User cells
1210 } else {
1211 log_assert(cell->known());
1212 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1213 for (auto conn : cell->connections())
1214 if (cell->input(conn.first) && !cell->output(conn.first)) {
1215 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = ";
1216 dump_sigspec_rhs(conn.second);
1217 f << ";\n";
1218 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1219 // Until we have proper clock tree detection, this really awful hack that opportunistically
1220 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1221 // be if only one clock edge was simulated by replacing:
1222 // top.p_clk = value<1>{0u}; top.step();
1223 // top.p_clk = value<1>{1u}; top.step();
1224 // with:
1225 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1226 // Don't rely on this; it will be removed without warning.
1227 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1228 if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) {
1229 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1230 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1231 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1232 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1233 }
1234 }
1235 }
1236 } else if (cell->input(conn.first)) {
1237 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = ";
1238 dump_sigspec_rhs(conn.second);
1239 f << ";\n";
1240 }
1241 auto assign_from_outputs = [&](bool cell_converged) {
1242 for (auto conn : cell->connections()) {
1243 if (cell->output(conn.first)) {
1244 if (conn.second.empty())
1245 continue; // ignore disconnected ports
1246 if (is_cxxrtl_sync_port(cell, conn.first))
1247 continue; // fully sync ports are handled in CELL_SYNC nodes
1248 f << indent;
1249 dump_sigspec_lhs(conn.second);
1250 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1251 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1252 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1253 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1254 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1255 // and consider the fate of the localized wires that used to be output ports.)
1256 //
1257 // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell
1258 // (which may be late bound) will converge immediately. Because of this, the choice between using .curr
1259 // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime.
1260 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1261 f << ".next;\n";
1262 else
1263 f << ".curr;\n";
1264 }
1265 }
1266 };
1267 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1268 inc_indent();
1269 assign_from_outputs(/*cell_converged=*/true);
1270 dec_indent();
1271 f << indent << "} else {\n";
1272 inc_indent();
1273 f << indent << "converged = false;\n";
1274 assign_from_outputs(/*cell_converged=*/false);
1275 dec_indent();
1276 f << indent << "}\n";
1277 }
1278 }
1279
1280 void dump_assign(const RTLIL::SigSig &sigsig)
1281 {
1282 f << indent;
1283 dump_sigspec_lhs(sigsig.first);
1284 f << " = ";
1285 dump_sigspec_rhs(sigsig.second);
1286 f << ";\n";
1287 }
1288
1289 void dump_case_rule(const RTLIL::CaseRule *rule)
1290 {
1291 for (auto action : rule->actions)
1292 dump_assign(action);
1293 for (auto switch_ : rule->switches)
1294 dump_switch_rule(switch_);
1295 }
1296
1297 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1298 {
1299 // The switch attributes are printed before the switch condition is captured.
1300 dump_attrs(rule);
1301 std::string signal_temp = fresh_temporary();
1302 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1303 dump_sigspec(rule->signal, /*is_lhs=*/false);
1304 f << ";\n";
1305
1306 bool first = true;
1307 for (auto case_ : rule->cases) {
1308 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1309 dump_attrs(rule);
1310 f << indent;
1311 if (!first)
1312 f << "} else ";
1313 first = false;
1314 if (!case_->compare.empty()) {
1315 f << "if (";
1316 bool first = true;
1317 for (auto &compare : case_->compare) {
1318 if (!first)
1319 f << " || ";
1320 first = false;
1321 if (compare.is_fully_def()) {
1322 f << signal_temp << " == ";
1323 dump_sigspec(compare, /*is_lhs=*/false);
1324 } else if (compare.is_fully_const()) {
1325 RTLIL::Const compare_mask, compare_value;
1326 for (auto bit : compare.as_const()) {
1327 switch (bit) {
1328 case RTLIL::S0:
1329 case RTLIL::S1:
1330 compare_mask.bits.push_back(RTLIL::S1);
1331 compare_value.bits.push_back(bit);
1332 break;
1333
1334 case RTLIL::Sx:
1335 case RTLIL::Sz:
1336 case RTLIL::Sa:
1337 compare_mask.bits.push_back(RTLIL::S0);
1338 compare_value.bits.push_back(RTLIL::S0);
1339 break;
1340
1341 default:
1342 log_assert(false);
1343 }
1344 }
1345 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1346 dump_const(compare_mask);
1347 f << ") == ";
1348 dump_const(compare_value);
1349 } else {
1350 log_assert(false);
1351 }
1352 }
1353 f << ") ";
1354 }
1355 f << "{\n";
1356 inc_indent();
1357 dump_case_rule(case_);
1358 dec_indent();
1359 }
1360 f << indent << "}\n";
1361 }
1362
1363 void dump_process(const RTLIL::Process *proc)
1364 {
1365 dump_attrs(proc);
1366 f << indent << "// process " << proc->name.str() << "\n";
1367 // The case attributes (for root case) are always empty.
1368 log_assert(proc->root_case.attributes.empty());
1369 dump_case_rule(&proc->root_case);
1370 for (auto sync : proc->syncs) {
1371 RTLIL::SigBit sync_bit;
1372 if (!sync->signal.empty()) {
1373 sync_bit = sync->signal[0];
1374 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1375 }
1376
1377 pool<std::string> events;
1378 switch (sync->type) {
1379 case RTLIL::STp:
1380 log_assert(sync_bit.wire != nullptr);
1381 events.insert("posedge_" + mangle(sync_bit));
1382 break;
1383 case RTLIL::STn:
1384 log_assert(sync_bit.wire != nullptr);
1385 events.insert("negedge_" + mangle(sync_bit));
1386 break;
1387 case RTLIL::STe:
1388 log_assert(sync_bit.wire != nullptr);
1389 events.insert("posedge_" + mangle(sync_bit));
1390 events.insert("negedge_" + mangle(sync_bit));
1391 break;
1392
1393 case RTLIL::STa:
1394 events.insert("true");
1395 break;
1396
1397 case RTLIL::ST0:
1398 case RTLIL::ST1:
1399 case RTLIL::STg:
1400 case RTLIL::STi:
1401 log_assert(false);
1402 }
1403 if (!events.empty()) {
1404 f << indent << "if (";
1405 bool first = true;
1406 for (auto &event : events) {
1407 if (!first)
1408 f << " || ";
1409 first = false;
1410 f << event;
1411 }
1412 f << ") {\n";
1413 inc_indent();
1414 for (auto action : sync->actions)
1415 dump_assign(action);
1416 dec_indent();
1417 f << indent << "}\n";
1418 }
1419 }
1420 }
1421
1422 void dump_wire(const RTLIL::Wire *wire, bool is_local_context)
1423 {
1424 if (elided_wires.count(wire))
1425 return;
1426 if (localized_wires.count(wire) != is_local_context)
1427 return;
1428
1429 if (is_local_context) {
1430 dump_attrs(wire);
1431 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1432 } else {
1433 std::string width;
1434 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1435 width = wire->get_string_attribute(ID(cxxrtl_width));
1436 } else {
1437 width = std::to_string(wire->width);
1438 }
1439
1440 dump_attrs(wire);
1441 f << indent << (is_input_wire(wire) ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1442 if (wire->has_attribute(ID::init)) {
1443 f << " ";
1444 dump_const_init(wire->attributes.at(ID::init));
1445 }
1446 f << ";\n";
1447 if (edge_wires[wire]) {
1448 if (is_input_wire(wire)) {
1449 f << indent << "value<" << width << "> prev_" << mangle(wire);
1450 if (wire->has_attribute(ID::init)) {
1451 f << " ";
1452 dump_const_init(wire->attributes.at(ID::init));
1453 }
1454 f << ";\n";
1455 }
1456 for (auto edge_type : edge_types) {
1457 if (edge_type.first.wire == wire) {
1458 std::string prev, next;
1459 if (is_input_wire(wire)) {
1460 prev = "prev_" + mangle(edge_type.first.wire);
1461 next = mangle(edge_type.first.wire);
1462 } else {
1463 prev = mangle(edge_type.first.wire) + ".curr";
1464 next = mangle(edge_type.first.wire) + ".next";
1465 }
1466 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1467 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1468 if (edge_type.second != RTLIL::STn) {
1469 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1470 inc_indent();
1471 f << indent << "return !" << prev << " && " << next << ";\n";
1472 dec_indent();
1473 f << indent << "}\n";
1474 }
1475 if (edge_type.second != RTLIL::STp) {
1476 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1477 inc_indent();
1478 f << indent << "return " << prev << " && !" << next << ";\n";
1479 dec_indent();
1480 f << indent << "}\n";
1481 }
1482 }
1483 }
1484 }
1485 }
1486 }
1487
1488 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1489 {
1490 vector<const RTLIL::Cell*> init_cells;
1491 for (auto cell : module->cells())
1492 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1493 init_cells.push_back(cell);
1494
1495 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1496 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1497 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1498 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1499 });
1500
1501 dump_attrs(memory);
1502 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1503 << " { " << memory->size << "u";
1504 if (init_cells.empty()) {
1505 f << " };\n";
1506 } else {
1507 f << ",\n";
1508 inc_indent();
1509 for (auto cell : init_cells) {
1510 dump_attrs(cell);
1511 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1512 size_t width = cell->getParam(ID::WIDTH).as_int();
1513 size_t words = cell->getParam(ID::WORDS).as_int();
1514 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1515 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1516 inc_indent();
1517 for (size_t n = 0; n < words; n++) {
1518 if (n % 4 == 0)
1519 f << "\n" << indent;
1520 else
1521 f << " ";
1522 dump_const(data, width, n * width, /*fixed_width=*/true);
1523 f << ",";
1524 }
1525 dec_indent();
1526 f << "\n" << indent << "}},\n";
1527 }
1528 dec_indent();
1529 f << indent << "};\n";
1530 }
1531 }
1532
1533 void dump_eval_method(RTLIL::Module *module)
1534 {
1535 inc_indent();
1536 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1537 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1538 for (auto wire : module->wires()) {
1539 if (edge_wires[wire]) {
1540 for (auto edge_type : edge_types) {
1541 if (edge_type.first.wire == wire) {
1542 if (edge_type.second != RTLIL::STn) {
1543 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1544 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1545 }
1546 if (edge_type.second != RTLIL::STp) {
1547 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1548 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1549 }
1550 }
1551 }
1552 }
1553 }
1554 for (auto wire : module->wires())
1555 dump_wire(wire, /*is_local_context=*/true);
1556 for (auto node : schedule[module]) {
1557 switch (node.type) {
1558 case FlowGraph::Node::Type::CONNECT:
1559 dump_connect(node.connect);
1560 break;
1561 case FlowGraph::Node::Type::CELL_SYNC:
1562 dump_cell_sync(node.cell);
1563 break;
1564 case FlowGraph::Node::Type::CELL_EVAL:
1565 dump_cell_eval(node.cell);
1566 break;
1567 case FlowGraph::Node::Type::PROCESS:
1568 dump_process(node.process);
1569 break;
1570 }
1571 }
1572 }
1573 f << indent << "return converged;\n";
1574 dec_indent();
1575 }
1576
1577 void dump_commit_method(RTLIL::Module *module)
1578 {
1579 inc_indent();
1580 f << indent << "bool changed = false;\n";
1581 for (auto wire : module->wires()) {
1582 if (elided_wires.count(wire) || localized_wires.count(wire))
1583 continue;
1584 if (is_input_wire(wire)) {
1585 if (edge_wires[wire])
1586 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1587 continue;
1588 }
1589 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1590 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1591 }
1592 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1593 for (auto memory : module->memories) {
1594 if (!writable_memories[memory.second])
1595 continue;
1596 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1597 }
1598 for (auto cell : module->cells()) {
1599 if (is_internal_cell(cell->type))
1600 continue;
1601 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1602 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1603 }
1604 }
1605 f << indent << "return changed;\n";
1606 dec_indent();
1607 }
1608
1609 void dump_debug_info_method(RTLIL::Module *module)
1610 {
1611 size_t count_const_wires = 0;
1612 size_t count_alias_wires = 0;
1613 size_t count_member_wires = 0;
1614 size_t count_skipped_wires = 0;
1615 inc_indent();
1616 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1617 for (auto wire : module->wires()) {
1618 if (wire->name[0] != '\\')
1619 continue;
1620 if (debug_const_wires.count(wire)) {
1621 // Wire tied to a constant
1622 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1623 dump_const(debug_const_wires[wire]);
1624 f << ";\n";
1625 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1626 f << ", debug_item(const_" << mangle(wire) << "));\n";
1627 count_const_wires++;
1628 } else if (debug_alias_wires.count(wire)) {
1629 // Alias of a member wire
1630 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1631 f << ", debug_item(" << mangle(debug_alias_wires[wire]) << "));\n";
1632 count_alias_wires++;
1633 } else if (!localized_wires.count(wire)) {
1634 // Member wire
1635 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1636 f << ", debug_item(" << mangle(wire) << "));\n";
1637 count_member_wires++;
1638 } else {
1639 count_skipped_wires++;
1640 }
1641 }
1642 for (auto &memory_it : module->memories) {
1643 if (memory_it.first[0] != '\\')
1644 continue;
1645 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1646 f << ", debug_item(" << mangle(memory_it.second) << "));\n";
1647 }
1648 for (auto cell : module->cells()) {
1649 if (is_internal_cell(cell->type))
1650 continue;
1651 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1652 f << indent << mangle(cell) << access << "debug_info(items, ";
1653 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1654 }
1655 dec_indent();
1656
1657 log_debug("Debug information statistics for module %s:\n", log_id(module));
1658 log_debug(" Const wires: %zu\n", count_const_wires);
1659 log_debug(" Alias wires: %zu\n", count_alias_wires);
1660 log_debug(" Member wires: %zu\n", count_member_wires);
1661 log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
1662 }
1663
1664 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1665 {
1666 if (metadata_map.empty()) {
1667 f << "metadata_map()";
1668 return;
1669 }
1670 f << "metadata_map({\n";
1671 inc_indent();
1672 for (auto metadata_item : metadata_map) {
1673 if (!metadata_item.first.begins_with("\\"))
1674 continue;
1675 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1676 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1677 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1678 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1679 f << escape_cxx_string(metadata_item.second.decode_string());
1680 } else {
1681 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1682 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1683 f << "u";
1684 }
1685 f << " },\n";
1686 }
1687 dec_indent();
1688 f << indent << "})";
1689 }
1690
1691 void dump_module_intf(RTLIL::Module *module)
1692 {
1693 dump_attrs(module);
1694 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1695 if (module->has_attribute(ID(cxxrtl_template)))
1696 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1697 f << indent << "struct " << mangle(module) << " : public module {\n";
1698 inc_indent();
1699 for (auto wire : module->wires()) {
1700 if (wire->port_id != 0)
1701 dump_wire(wire, /*is_local_context=*/false);
1702 }
1703 f << "\n";
1704 f << indent << "bool eval() override {\n";
1705 dump_eval_method(module);
1706 f << indent << "}\n";
1707 f << "\n";
1708 f << indent << "bool commit() override {\n";
1709 dump_commit_method(module);
1710 f << indent << "}\n";
1711 f << "\n";
1712 if (debug_info) {
1713 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1714 dump_debug_info_method(module);
1715 f << indent << "}\n";
1716 f << "\n";
1717 }
1718 f << indent << "static std::unique_ptr<" << mangle(module);
1719 f << template_params(module, /*is_decl=*/false) << "> ";
1720 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1721 dec_indent();
1722 f << indent << "}; // struct " << mangle(module) << "\n";
1723 f << "\n";
1724 if (blackbox_specializations.count(module)) {
1725 // If templated black boxes are used, the constructor of any module which includes the black box cell
1726 // (which calls the declared but not defined in the generated code `create` function) may only be used
1727 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1728 // a forward-declared explicit specialization.
1729 //
1730 // Option (b) makes it possible to have the generated code and the black box implementation in different
1731 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1732 // a specialization for every combination of parameters the generated code may use; but since the main
1733 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1734 // be very few such combinations anyway.
1735 for (auto specialization : blackbox_specializations[module]) {
1736 f << indent << "template<>\n";
1737 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1738 f << mangle(module) << specialization << "::";
1739 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1740 f << "\n";
1741 }
1742 }
1743 } else {
1744 f << indent << "struct " << mangle(module) << " : public module {\n";
1745 inc_indent();
1746 for (auto wire : module->wires())
1747 dump_wire(wire, /*is_local_context=*/false);
1748 f << "\n";
1749 bool has_memories = false;
1750 for (auto memory : module->memories) {
1751 dump_memory(module, memory.second);
1752 has_memories = true;
1753 }
1754 if (has_memories)
1755 f << "\n";
1756 bool has_cells = false;
1757 for (auto cell : module->cells()) {
1758 if (is_internal_cell(cell->type))
1759 continue;
1760 dump_attrs(cell);
1761 RTLIL::Module *cell_module = module->design->module(cell->type);
1762 log_assert(cell_module != nullptr);
1763 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1764 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1765 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1766 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1767 dump_metadata_map(cell->parameters);
1768 f << ", ";
1769 dump_metadata_map(cell->attributes);
1770 f << ");\n";
1771 } else {
1772 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1773 }
1774 has_cells = true;
1775 }
1776 if (has_cells)
1777 f << "\n";
1778 f << indent << "bool eval() override;\n";
1779 f << indent << "bool commit() override;\n";
1780 if (debug_info)
1781 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
1782 dec_indent();
1783 f << indent << "}; // struct " << mangle(module) << "\n";
1784 f << "\n";
1785 }
1786 }
1787
1788 void dump_module_impl(RTLIL::Module *module)
1789 {
1790 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1791 return;
1792 f << indent << "bool " << mangle(module) << "::eval() {\n";
1793 dump_eval_method(module);
1794 f << indent << "}\n";
1795 f << "\n";
1796 f << indent << "bool " << mangle(module) << "::commit() {\n";
1797 dump_commit_method(module);
1798 f << indent << "}\n";
1799 f << "\n";
1800 if (debug_info) {
1801 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
1802 dump_debug_info_method(module);
1803 f << indent << "}\n";
1804 f << "\n";
1805 }
1806 }
1807
1808 void dump_design(RTLIL::Design *design)
1809 {
1810 RTLIL::Module *top_module = nullptr;
1811 std::vector<RTLIL::Module*> modules;
1812 TopoSort<RTLIL::Module*> topo_design;
1813 for (auto module : design->modules()) {
1814 if (!design->selected_module(module))
1815 continue;
1816 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1817 modules.push_back(module); // cxxrtl blackboxes first
1818 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
1819 continue;
1820 if (module->get_bool_attribute(ID::top))
1821 top_module = module;
1822
1823 topo_design.node(module);
1824 for (auto cell : module->cells()) {
1825 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
1826 continue;
1827 RTLIL::Module *cell_module = design->module(cell->type);
1828 log_assert(cell_module != nullptr);
1829 topo_design.edge(cell_module, module);
1830 }
1831 }
1832 log_assert(topo_design.sort());
1833 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
1834
1835 if (split_intf) {
1836 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
1837 std::string include_guard = design_ns + "_header";
1838 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
1839
1840 f << "#ifndef " << include_guard << "\n";
1841 f << "#define " << include_guard << "\n";
1842 f << "\n";
1843 if (top_module != nullptr && debug_info) {
1844 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
1845 f << "\n";
1846 f << "#ifdef __cplusplus\n";
1847 f << "extern \"C\" {\n";
1848 f << "#endif\n";
1849 f << "\n";
1850 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
1851 f << "\n";
1852 f << "#ifdef __cplusplus\n";
1853 f << "}\n";
1854 f << "#endif\n";
1855 f << "\n";
1856 } else {
1857 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
1858 f << "\n";
1859 }
1860 f << "#ifdef __cplusplus\n";
1861 f << "\n";
1862 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1863 f << "\n";
1864 f << "using namespace cxxrtl;\n";
1865 f << "\n";
1866 f << "namespace " << design_ns << " {\n";
1867 f << "\n";
1868 for (auto module : modules)
1869 dump_module_intf(module);
1870 f << "} // namespace " << design_ns << "\n";
1871 f << "\n";
1872 f << "#endif // __cplusplus\n";
1873 f << "\n";
1874 f << "#endif\n";
1875 *intf_f << f.str(); f.str("");
1876 }
1877
1878 if (split_intf)
1879 f << "#include \"" << intf_filename << "\"\n";
1880 else
1881 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1882 f << "\n";
1883 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
1884 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1885 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
1886 f << "#endif\n";
1887 f << "\n";
1888 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1889 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
1890 f << "#endif\n";
1891 f << "\n";
1892 f << "using namespace cxxrtl_yosys;\n";
1893 f << "\n";
1894 f << "namespace " << design_ns << " {\n";
1895 f << "\n";
1896 for (auto module : modules) {
1897 if (!split_intf)
1898 dump_module_intf(module);
1899 dump_module_impl(module);
1900 }
1901 f << "} // namespace " << design_ns << "\n";
1902 f << "\n";
1903 if (top_module != nullptr && debug_info) {
1904 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
1905 inc_indent();
1906 f << indent << "return new _cxxrtl_toplevel { ";
1907 f << "std::make_unique<" << design_ns << "::" << mangle(top_module) << ">()";
1908 f << " };\n";
1909 dec_indent();
1910 f << "}\n";
1911 }
1912
1913 *impl_f << f.str(); f.str("");
1914 }
1915
1916 // Edge-type sync rules require us to emit edge detectors, which require coordination between
1917 // eval and commit phases. To do this we need to collect them upfront.
1918 //
1919 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
1920 // operate at wire bit granularity; it is possible to have code similar to:
1921 // wire [3:0] clocks;
1922 // always @(posedge clocks[0]) ...
1923 // To handle this we track edge sensitivity both for wires and wire bits.
1924 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
1925 {
1926 signal = sigmap(signal);
1927 log_assert(signal.is_wire() && signal.is_bit());
1928 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
1929
1930 RTLIL::SigBit sigbit = signal[0];
1931 if (!edge_types.count(sigbit))
1932 edge_types[sigbit] = type;
1933 else if (edge_types[sigbit] != type)
1934 edge_types[sigbit] = RTLIL::STe;
1935 edge_wires.insert(signal.as_wire());
1936 }
1937
1938 void analyze_design(RTLIL::Design *design)
1939 {
1940 bool has_feedback_arcs = false;
1941 bool has_buffered_wires = false;
1942
1943 for (auto module : design->modules()) {
1944 if (!design->selected_module(module))
1945 continue;
1946
1947 SigMap &sigmap = sigmaps[module];
1948 sigmap.set(module);
1949
1950 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1951 for (auto port : module->ports) {
1952 RTLIL::Wire *wire = module->wire(port);
1953 if (wire->has_attribute(ID(cxxrtl_edge))) {
1954 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
1955 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
1956 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
1957 log_id(module), log_signal(wire));
1958
1959 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
1960 for (int i = 0; i < GetSize(wire); i++) {
1961 RTLIL::SigSpec wire_sig = wire;
1962 switch (edges[i]) {
1963 case '-': break;
1964 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
1965 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
1966 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
1967 default:
1968 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
1969 "other than '-', 'p', 'n', or 'a'.\n",
1970 log_id(module), log_signal(wire));
1971 }
1972 }
1973 }
1974 }
1975
1976 // Black boxes converge by default, since their implementations are quite unlikely to require
1977 // internal propagation of comb signals.
1978 eval_converges[module] = true;
1979 continue;
1980 }
1981
1982 FlowGraph flow;
1983
1984 for (auto conn : module->connections())
1985 flow.add_node(conn);
1986
1987 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
1988 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
1989 pool<const RTLIL::Cell*>> memwr_per_domain;
1990 for (auto cell : module->cells()) {
1991 if (!cell->known())
1992 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
1993
1994 RTLIL::Module *cell_module = design->module(cell->type);
1995 if (cell_module &&
1996 cell_module->get_blackbox_attribute() &&
1997 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
1998 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
1999
2000 if (cell_module &&
2001 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2002 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2003 blackbox_specializations[cell_module].insert(template_args(cell));
2004
2005 FlowGraph::Node *node = flow.add_node(cell);
2006
2007 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2008 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
2009 if (cell->getPort(ID::CLK).is_wire())
2010 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2011 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2012 }
2013 // Similar for memory port cells.
2014 if (cell->type.in(ID($memrd), ID($memwr))) {
2015 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2016 if (cell->getPort(ID::CLK).is_wire())
2017 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2018 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2019 }
2020 memrw_cell_nodes[cell] = node;
2021 }
2022 // Optimize access to read-only memories.
2023 if (cell->type == ID($memwr))
2024 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2025 // Collect groups of memory write ports in the same domain.
2026 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2027 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2028 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2029 memwr_per_domain[{clk_bit, memory}].insert(cell);
2030 }
2031 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2032 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2033 if (cell->type.in(ID($mem)))
2034 log_assert(false);
2035 }
2036 for (auto cell : module->cells()) {
2037 // Collect groups of memory write ports read by every transparent read port.
2038 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2039 cell->getParam(ID::TRANSPARENT).as_bool()) {
2040 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2041 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2042 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2043 transparent_for[cell].insert(memwr_cell);
2044 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2045 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2046 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2047 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2048 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2049 }
2050 }
2051 }
2052
2053 for (auto proc : module->processes) {
2054 flow.add_node(proc.second);
2055
2056 for (auto sync : proc.second->syncs)
2057 switch (sync->type) {
2058 // Edge-type sync rules require pre-registration.
2059 case RTLIL::STp:
2060 case RTLIL::STn:
2061 case RTLIL::STe:
2062 register_edge_signal(sigmap, sync->signal, sync->type);
2063 break;
2064
2065 // Level-type sync rules require no special handling.
2066 case RTLIL::ST0:
2067 case RTLIL::ST1:
2068 case RTLIL::STa:
2069 break;
2070
2071 case RTLIL::STg:
2072 log_cmd_error("Global clock is not supported.\n");
2073
2074 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2075 // attribute regardless of input.
2076 case RTLIL::STi:
2077 log_assert(false);
2078 }
2079 }
2080
2081 for (auto wire : module->wires()) {
2082 if (!flow.is_elidable(wire)) continue;
2083 if (wire->port_id != 0) continue;
2084 if (wire->get_bool_attribute(ID::keep)) continue;
2085 if (wire->name.begins_with("$") && !elide_internal) continue;
2086 if (wire->name.begins_with("\\") && !elide_public) continue;
2087 if (edge_wires[wire]) continue;
2088 log_assert(flow.wire_comb_defs[wire].size() == 1);
2089 elided_wires[wire] = **flow.wire_comb_defs[wire].begin();
2090 }
2091
2092 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2093 for (auto wire_comb_def : flow.wire_comb_defs)
2094 for (auto node : wire_comb_def.second)
2095 node_defs[node].insert(wire_comb_def.first);
2096
2097 Scheduler<FlowGraph::Node> scheduler;
2098 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2099 for (auto node : flow.nodes)
2100 node_map[node] = scheduler.add(node);
2101 for (auto node_def : node_defs) {
2102 auto vertex = node_map[node_def.first];
2103 for (auto wire : node_def.second)
2104 for (auto succ_node : flow.wire_uses[wire]) {
2105 auto succ_vertex = node_map[succ_node];
2106 vertex->succs.insert(succ_vertex);
2107 succ_vertex->preds.insert(vertex);
2108 }
2109 }
2110
2111 auto eval_order = scheduler.schedule();
2112 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2113 pool<const RTLIL::Wire*> feedback_wires;
2114 for (auto vertex : eval_order) {
2115 auto node = vertex->data;
2116 schedule[module].push_back(*node);
2117 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2118 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2119 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2120 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2121 evaluated.insert(node);
2122 for (auto wire : node_defs[node])
2123 for (auto succ_node : flow.wire_uses[wire])
2124 if (evaluated[succ_node]) {
2125 feedback_wires.insert(wire);
2126 // Feedback wires may never be elided because feedback requires state, but the point of elision
2127 // (and localization) is to eliminate state.
2128 elided_wires.erase(wire);
2129 }
2130 }
2131
2132 if (!feedback_wires.empty()) {
2133 has_feedback_arcs = true;
2134 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2135 for (auto wire : feedback_wires)
2136 log(" %s\n", log_id(wire));
2137 log("\n");
2138 }
2139
2140 for (auto wire : module->wires()) {
2141 if (feedback_wires[wire]) continue;
2142 if (wire->port_id != 0) continue;
2143 if (wire->get_bool_attribute(ID::keep)) continue;
2144 if (wire->name.begins_with("$") && !localize_internal) continue;
2145 if (wire->name.begins_with("\\") && !localize_public) continue;
2146 if (edge_wires[wire]) continue;
2147 if (flow.wire_sync_defs.count(wire) > 0) continue;
2148 localized_wires.insert(wire);
2149 }
2150
2151 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2152 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2153 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2154 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2155 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2156 // also require more than one delta cycle to converge.
2157 pool<const RTLIL::Wire*> buffered_wires;
2158 for (auto wire : module->wires()) {
2159 if (flow.wire_comb_defs[wire].size() > 0 && !elided_wires.count(wire) && !localized_wires[wire]) {
2160 if (!feedback_wires[wire])
2161 buffered_wires.insert(wire);
2162 }
2163 }
2164 if (!buffered_wires.empty()) {
2165 has_buffered_wires = true;
2166 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2167 for (auto wire : buffered_wires)
2168 log(" %s\n", log_id(wire));
2169 log("\n");
2170 }
2171
2172 eval_converges[module] = feedback_wires.empty() && buffered_wires.empty();
2173
2174 if (debug_info) {
2175 // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
2176 // at essentially zero additional cost.
2177 //
2178 // Note that the information collected here can't be used for optimizing the netlist: debug information queries
2179 // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
2180 for (auto wire : module->wires()) {
2181 if (wire->name[0] != '\\')
2182 continue;
2183 if (!localized_wires[wire])
2184 continue;
2185 const RTLIL::Wire *wire_it = wire;
2186 while (1) {
2187 if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it]))
2188 break; // not an alias: complex def
2189 log_assert(flow.wire_comb_defs[wire_it].size() == 1);
2190 FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin();
2191 if (node->type != FlowGraph::Node::Type::CONNECT)
2192 break; // not an alias: def by cell
2193 RTLIL::SigSpec rhs_sig = node->connect.second;
2194 if (rhs_sig.is_wire()) {
2195 RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
2196 if (localized_wires[rhs_wire]) {
2197 wire_it = rhs_wire; // maybe an alias
2198 } else {
2199 debug_alias_wires[wire] = rhs_wire; // is an alias
2200 break;
2201 }
2202 } else if (rhs_sig.is_fully_const()) {
2203 debug_const_wires[wire] = rhs_sig.as_const(); // is a const
2204 break;
2205 } else {
2206 break; // not an alias: complex rhs
2207 }
2208 }
2209 }
2210 }
2211 }
2212 if (has_feedback_arcs || has_buffered_wires) {
2213 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2214 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2215 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2216 const char *why_pessimistic = nullptr;
2217 if (has_feedback_arcs)
2218 why_pessimistic = "feedback wires";
2219 else if (has_buffered_wires)
2220 why_pessimistic = "buffered combinatorial wires";
2221 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2222 if (!max_opt_level)
2223 log("Increasing the optimization level may eliminate %s from the design.\n", why_pessimistic);
2224 }
2225 }
2226
2227 void check_design(RTLIL::Design *design, bool &has_sync_init, bool &has_packed_mem)
2228 {
2229 has_sync_init = has_packed_mem = false;
2230
2231 for (auto module : design->modules()) {
2232 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2233 continue;
2234
2235 if (!design->selected_whole_module(module))
2236 if (design->selected_module(module))
2237 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2238 if (!design->selected_module(module))
2239 continue;
2240
2241 for (auto proc : module->processes)
2242 for (auto sync : proc.second->syncs)
2243 if (sync->type == RTLIL::STi)
2244 has_sync_init = true;
2245
2246 for (auto cell : module->cells())
2247 if (cell->type == ID($mem))
2248 has_packed_mem = true;
2249 }
2250 }
2251
2252 void prepare_design(RTLIL::Design *design)
2253 {
2254 bool did_anything = false;
2255 bool has_sync_init, has_packed_mem;
2256 log_push();
2257 check_design(design, has_sync_init, has_packed_mem);
2258 if (run_proc_flatten) {
2259 Pass::call(design, "proc");
2260 Pass::call(design, "flatten");
2261 did_anything = true;
2262 } else if (has_sync_init) {
2263 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2264 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2265 Pass::call(design, "proc_prune");
2266 Pass::call(design, "proc_clean");
2267 Pass::call(design, "proc_init");
2268 did_anything = true;
2269 }
2270 if (has_packed_mem) {
2271 Pass::call(design, "memory_unpack");
2272 did_anything = true;
2273 }
2274 // Recheck the design if it was modified.
2275 if (has_sync_init || has_packed_mem)
2276 check_design(design, has_sync_init, has_packed_mem);
2277 log_assert(!(has_sync_init || has_packed_mem));
2278 log_pop();
2279 if (did_anything)
2280 log_spacer();
2281 analyze_design(design);
2282 }
2283 };
2284
2285 struct CxxrtlBackend : public Backend {
2286 static const int DEFAULT_OPT_LEVEL = 5;
2287 static const int DEFAULT_DEBUG_LEVEL = 1;
2288
2289 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2290 void help() YS_OVERRIDE
2291 {
2292 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2293 log("\n");
2294 log(" write_cxxrtl [options] [filename]\n");
2295 log("\n");
2296 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2297 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2298 log("\n");
2299 log("The following driver may be used as an example for a design with a single clock\n");
2300 log("driving rising edge triggered flip-flops:\n");
2301 log("\n");
2302 log(" #include \"top.cc\"\n");
2303 log("\n");
2304 log(" int main() {\n");
2305 log(" cxxrtl_design::p_top top;\n");
2306 log(" top.step();\n");
2307 log(" while (1) {\n");
2308 log(" /* user logic */\n");
2309 log(" top.p_clk = value<1> {0u};\n");
2310 log(" top.step();\n");
2311 log(" top.p_clk = value<1> {1u};\n");
2312 log(" top.step();\n");
2313 log(" }\n");
2314 log(" }\n");
2315 log("\n");
2316 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2317 log("subject to race conditions. If, in the example above, the user logic would run\n");
2318 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2319 log("\n");
2320 log("This backend supports replacing parts of the design with black boxes implemented\n");
2321 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2322 log("and the generated code consists only of an interface and a factory function.\n");
2323 log("The driver must implement the factory function that creates an implementation of\n");
2324 log("the black box, taking into account the parameters it is instantiated with.\n");
2325 log("\n");
2326 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2327 log("a synchronous debug sink:\n");
2328 log("\n");
2329 log(" (* cxxrtl_blackbox *)\n");
2330 log(" module debug(...);\n");
2331 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2332 log(" input en;\n");
2333 log(" input [7:0] i_data;\n");
2334 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2335 log(" endmodule\n");
2336 log("\n");
2337 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2338 log("\n");
2339 log(" struct bb_p_debug : public module {\n");
2340 log(" value<1> p_clk;\n");
2341 log(" bool posedge_p_clk() const { /* ... */ }\n");
2342 log(" value<1> p_en;\n");
2343 log(" value<8> p_i_data;\n");
2344 log(" wire<8> p_o_data;\n");
2345 log("\n");
2346 log(" bool eval() override;\n");
2347 log(" bool commit() override;\n");
2348 log("\n");
2349 log(" static std::unique_ptr<bb_p_debug>\n");
2350 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2351 log(" };\n");
2352 log("\n");
2353 log("The `create' function must be implemented by the driver. For example, it could\n");
2354 log("always provide an implementation logging the values to standard error stream:\n");
2355 log("\n");
2356 log(" namespace cxxrtl_design {\n");
2357 log("\n");
2358 log(" struct stderr_debug : public bb_p_debug {\n");
2359 log(" bool eval() override {\n");
2360 log(" if (posedge_p_clk() && p_en)\n");
2361 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2362 log(" p_o_data.next = p_i_data;\n");
2363 log(" return bb_p_debug::eval();\n");
2364 log(" }\n");
2365 log(" };\n");
2366 log("\n");
2367 log(" std::unique_ptr<bb_p_debug>\n");
2368 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2369 log(" cxxrtl::metadata_map attributes) {\n");
2370 log(" return std::make_unique<stderr_debug>();\n");
2371 log(" }\n");
2372 log("\n");
2373 log(" }\n");
2374 log("\n");
2375 log("For complex applications of black boxes, it is possible to parameterize their\n");
2376 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2377 log("interface for a configurable width debug sink:\n");
2378 log("\n");
2379 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2380 log(" module debug(...);\n");
2381 log(" parameter WIDTH = 8;\n");
2382 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2383 log(" input en;\n");
2384 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2385 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2386 log(" endmodule\n");
2387 log("\n");
2388 log("For this parametric HDL interface, this backend will generate the following C++\n");
2389 log("interface (only the differences are shown):\n");
2390 log("\n");
2391 log(" template<size_t WIDTH>\n");
2392 log(" struct bb_p_debug : public module {\n");
2393 log(" // ...\n");
2394 log(" value<WIDTH> p_i_data;\n");
2395 log(" wire<WIDTH> p_o_data;\n");
2396 log(" // ...\n");
2397 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2398 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2399 log(" };\n");
2400 log("\n");
2401 log("The `create' function must be implemented by the driver, specialized for every\n");
2402 log("possible combination of template parameters. (Specialization is necessary to\n");
2403 log("enable separate compilation of generated code and black box implementations.)\n");
2404 log("\n");
2405 log(" template<size_t SIZE>\n");
2406 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2407 log(" // ...\n");
2408 log(" };\n");
2409 log("\n");
2410 log(" template<>\n");
2411 log(" std::unique_ptr<bb_p_debug<8>>\n");
2412 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2413 log(" cxxrtl::metadata_map attributes) {\n");
2414 log(" return std::make_unique<stderr_debug<8>>();\n");
2415 log(" }\n");
2416 log("\n");
2417 log("The following attributes are recognized by this backend:\n");
2418 log("\n");
2419 log(" cxxrtl_blackbox\n");
2420 log(" only valid on modules. if specified, the module contents are ignored,\n");
2421 log(" and the generated code includes only the module interface and a factory\n");
2422 log(" function, which will be called to instantiate the module.\n");
2423 log("\n");
2424 log(" cxxrtl_edge\n");
2425 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2426 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2427 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2428 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2429 log("\n");
2430 log(" cxxrtl_template\n");
2431 log(" only valid on black boxes. must contain a space separated sequence of\n");
2432 log(" identifiers that have a corresponding black box parameters. for each\n");
2433 log(" of them, the generated code includes a `size_t` template parameter.\n");
2434 log("\n");
2435 log(" cxxrtl_width\n");
2436 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2437 log(" is directly inserted into generated code.\n");
2438 log("\n");
2439 log(" cxxrtl_comb, cxxrtl_sync\n");
2440 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2441 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2442 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2443 log(" if neither is specified, the output will be pessimistically treated as\n");
2444 log(" driven by both combinatorial and synchronous logic.\n");
2445 log("\n");
2446 log("The following options are supported by this backend:\n");
2447 log("\n");
2448 log(" -header\n");
2449 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2450 log(" if specified, the backend must be called with a filename, and filename\n");
2451 log(" of the interface is derived from filename of the implementation.\n");
2452 log(" otherwise, interface and implementation are generated together.\n");
2453 log("\n");
2454 log(" -namespace <ns-name>\n");
2455 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2456 log(" \"cxxrtl_design\" is used.\n");
2457 log("\n");
2458 log(" -O <level>\n");
2459 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2460 log(" levels dramatically decrease compile and run time, and highest level\n");
2461 log(" possible for a design should be used.\n");
2462 log("\n");
2463 log(" -O0\n");
2464 log(" no optimization.\n");
2465 log("\n");
2466 log(" -O1\n");
2467 log(" elide internal wires if possible.\n");
2468 log("\n");
2469 log(" -O2\n");
2470 log(" like -O1, and localize internal wires if possible.\n");
2471 log("\n");
2472 log(" -O3\n");
2473 log(" like -O2, and elide public wires not marked (*keep*) if possible.\n");
2474 log("\n");
2475 log(" -O4\n");
2476 log(" like -O3, and localize public wires not marked (*keep*) if possible.\n");
2477 log("\n");
2478 log(" -O5\n");
2479 log(" like -O4, and run `proc; flatten` first.\n");
2480 log("\n");
2481 log(" -g <level>\n");
2482 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2483 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2484 log("\n");
2485 log(" -g0\n");
2486 log(" no debug information.\n");
2487 log("\n");
2488 log(" -g1\n");
2489 log(" debug information for non-optimized public wires. this also makes it\n");
2490 log(" possible to use the C API.\n");
2491 log("\n");
2492 }
2493
2494 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
2495 {
2496 int opt_level = DEFAULT_OPT_LEVEL;
2497 int debug_level = DEFAULT_DEBUG_LEVEL;
2498 CxxrtlWorker worker;
2499
2500 log_header(design, "Executing CXXRTL backend.\n");
2501
2502 size_t argidx;
2503 for (argidx = 1; argidx < args.size(); argidx++)
2504 {
2505 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2506 opt_level = std::stoi(args[++argidx]);
2507 continue;
2508 }
2509 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2510 opt_level = std::stoi(args[argidx].substr(2));
2511 continue;
2512 }
2513 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2514 debug_level = std::stoi(args[++argidx]);
2515 continue;
2516 }
2517 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2518 debug_level = std::stoi(args[argidx].substr(2));
2519 continue;
2520 }
2521 if (args[argidx] == "-header") {
2522 worker.split_intf = true;
2523 continue;
2524 }
2525 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2526 worker.design_ns = args[++argidx];
2527 continue;
2528 }
2529 break;
2530 }
2531 extra_args(f, filename, args, argidx);
2532
2533 switch (opt_level) {
2534 // the highest level here must match DEFAULT_OPT_LEVEL
2535 case 5:
2536 worker.max_opt_level = true;
2537 worker.run_proc_flatten = true;
2538 YS_FALLTHROUGH
2539 case 4:
2540 worker.localize_public = true;
2541 YS_FALLTHROUGH
2542 case 3:
2543 worker.elide_public = true;
2544 YS_FALLTHROUGH
2545 case 2:
2546 worker.localize_internal = true;
2547 YS_FALLTHROUGH
2548 case 1:
2549 worker.elide_internal = true;
2550 YS_FALLTHROUGH
2551 case 0:
2552 break;
2553 default:
2554 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2555 }
2556
2557 switch (debug_level) {
2558 // the highest level here must match DEFAULT_DEBUG_LEVEL
2559 case 1:
2560 worker.debug_info = true;
2561 YS_FALLTHROUGH
2562 case 0:
2563 break;
2564 default:
2565 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2566 }
2567
2568 std::ofstream intf_f;
2569 if (worker.split_intf) {
2570 if (filename == "<stdout>")
2571 log_cmd_error("Option -header must be used with a filename.\n");
2572
2573 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2574 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2575 if (intf_f.fail())
2576 log_cmd_error("Can't open file `%s' for writing: %s\n",
2577 worker.intf_filename.c_str(), strerror(errno));
2578
2579 worker.intf_f = &intf_f;
2580 }
2581 worker.impl_f = f;
2582
2583 worker.prepare_design(design);
2584 worker.dump_design(design);
2585 }
2586 } CxxrtlBackend;
2587
2588 PRIVATE_NAMESPACE_END