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Merge pull request #2414 from zeldin/abc-depend-clang-fix
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/mem.h"
26 #include "kernel/log.h"
27
28 USING_YOSYS_NAMESPACE
29 PRIVATE_NAMESPACE_BEGIN
30
31 // [[CITE]]
32 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
33 // Information Processing Letters, Vol. 47, pp 319-323, 1993
34 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
35
36 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
37 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
38 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
39 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
40 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
41 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
42 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
43 template<class T>
44 struct Scheduler {
45 struct Vertex {
46 T *data;
47 Vertex *prev, *next;
48 pool<Vertex*, hash_ptr_ops> preds, succs;
49
50 Vertex() : data(NULL), prev(this), next(this) {}
51 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
52
53 bool empty() const
54 {
55 log_assert(data == NULL);
56 if (next == this) {
57 log_assert(prev == next);
58 return true;
59 }
60 return false;
61 }
62
63 void link(Vertex *list)
64 {
65 log_assert(prev == NULL && next == NULL);
66 next = list;
67 prev = list->prev;
68 list->prev->next = this;
69 list->prev = this;
70 }
71
72 void unlink()
73 {
74 log_assert(prev->next == this && next->prev == this);
75 prev->next = next;
76 next->prev = prev;
77 next = prev = NULL;
78 }
79
80 int delta() const
81 {
82 return succs.size() - preds.size();
83 }
84 };
85
86 std::vector<Vertex*> vertices;
87 Vertex *sources = new Vertex;
88 Vertex *sinks = new Vertex;
89 dict<int, Vertex*> bins;
90
91 ~Scheduler()
92 {
93 delete sources;
94 delete sinks;
95 for (auto bin : bins)
96 delete bin.second;
97 for (auto vertex : vertices)
98 delete vertex;
99 }
100
101 Vertex *add(T *data)
102 {
103 Vertex *vertex = new Vertex(data);
104 vertices.push_back(vertex);
105 return vertex;
106 }
107
108 void relink(Vertex *vertex)
109 {
110 if (vertex->succs.empty())
111 vertex->link(sinks);
112 else if (vertex->preds.empty())
113 vertex->link(sources);
114 else {
115 int delta = vertex->delta();
116 if (!bins.count(delta))
117 bins[delta] = new Vertex;
118 vertex->link(bins[delta]);
119 }
120 }
121
122 Vertex *remove(Vertex *vertex)
123 {
124 vertex->unlink();
125 for (auto pred : vertex->preds) {
126 if (pred == vertex)
127 continue;
128 log_assert(pred->succs[vertex]);
129 pred->unlink();
130 pred->succs.erase(vertex);
131 relink(pred);
132 }
133 for (auto succ : vertex->succs) {
134 if (succ == vertex)
135 continue;
136 log_assert(succ->preds[vertex]);
137 succ->unlink();
138 succ->preds.erase(vertex);
139 relink(succ);
140 }
141 vertex->preds.clear();
142 vertex->succs.clear();
143 return vertex;
144 }
145
146 std::vector<Vertex*> schedule()
147 {
148 std::vector<Vertex*> s1, s2r;
149 for (auto vertex : vertices)
150 relink(vertex);
151 bool bins_empty = false;
152 while (!(sinks->empty() && sources->empty() && bins_empty)) {
153 while (!sinks->empty())
154 s2r.push_back(remove(sinks->next));
155 while (!sources->empty())
156 s1.push_back(remove(sources->next));
157 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
158 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
159 // naive implementation of find-max-key.
160 bins_empty = true;
161 bins.template sort<std::greater<int>>();
162 for (auto bin : bins) {
163 if (!bin.second->empty()) {
164 bins_empty = false;
165 s1.push_back(remove(bin.second->next));
166 break;
167 }
168 }
169 }
170 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
171 return s1;
172 }
173 };
174
175 bool is_unary_cell(RTLIL::IdString type)
176 {
177 return type.in(
178 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
179 ID($pos), ID($neg));
180 }
181
182 bool is_binary_cell(RTLIL::IdString type)
183 {
184 return type.in(
185 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
186 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
187 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
188 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
189 }
190
191 bool is_extending_cell(RTLIL::IdString type)
192 {
193 return !type.in(
194 ID($logic_not), ID($logic_and), ID($logic_or),
195 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
196 }
197
198 bool is_elidable_cell(RTLIL::IdString type)
199 {
200 return is_unary_cell(type) || is_binary_cell(type) || type.in(
201 ID($mux), ID($concat), ID($slice), ID($pmux));
202 }
203
204 bool is_ff_cell(RTLIL::IdString type)
205 {
206 return type.in(
207 ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
208 ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
209 ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
210 }
211
212 bool is_internal_cell(RTLIL::IdString type)
213 {
214 return type[0] == '$' && !type.begins_with("$paramod");
215 }
216
217 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
218 {
219 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
220 log_assert(cell_module != nullptr);
221 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
222 }
223
224 enum class CxxrtlPortType {
225 UNKNOWN = 0, // or mixed comb/sync
226 COMB = 1,
227 SYNC = 2,
228 };
229
230 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
231 {
232 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
233 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
234 return CxxrtlPortType::UNKNOWN;
235 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
236 log_assert(cell_output_wire != nullptr);
237 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
238 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
239 if (is_comb && is_sync)
240 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
241 log_id(cell_module), log_signal(cell_output_wire));
242 else if (is_comb)
243 return CxxrtlPortType::COMB;
244 else if (is_sync)
245 return CxxrtlPortType::SYNC;
246 return CxxrtlPortType::UNKNOWN;
247 }
248
249 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
250 {
251 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
252 }
253
254 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
255 {
256 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
257 }
258
259 struct FlowGraph {
260 struct Node {
261 enum class Type {
262 CONNECT,
263 CELL_SYNC,
264 CELL_EVAL,
265 PROCESS
266 };
267
268 Type type;
269 RTLIL::SigSig connect = {};
270 const RTLIL::Cell *cell = NULL;
271 const RTLIL::Process *process = NULL;
272 };
273
274 std::vector<Node*> nodes;
275 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
276 dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
277 dict<RTLIL::SigBit, bool> bit_has_state;
278
279 ~FlowGraph()
280 {
281 for (auto node : nodes)
282 delete node;
283 }
284
285 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool elidable)
286 {
287 for (auto chunk : sig.chunks())
288 if (chunk.wire) {
289 if (is_ff) {
290 // A sync def means that a wire holds design state because it is driven directly by
291 // a flip-flop output. Such a wire can never be unbuffered.
292 wire_sync_defs[chunk.wire].insert(node);
293 } else {
294 // A comb def means that a wire doesn't hold design state. It might still be connected,
295 // indirectly, to a flip-flop output.
296 wire_comb_defs[chunk.wire].insert(node);
297 }
298 }
299 for (auto bit : sig.bits())
300 bit_has_state[bit] |= is_ff;
301 // Only comb defs of an entire wire in the right order can be elided.
302 if (!is_ff && sig.is_wire())
303 wire_def_elidable[sig.as_wire()] = elidable;
304 }
305
306 void add_uses(Node *node, const RTLIL::SigSpec &sig)
307 {
308 for (auto chunk : sig.chunks())
309 if (chunk.wire) {
310 wire_uses[chunk.wire].insert(node);
311 // Only a single use of an entire wire in the right order can be elided.
312 // (But the use can include other chunks.)
313 if (!wire_use_elidable.count(chunk.wire))
314 wire_use_elidable[chunk.wire] = true;
315 else
316 wire_use_elidable[chunk.wire] = false;
317 }
318 }
319
320 bool is_elidable(const RTLIL::Wire *wire) const
321 {
322 if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire))
323 return wire_def_elidable.at(wire) && wire_use_elidable.at(wire);
324 return false;
325 }
326
327 // Connections
328 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
329 {
330 add_defs(node, conn.first, /*is_ff=*/false, /*elidable=*/true);
331 add_uses(node, conn.second);
332 }
333
334 Node *add_node(const RTLIL::SigSig &conn)
335 {
336 Node *node = new Node;
337 node->type = Node::Type::CONNECT;
338 node->connect = conn;
339 nodes.push_back(node);
340 add_connect_defs_uses(node, conn);
341 return node;
342 }
343
344 // Cells
345 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
346 {
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
352 //
353 // wire<1> i_tmp;
354 // cell->p_i = i_tmp.curr;
355 // cell->eval();
356 // i_tmp.next = cell->p_o.curr;
357 //
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
361 //
362 // value<1> i_tmp;
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
365 // cell->eval();
366 //
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn : cell->connections())
374 if (cell->output(conn.first))
375 if (is_cxxrtl_sync_port(cell, conn.first)) {
376 // See note regarding elidability below.
377 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false);
378 }
379 }
380
381 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
382 {
383 for (auto conn : cell->connections()) {
384 if (cell->output(conn.first)) {
385 if (is_elidable_cell(cell->type))
386 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/true);
387 else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
388 add_defs(node, conn.second, /*is_ff=*/true, /*elidable=*/false);
389 else if (is_internal_cell(cell->type))
390 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false);
391 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
392 // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
396 // the infrastructure required to elide outputs of cells with many of them.
397 add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false);
398 }
399 }
400 if (cell->input(conn.first))
401 add_uses(node, conn.second);
402 }
403 }
404
405 Node *add_node(const RTLIL::Cell *cell)
406 {
407 log_assert(cell->known());
408
409 bool has_fully_sync_outputs = false;
410 for (auto conn : cell->connections())
411 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
412 has_fully_sync_outputs = true;
413 break;
414 }
415 if (has_fully_sync_outputs) {
416 Node *node = new Node;
417 node->type = Node::Type::CELL_SYNC;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_sync_defs(node, cell);
421 }
422
423 Node *node = new Node;
424 node->type = Node::Type::CELL_EVAL;
425 node->cell = cell;
426 nodes.push_back(node);
427 add_cell_eval_defs_uses(node, cell);
428 return node;
429 }
430
431 // Processes
432 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
433 {
434 for (auto &action : case_->actions) {
435 add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false);
436 add_uses(node, action.second);
437 }
438 for (auto sub_switch : case_->switches) {
439 add_uses(node, sub_switch->signal);
440 for (auto sub_case : sub_switch->cases) {
441 for (auto &compare : sub_case->compare)
442 add_uses(node, compare);
443 add_case_defs_uses(node, sub_case);
444 }
445 }
446 }
447
448 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
449 {
450 add_case_defs_uses(node, &process->root_case);
451 for (auto sync : process->syncs)
452 for (auto action : sync->actions) {
453 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
454 add_defs(node, action.first, /*is_ff=*/true, /*elidable=*/false);
455 else
456 add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false);
457 add_uses(node, action.second);
458 }
459 }
460
461 Node *add_node(const RTLIL::Process *process)
462 {
463 Node *node = new Node;
464 node->type = Node::Type::PROCESS;
465 node->process = process;
466 nodes.push_back(node);
467 add_process_defs_uses(node, process);
468 return node;
469 }
470 };
471
472 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
473 {
474 std::vector<std::string> result;
475 size_t prev = 0;
476 while (true) {
477 size_t curr = str.find_first_of(sep, prev);
478 if (curr == std::string::npos) {
479 std::string part = str.substr(prev);
480 if (!part.empty()) result.push_back(part);
481 break;
482 } else {
483 std::string part = str.substr(prev, curr - prev);
484 if (!part.empty()) result.push_back(part);
485 prev = curr + 1;
486 }
487 }
488 return result;
489 }
490
491 std::string escape_cxx_string(const std::string &input)
492 {
493 std::string output = "\"";
494 for (auto c : input) {
495 if (::isprint(c)) {
496 if (c == '\\')
497 output.push_back('\\');
498 output.push_back(c);
499 } else {
500 char l = c & 0xf, h = (c >> 4) & 0xf;
501 output.append("\\x");
502 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
503 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
504 }
505 }
506 output.push_back('"');
507 if (output.find('\0') != std::string::npos) {
508 output.insert(0, "std::string {");
509 output.append(stringf(", %zu}", input.size()));
510 }
511 return output;
512 }
513
514 template<class T>
515 std::string get_hdl_name(T *object)
516 {
517 if (object->has_attribute(ID::hdlname))
518 return object->get_string_attribute(ID::hdlname);
519 else
520 return object->name.str().substr(1);
521 }
522
523 struct CxxrtlWorker {
524 bool split_intf = false;
525 std::string intf_filename;
526 std::string design_ns = "cxxrtl_design";
527 std::ostream *impl_f = nullptr;
528 std::ostream *intf_f = nullptr;
529
530 bool run_hierarchy = false;
531 bool run_flatten = false;
532 bool run_proc = false;
533
534 bool unbuffer_internal = false;
535 bool unbuffer_public = false;
536 bool localize_internal = false;
537 bool localize_public = false;
538 bool elide_internal = false;
539 bool elide_public = false;
540
541 bool debug_info = false;
542
543 std::ostringstream f;
544 std::string indent;
545 int temporary = 0;
546
547 dict<const RTLIL::Module*, SigMap> sigmaps;
548 pool<const RTLIL::Wire*> edge_wires;
549 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
550 pool<const RTLIL::Memory*> writable_memories;
551 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
552 dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
553 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
554 pool<const RTLIL::Wire*> unbuffered_wires;
555 pool<const RTLIL::Wire*> localized_wires;
556 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
557 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
558 dict<RTLIL::SigBit, bool> bit_has_state;
559 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
560 dict<const RTLIL::Module*, bool> eval_converges;
561
562 void inc_indent() {
563 indent += "\t";
564 }
565 void dec_indent() {
566 indent.resize(indent.size() - 1);
567 }
568
569 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
570 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
571 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
572 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
573 // 1. All generated identifiers start with `_`.
574 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
575 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
576 // 2. An underscore is escaped with another underscore, i.e. `__`.
577 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
578 std::string mangle_name(const RTLIL::IdString &name)
579 {
580 std::string mangled;
581 bool first = true;
582 for (char c : name.str()) {
583 if (first) {
584 first = false;
585 if (c == '\\')
586 mangled += "p_";
587 else if (c == '$')
588 mangled += "i_";
589 else
590 log_assert(false);
591 } else {
592 if (isalnum(c)) {
593 mangled += c;
594 } else if (c == '_') {
595 mangled += "__";
596 } else {
597 char l = c & 0xf, h = (c >> 4) & 0xf;
598 mangled += '_';
599 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
600 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
601 mangled += '_';
602 }
603 }
604 }
605 return mangled;
606 }
607
608 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
609 {
610 // Class namespace.
611 if (is_blackbox)
612 return "bb_" + mangle_name(name);
613 return mangle_name(name);
614 }
615
616 std::string mangle_memory_name(const RTLIL::IdString &name)
617 {
618 // Class member namespace.
619 return "memory_" + mangle_name(name);
620 }
621
622 std::string mangle_cell_name(const RTLIL::IdString &name)
623 {
624 // Class member namespace.
625 return "cell_" + mangle_name(name);
626 }
627
628 std::string mangle_wire_name(const RTLIL::IdString &name)
629 {
630 // Class member namespace.
631 return mangle_name(name);
632 }
633
634 std::string mangle(const RTLIL::Module *module)
635 {
636 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
637 }
638
639 std::string mangle(const RTLIL::Memory *memory)
640 {
641 return mangle_memory_name(memory->name);
642 }
643
644 std::string mangle(const RTLIL::Cell *cell)
645 {
646 return mangle_cell_name(cell->name);
647 }
648
649 std::string mangle(const RTLIL::Wire *wire)
650 {
651 return mangle_wire_name(wire->name);
652 }
653
654 std::string mangle(RTLIL::SigBit sigbit)
655 {
656 log_assert(sigbit.wire != NULL);
657 if (sigbit.wire->width == 1)
658 return mangle(sigbit.wire);
659 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
660 }
661
662 std::vector<std::string> template_param_names(const RTLIL::Module *module)
663 {
664 if (!module->has_attribute(ID(cxxrtl_template)))
665 return {};
666
667 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
668 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
669
670 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
671 for (const auto &param_name : param_names) {
672 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
673 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
674 // in both Verilog and C++, anyway.)
675 if (!isupper(param_name[0]))
676 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
677 "which does not start with an uppercase letter.\n",
678 log_id(module), param_name.c_str());
679 }
680 return param_names;
681 }
682
683 std::string template_params(const RTLIL::Module *module, bool is_decl)
684 {
685 std::vector<std::string> param_names = template_param_names(module);
686 if (param_names.empty())
687 return "";
688
689 std::string params = "<";
690 bool first = true;
691 for (const auto &param_name : param_names) {
692 if (!first)
693 params += ", ";
694 first = false;
695 if (is_decl)
696 params += "size_t ";
697 params += param_name;
698 }
699 params += ">";
700 return params;
701 }
702
703 std::string template_args(const RTLIL::Cell *cell)
704 {
705 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
706 log_assert(cell_module != nullptr);
707 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
708 return "";
709
710 std::vector<std::string> param_names = template_param_names(cell_module);
711 if (param_names.empty())
712 return "";
713
714 std::string params = "<";
715 bool first = true;
716 for (const auto &param_name : param_names) {
717 if (!first)
718 params += ", ";
719 first = false;
720 params += "/*" + param_name + "=*/";
721 RTLIL::IdString id_param_name = '\\' + param_name;
722 if (!cell->hasParam(id_param_name))
723 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
724 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
725 RTLIL::Const param_value = cell->getParam(id_param_name);
726 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
727 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
728 "is not a positive integer.\n",
729 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
730 params += std::to_string(cell->getParam(id_param_name).as_int());
731 }
732 params += ">";
733 return params;
734 }
735
736 std::string fresh_temporary()
737 {
738 return stringf("tmp_%d", temporary++);
739 }
740
741 void dump_attrs(const RTLIL::AttrObject *object)
742 {
743 for (auto attr : object->attributes) {
744 f << indent << "// " << attr.first.str() << ": ";
745 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
746 f << attr.second.decode_string();
747 } else {
748 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
749 }
750 f << "\n";
751 }
752 }
753
754 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
755 {
756 const int CHUNK_SIZE = 32;
757 f << "{";
758 while (width > 0) {
759 int chunk_width = min(width, CHUNK_SIZE);
760 uint32_t chunk = data.extract(offset, chunk_width).as_int();
761 if (fixed_width)
762 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
763 else
764 f << stringf("%#xu", chunk);
765 if (width > CHUNK_SIZE)
766 f << ',';
767 offset += CHUNK_SIZE;
768 width -= CHUNK_SIZE;
769 }
770 f << "}";
771 }
772
773 void dump_const_init(const RTLIL::Const &data)
774 {
775 dump_const_init(data, data.size());
776 }
777
778 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
779 {
780 f << "value<" << width << ">";
781 dump_const_init(data, width, offset, fixed_width);
782 }
783
784 void dump_const(const RTLIL::Const &data)
785 {
786 dump_const(data, data.size());
787 }
788
789 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs)
790 {
791 if (chunk.wire == NULL) {
792 dump_const(chunk.data, chunk.width, chunk.offset);
793 return false;
794 } else {
795 if (elided_wires.count(chunk.wire)) {
796 log_assert(!is_lhs);
797 const FlowGraph::Node &node = elided_wires[chunk.wire];
798 switch (node.type) {
799 case FlowGraph::Node::Type::CONNECT:
800 dump_connect_elided(node.connect);
801 break;
802 case FlowGraph::Node::Type::CELL_EVAL:
803 log_assert(is_elidable_cell(node.cell->type));
804 dump_cell_elided(node.cell);
805 break;
806 default:
807 log_assert(false);
808 }
809 } else if (unbuffered_wires[chunk.wire]) {
810 f << mangle(chunk.wire);
811 } else {
812 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
813 }
814 if (chunk.width == chunk.wire->width && chunk.offset == 0)
815 return false;
816 else if (chunk.width == 1)
817 f << ".slice<" << chunk.offset << ">()";
818 else
819 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
820 return true;
821 }
822 }
823
824 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs)
825 {
826 if (sig.empty()) {
827 f << "value<0>()";
828 return false;
829 } else if (sig.is_chunk()) {
830 return dump_sigchunk(sig.as_chunk(), is_lhs);
831 } else {
832 dump_sigchunk(*sig.chunks().rbegin(), is_lhs);
833 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
834 f << ".concat(";
835 dump_sigchunk(*it, is_lhs);
836 f << ")";
837 }
838 return true;
839 }
840 }
841
842 void dump_sigspec_lhs(const RTLIL::SigSpec &sig)
843 {
844 dump_sigspec(sig, /*is_lhs=*/true);
845 }
846
847 void dump_sigspec_rhs(const RTLIL::SigSpec &sig)
848 {
849 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
850 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
851 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
852 // type conversion, but only if the expression needs it.
853 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false);
854 if (is_complex)
855 f << ".val()";
856 }
857
858 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
859 {
860 for (auto chunk : sig.chunks()) {
861 if (!chunk.wire || !elided_wires.count(chunk.wire))
862 continue;
863
864 const FlowGraph::Node &node = elided_wires[chunk.wire];
865 switch (node.type) {
866 case FlowGraph::Node::Type::CONNECT:
867 collect_connect(node.connect, cells);
868 break;
869 case FlowGraph::Node::Type::CELL_EVAL:
870 collect_cell_eval(node.cell, cells);
871 break;
872 default:
873 log_assert(false);
874 }
875 }
876 }
877
878 void dump_connect_elided(const RTLIL::SigSig &conn)
879 {
880 dump_sigspec_rhs(conn.second);
881 }
882
883 bool is_connect_elided(const RTLIL::SigSig &conn)
884 {
885 return conn.first.is_wire() && elided_wires.count(conn.first.as_wire());
886 }
887
888 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
889 {
890 if (!is_connect_elided(conn))
891 return;
892
893 collect_sigspec_rhs(conn.second, cells);
894 }
895
896 void dump_connect(const RTLIL::SigSig &conn)
897 {
898 if (is_connect_elided(conn))
899 return;
900
901 f << indent << "// connection\n";
902 f << indent;
903 dump_sigspec_lhs(conn.first);
904 f << " = ";
905 dump_connect_elided(conn);
906 f << ";\n";
907 }
908
909 void dump_cell_sync(const RTLIL::Cell *cell)
910 {
911 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
912 f << indent << "// cell " << cell->name.str() << " syncs\n";
913 for (auto conn : cell->connections())
914 if (cell->output(conn.first))
915 if (is_cxxrtl_sync_port(cell, conn.first)) {
916 f << indent;
917 dump_sigspec_lhs(conn.second);
918 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
919 }
920 }
921
922 void dump_cell_elided(const RTLIL::Cell *cell)
923 {
924 // Unary cells
925 if (is_unary_cell(cell->type)) {
926 f << cell->type.substr(1);
927 if (is_extending_cell(cell->type))
928 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
929 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
930 dump_sigspec_rhs(cell->getPort(ID::A));
931 f << ")";
932 // Binary cells
933 } else if (is_binary_cell(cell->type)) {
934 f << cell->type.substr(1);
935 if (is_extending_cell(cell->type))
936 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
937 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
938 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
939 dump_sigspec_rhs(cell->getPort(ID::A));
940 f << ", ";
941 dump_sigspec_rhs(cell->getPort(ID::B));
942 f << ")";
943 // Muxes
944 } else if (cell->type == ID($mux)) {
945 f << "(";
946 dump_sigspec_rhs(cell->getPort(ID::S));
947 f << " ? ";
948 dump_sigspec_rhs(cell->getPort(ID::B));
949 f << " : ";
950 dump_sigspec_rhs(cell->getPort(ID::A));
951 f << ")";
952 // Parallel (one-hot) muxes
953 } else if (cell->type == ID($pmux)) {
954 int width = cell->getParam(ID::WIDTH).as_int();
955 int s_width = cell->getParam(ID::S_WIDTH).as_int();
956 for (int part = 0; part < s_width; part++) {
957 f << "(";
958 dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
959 f << " ? ";
960 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
961 f << " : ";
962 }
963 dump_sigspec_rhs(cell->getPort(ID::A));
964 for (int part = 0; part < s_width; part++) {
965 f << ")";
966 }
967 // Concats
968 } else if (cell->type == ID($concat)) {
969 dump_sigspec_rhs(cell->getPort(ID::B));
970 f << ".concat(";
971 dump_sigspec_rhs(cell->getPort(ID::A));
972 f << ").val()";
973 // Slices
974 } else if (cell->type == ID($slice)) {
975 dump_sigspec_rhs(cell->getPort(ID::A));
976 f << ".slice<";
977 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
978 f << ",";
979 f << cell->getParam(ID::OFFSET).as_int();
980 f << ">().val()";
981 } else {
982 log_assert(false);
983 }
984 }
985
986 bool is_cell_elided(const RTLIL::Cell *cell)
987 {
988 return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
989 elided_wires.count(cell->getPort(ID::Y).as_wire());
990 }
991
992 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
993 {
994 if (!is_cell_elided(cell))
995 return;
996
997 cells.push_back(cell->name);
998 for (auto port : cell->connections())
999 if (port.first != ID::Y)
1000 collect_sigspec_rhs(port.second, cells);
1001 }
1002
1003 void dump_cell_eval(const RTLIL::Cell *cell)
1004 {
1005 if (is_cell_elided(cell))
1006 return;
1007 if (cell->type == ID($meminit))
1008 return; // Handled elsewhere.
1009
1010 std::vector<RTLIL::IdString> elided_cells;
1011 if (is_elidable_cell(cell->type)) {
1012 for (auto port : cell->connections())
1013 if (port.first != ID::Y)
1014 collect_sigspec_rhs(port.second, elided_cells);
1015 }
1016 if (elided_cells.empty()) {
1017 dump_attrs(cell);
1018 f << indent << "// cell " << cell->name.str() << "\n";
1019 } else {
1020 f << indent << "// cells";
1021 for (auto elided_cell : elided_cells)
1022 f << " " << elided_cell.str();
1023 f << "\n";
1024 }
1025
1026 // Elidable cells
1027 if (is_elidable_cell(cell->type)) {
1028 f << indent;
1029 dump_sigspec_lhs(cell->getPort(ID::Y));
1030 f << " = ";
1031 dump_cell_elided(cell);
1032 f << ";\n";
1033 // Flip-flops
1034 } else if (is_ff_cell(cell->type)) {
1035 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1036 // Edge-sensitive logic
1037 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1038 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1039 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1040 << mangle(clk_bit) << ") {\n";
1041 inc_indent();
1042 if (cell->hasPort(ID::EN)) {
1043 f << indent << "if (";
1044 dump_sigspec_rhs(cell->getPort(ID::EN));
1045 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1046 inc_indent();
1047 }
1048 f << indent;
1049 dump_sigspec_lhs(cell->getPort(ID::Q));
1050 f << " = ";
1051 dump_sigspec_rhs(cell->getPort(ID::D));
1052 f << ";\n";
1053 if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
1054 dec_indent();
1055 f << indent << "}\n";
1056 }
1057 if (cell->hasPort(ID::SRST)) {
1058 f << indent << "if (";
1059 dump_sigspec_rhs(cell->getPort(ID::SRST));
1060 f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
1061 inc_indent();
1062 f << indent;
1063 dump_sigspec_lhs(cell->getPort(ID::Q));
1064 f << " = ";
1065 dump_const(cell->getParam(ID::SRST_VALUE));
1066 f << ";\n";
1067 dec_indent();
1068 f << indent << "}\n";
1069 }
1070 if (cell->hasPort(ID::EN) && cell->type == ID($sdffce)) {
1071 dec_indent();
1072 f << indent << "}\n";
1073 }
1074 dec_indent();
1075 f << indent << "}\n";
1076 } else if (cell->hasPort(ID::EN)) {
1077 // Level-sensitive logic
1078 f << indent << "if (";
1079 dump_sigspec_rhs(cell->getPort(ID::EN));
1080 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1081 inc_indent();
1082 f << indent;
1083 dump_sigspec_lhs(cell->getPort(ID::Q));
1084 f << " = ";
1085 dump_sigspec_rhs(cell->getPort(ID::D));
1086 f << ";\n";
1087 dec_indent();
1088 f << indent << "}\n";
1089 }
1090 if (cell->hasPort(ID::ARST)) {
1091 // Asynchronous reset (entire coarse cell at once)
1092 f << indent << "if (";
1093 dump_sigspec_rhs(cell->getPort(ID::ARST));
1094 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1095 inc_indent();
1096 f << indent;
1097 dump_sigspec_lhs(cell->getPort(ID::Q));
1098 f << " = ";
1099 dump_const(cell->getParam(ID::ARST_VALUE));
1100 f << ";\n";
1101 dec_indent();
1102 f << indent << "}\n";
1103 }
1104 if (cell->hasPort(ID::SET)) {
1105 // Asynchronous set (for individual bits)
1106 f << indent;
1107 dump_sigspec_lhs(cell->getPort(ID::Q));
1108 f << " = ";
1109 dump_sigspec_lhs(cell->getPort(ID::Q));
1110 f << ".update(";
1111 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1112 f << ", ";
1113 dump_sigspec_rhs(cell->getPort(ID::SET));
1114 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1115 }
1116 if (cell->hasPort(ID::CLR)) {
1117 // Asynchronous clear (for individual bits; priority over set)
1118 f << indent;
1119 dump_sigspec_lhs(cell->getPort(ID::Q));
1120 f << " = ";
1121 dump_sigspec_lhs(cell->getPort(ID::Q));
1122 f << ".update(";
1123 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1124 f << ", ";
1125 dump_sigspec_rhs(cell->getPort(ID::CLR));
1126 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1127 }
1128 // Memory ports
1129 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1130 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1131 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1132 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1133 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1134 << mangle(clk_bit) << ") {\n";
1135 inc_indent();
1136 }
1137 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1138 std::string valid_index_temp = fresh_temporary();
1139 f << indent << "auto " << valid_index_temp << " = memory_index(";
1140 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1141 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1142 if (cell->type == ID($memrd)) {
1143 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1144 if (has_enable) {
1145 f << indent << "if (";
1146 dump_sigspec_rhs(cell->getPort(ID::EN));
1147 f << ") {\n";
1148 inc_indent();
1149 }
1150 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1151 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1152 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DNDEBUG not
1153 // just for release builds, but also to make sure the simulator (which is presumably embedded in some
1154 // larger program) will never crash the code that calls into it.
1155 //
1156 // If assertions are disabled, out of bounds reads are defined to return zero.
1157 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1158 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1159 inc_indent();
1160 if (writable_memories[memory]) {
1161 std::string lhs_temp = fresh_temporary();
1162 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1163 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1164 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1165 if (!memwr_cells.empty()) {
1166 std::string addr_temp = fresh_temporary();
1167 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1168 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1169 f << ";\n";
1170 std::sort(memwr_cells.begin(), memwr_cells.end(),
1171 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1172 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1173 });
1174 for (auto memwr_cell : memwr_cells) {
1175 f << indent << "if (" << addr_temp << " == ";
1176 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1177 f << ") {\n";
1178 inc_indent();
1179 f << indent << lhs_temp << " = " << lhs_temp;
1180 f << ".update(";
1181 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1182 f << ", ";
1183 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1184 f << ");\n";
1185 dec_indent();
1186 f << indent << "}\n";
1187 }
1188 }
1189 f << indent;
1190 dump_sigspec_lhs(cell->getPort(ID::DATA));
1191 f << " = " << lhs_temp << ";\n";
1192 } else {
1193 f << indent;
1194 dump_sigspec_lhs(cell->getPort(ID::DATA));
1195 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1196 }
1197 dec_indent();
1198 f << indent << "} else {\n";
1199 inc_indent();
1200 f << indent;
1201 dump_sigspec_lhs(cell->getPort(ID::DATA));
1202 f << " = value<" << memory->width << "> {};\n";
1203 dec_indent();
1204 f << indent << "}\n";
1205 if (has_enable) {
1206 dec_indent();
1207 f << indent << "}\n";
1208 }
1209 } else /*if (cell->type == ID($memwr))*/ {
1210 log_assert(writable_memories[memory]);
1211 // See above for rationale of having both the assert and the condition.
1212 //
1213 // If assertions are disabled, out of bounds writes are defined to do nothing.
1214 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1215 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1216 inc_indent();
1217 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1218 dump_sigspec_rhs(cell->getPort(ID::DATA));
1219 f << ", ";
1220 dump_sigspec_rhs(cell->getPort(ID::EN));
1221 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1222 dec_indent();
1223 f << indent << "}\n";
1224 }
1225 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1226 dec_indent();
1227 f << indent << "}\n";
1228 }
1229 // Internal cells
1230 } else if (is_internal_cell(cell->type)) {
1231 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1232 // User cells
1233 } else {
1234 log_assert(cell->known());
1235 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1236 for (auto conn : cell->connections())
1237 if (cell->input(conn.first) && !cell->output(conn.first)) {
1238 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = ";
1239 dump_sigspec_rhs(conn.second);
1240 f << ";\n";
1241 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1242 // Until we have proper clock tree detection, this really awful hack that opportunistically
1243 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1244 // be if only one clock edge was simulated by replacing:
1245 // top.p_clk = value<1>{0u}; top.step();
1246 // top.p_clk = value<1>{1u}; top.step();
1247 // with:
1248 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1249 // Don't rely on this; it will be removed without warning.
1250 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1251 if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) {
1252 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1253 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1254 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1255 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1256 }
1257 }
1258 }
1259 } else if (cell->input(conn.first)) {
1260 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = ";
1261 dump_sigspec_rhs(conn.second);
1262 f << ";\n";
1263 }
1264 auto assign_from_outputs = [&](bool cell_converged) {
1265 for (auto conn : cell->connections()) {
1266 if (cell->output(conn.first)) {
1267 if (conn.second.empty())
1268 continue; // ignore disconnected ports
1269 if (is_cxxrtl_sync_port(cell, conn.first))
1270 continue; // fully sync ports are handled in CELL_SYNC nodes
1271 f << indent;
1272 dump_sigspec_lhs(conn.second);
1273 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1274 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1275 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1276 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1277 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1278 // and consider the fate of the localized wires that used to be output ports.)
1279 //
1280 // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell
1281 // (which may be late bound) will converge immediately. Because of this, the choice between using .curr
1282 // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime.
1283 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1284 f << ".next;\n";
1285 else
1286 f << ".curr;\n";
1287 }
1288 }
1289 };
1290 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1291 inc_indent();
1292 assign_from_outputs(/*cell_converged=*/true);
1293 dec_indent();
1294 f << indent << "} else {\n";
1295 inc_indent();
1296 f << indent << "converged = false;\n";
1297 assign_from_outputs(/*cell_converged=*/false);
1298 dec_indent();
1299 f << indent << "}\n";
1300 }
1301 }
1302
1303 void dump_assign(const RTLIL::SigSig &sigsig)
1304 {
1305 f << indent;
1306 dump_sigspec_lhs(sigsig.first);
1307 f << " = ";
1308 dump_sigspec_rhs(sigsig.second);
1309 f << ";\n";
1310 }
1311
1312 void dump_case_rule(const RTLIL::CaseRule *rule)
1313 {
1314 for (auto action : rule->actions)
1315 dump_assign(action);
1316 for (auto switch_ : rule->switches)
1317 dump_switch_rule(switch_);
1318 }
1319
1320 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1321 {
1322 // The switch attributes are printed before the switch condition is captured.
1323 dump_attrs(rule);
1324 std::string signal_temp = fresh_temporary();
1325 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1326 dump_sigspec(rule->signal, /*is_lhs=*/false);
1327 f << ";\n";
1328
1329 bool first = true;
1330 for (auto case_ : rule->cases) {
1331 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1332 dump_attrs(rule);
1333 f << indent;
1334 if (!first)
1335 f << "} else ";
1336 first = false;
1337 if (!case_->compare.empty()) {
1338 f << "if (";
1339 bool first = true;
1340 for (auto &compare : case_->compare) {
1341 if (!first)
1342 f << " || ";
1343 first = false;
1344 if (compare.is_fully_def()) {
1345 f << signal_temp << " == ";
1346 dump_sigspec(compare, /*is_lhs=*/false);
1347 } else if (compare.is_fully_const()) {
1348 RTLIL::Const compare_mask, compare_value;
1349 for (auto bit : compare.as_const()) {
1350 switch (bit) {
1351 case RTLIL::S0:
1352 case RTLIL::S1:
1353 compare_mask.bits.push_back(RTLIL::S1);
1354 compare_value.bits.push_back(bit);
1355 break;
1356
1357 case RTLIL::Sx:
1358 case RTLIL::Sz:
1359 case RTLIL::Sa:
1360 compare_mask.bits.push_back(RTLIL::S0);
1361 compare_value.bits.push_back(RTLIL::S0);
1362 break;
1363
1364 default:
1365 log_assert(false);
1366 }
1367 }
1368 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1369 dump_const(compare_mask);
1370 f << ") == ";
1371 dump_const(compare_value);
1372 } else {
1373 log_assert(false);
1374 }
1375 }
1376 f << ") ";
1377 }
1378 f << "{\n";
1379 inc_indent();
1380 dump_case_rule(case_);
1381 dec_indent();
1382 }
1383 f << indent << "}\n";
1384 }
1385
1386 void dump_process(const RTLIL::Process *proc)
1387 {
1388 dump_attrs(proc);
1389 f << indent << "// process " << proc->name.str() << "\n";
1390 // The case attributes (for root case) are always empty.
1391 log_assert(proc->root_case.attributes.empty());
1392 dump_case_rule(&proc->root_case);
1393 for (auto sync : proc->syncs) {
1394 RTLIL::SigBit sync_bit;
1395 if (!sync->signal.empty()) {
1396 sync_bit = sync->signal[0];
1397 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1398 }
1399
1400 pool<std::string> events;
1401 switch (sync->type) {
1402 case RTLIL::STp:
1403 log_assert(sync_bit.wire != nullptr);
1404 events.insert("posedge_" + mangle(sync_bit));
1405 break;
1406 case RTLIL::STn:
1407 log_assert(sync_bit.wire != nullptr);
1408 events.insert("negedge_" + mangle(sync_bit));
1409 break;
1410 case RTLIL::STe:
1411 log_assert(sync_bit.wire != nullptr);
1412 events.insert("posedge_" + mangle(sync_bit));
1413 events.insert("negedge_" + mangle(sync_bit));
1414 break;
1415
1416 case RTLIL::STa:
1417 events.insert("true");
1418 break;
1419
1420 case RTLIL::ST0:
1421 case RTLIL::ST1:
1422 case RTLIL::STg:
1423 case RTLIL::STi:
1424 log_assert(false);
1425 }
1426 if (!events.empty()) {
1427 f << indent << "if (";
1428 bool first = true;
1429 for (auto &event : events) {
1430 if (!first)
1431 f << " || ";
1432 first = false;
1433 f << event;
1434 }
1435 f << ") {\n";
1436 inc_indent();
1437 for (auto action : sync->actions)
1438 dump_assign(action);
1439 dec_indent();
1440 f << indent << "}\n";
1441 }
1442 }
1443 }
1444
1445 void dump_wire(const RTLIL::Wire *wire, bool is_local_context)
1446 {
1447 if (elided_wires.count(wire))
1448 return;
1449
1450 if (localized_wires[wire] && is_local_context) {
1451 dump_attrs(wire);
1452 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1453 }
1454 if (!localized_wires[wire] && !is_local_context) {
1455 std::string width;
1456 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1457 width = wire->get_string_attribute(ID(cxxrtl_width));
1458 } else {
1459 width = std::to_string(wire->width);
1460 }
1461
1462 dump_attrs(wire);
1463 f << indent;
1464 if (wire->port_input && wire->port_output)
1465 f << "/*inout*/ ";
1466 else if (wire->port_input)
1467 f << "/*input*/ ";
1468 else if (wire->port_output)
1469 f << "/*output*/ ";
1470 f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1471 if (wire->has_attribute(ID::init)) {
1472 f << " ";
1473 dump_const_init(wire->attributes.at(ID::init));
1474 }
1475 f << ";\n";
1476 if (edge_wires[wire]) {
1477 if (unbuffered_wires[wire]) {
1478 f << indent << "value<" << width << "> prev_" << mangle(wire);
1479 if (wire->has_attribute(ID::init)) {
1480 f << " ";
1481 dump_const_init(wire->attributes.at(ID::init));
1482 }
1483 f << ";\n";
1484 }
1485 for (auto edge_type : edge_types) {
1486 if (edge_type.first.wire == wire) {
1487 std::string prev, next;
1488 if (unbuffered_wires[wire]) {
1489 prev = "prev_" + mangle(edge_type.first.wire);
1490 next = mangle(edge_type.first.wire);
1491 } else {
1492 prev = mangle(edge_type.first.wire) + ".curr";
1493 next = mangle(edge_type.first.wire) + ".next";
1494 }
1495 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1496 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1497 if (edge_type.second != RTLIL::STn) {
1498 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1499 inc_indent();
1500 f << indent << "return !" << prev << " && " << next << ";\n";
1501 dec_indent();
1502 f << indent << "}\n";
1503 }
1504 if (edge_type.second != RTLIL::STp) {
1505 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1506 inc_indent();
1507 f << indent << "return " << prev << " && !" << next << ";\n";
1508 dec_indent();
1509 f << indent << "}\n";
1510 }
1511 }
1512 }
1513 }
1514 }
1515 }
1516
1517 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1518 {
1519 vector<const RTLIL::Cell*> init_cells;
1520 for (auto cell : module->cells())
1521 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1522 init_cells.push_back(cell);
1523
1524 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1525 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1526 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1527 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1528 });
1529
1530 dump_attrs(memory);
1531 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1532 << " { " << memory->size << "u";
1533 if (init_cells.empty()) {
1534 f << " };\n";
1535 } else {
1536 f << ",\n";
1537 inc_indent();
1538 for (auto cell : init_cells) {
1539 dump_attrs(cell);
1540 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1541 size_t width = cell->getParam(ID::WIDTH).as_int();
1542 size_t words = cell->getParam(ID::WORDS).as_int();
1543 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1544 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1545 inc_indent();
1546 for (size_t n = 0; n < words; n++) {
1547 if (n % 4 == 0)
1548 f << "\n" << indent;
1549 else
1550 f << " ";
1551 dump_const(data, width, n * width, /*fixed_width=*/true);
1552 f << ",";
1553 }
1554 dec_indent();
1555 f << "\n" << indent << "}},\n";
1556 }
1557 dec_indent();
1558 f << indent << "};\n";
1559 }
1560 }
1561
1562 void dump_eval_method(RTLIL::Module *module)
1563 {
1564 inc_indent();
1565 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1566 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1567 for (auto wire : module->wires()) {
1568 if (edge_wires[wire]) {
1569 for (auto edge_type : edge_types) {
1570 if (edge_type.first.wire == wire) {
1571 if (edge_type.second != RTLIL::STn) {
1572 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1573 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1574 }
1575 if (edge_type.second != RTLIL::STp) {
1576 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1577 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1578 }
1579 }
1580 }
1581 }
1582 }
1583 for (auto wire : module->wires())
1584 dump_wire(wire, /*is_local_context=*/true);
1585 for (auto node : schedule[module]) {
1586 switch (node.type) {
1587 case FlowGraph::Node::Type::CONNECT:
1588 dump_connect(node.connect);
1589 break;
1590 case FlowGraph::Node::Type::CELL_SYNC:
1591 dump_cell_sync(node.cell);
1592 break;
1593 case FlowGraph::Node::Type::CELL_EVAL:
1594 dump_cell_eval(node.cell);
1595 break;
1596 case FlowGraph::Node::Type::PROCESS:
1597 dump_process(node.process);
1598 break;
1599 }
1600 }
1601 }
1602 f << indent << "return converged;\n";
1603 dec_indent();
1604 }
1605
1606 void dump_commit_method(RTLIL::Module *module)
1607 {
1608 inc_indent();
1609 f << indent << "bool changed = false;\n";
1610 for (auto wire : module->wires()) {
1611 if (elided_wires.count(wire))
1612 continue;
1613 if (unbuffered_wires[wire]) {
1614 if (edge_wires[wire])
1615 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1616 continue;
1617 }
1618 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1619 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1620 }
1621 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1622 for (auto memory : module->memories) {
1623 if (!writable_memories[memory.second])
1624 continue;
1625 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1626 }
1627 for (auto cell : module->cells()) {
1628 if (is_internal_cell(cell->type))
1629 continue;
1630 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1631 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1632 }
1633 }
1634 f << indent << "return changed;\n";
1635 dec_indent();
1636 }
1637
1638 void dump_debug_info_method(RTLIL::Module *module)
1639 {
1640 size_t count_public_wires = 0;
1641 size_t count_const_wires = 0;
1642 size_t count_alias_wires = 0;
1643 size_t count_member_wires = 0;
1644 size_t count_skipped_wires = 0;
1645 size_t count_driven_sync = 0;
1646 size_t count_driven_comb = 0;
1647 size_t count_undriven = 0;
1648 size_t count_mixed_driver = 0;
1649 inc_indent();
1650 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1651 for (auto wire : module->wires()) {
1652 if (wire->name[0] != '\\')
1653 continue;
1654 if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
1655 continue;
1656 count_public_wires++;
1657 if (debug_const_wires.count(wire)) {
1658 // Wire tied to a constant
1659 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1660 dump_const(debug_const_wires[wire]);
1661 f << ";\n";
1662 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1663 f << ", debug_item(const_" << mangle(wire) << ", ";
1664 f << wire->start_offset << "));\n";
1665 count_const_wires++;
1666 } else if (debug_alias_wires.count(wire)) {
1667 // Alias of a member wire
1668 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1669 f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
1670 f << wire->start_offset << "));\n";
1671 count_alias_wires++;
1672 } else if (!localized_wires.count(wire)) {
1673 // Member wire
1674 std::vector<std::string> flags;
1675
1676 if (wire->port_input && wire->port_output)
1677 flags.push_back("INOUT");
1678 else if (wire->port_input)
1679 flags.push_back("INPUT");
1680 else if (wire->port_output)
1681 flags.push_back("OUTPUT");
1682
1683 bool has_driven_sync = false;
1684 bool has_driven_comb = false;
1685 bool has_undriven = false;
1686 SigSpec sig(wire);
1687 for (auto bit : sig.bits())
1688 if (!bit_has_state.count(bit))
1689 has_undriven = true;
1690 else if (bit_has_state[bit])
1691 has_driven_sync = true;
1692 else
1693 has_driven_comb = true;
1694 if (has_driven_sync)
1695 flags.push_back("DRIVEN_SYNC");
1696 if (has_driven_sync && !has_driven_comb && !has_undriven)
1697 count_driven_sync++;
1698 if (has_driven_comb)
1699 flags.push_back("DRIVEN_COMB");
1700 if (!has_driven_sync && has_driven_comb && !has_undriven)
1701 count_driven_comb++;
1702 if (has_undriven)
1703 flags.push_back("UNDRIVEN");
1704 if (!has_driven_sync && !has_driven_comb && has_undriven)
1705 count_undriven++;
1706 if (has_driven_sync + has_driven_comb + has_undriven > 1)
1707 count_mixed_driver++;
1708
1709 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1710 f << ", debug_item(" << mangle(wire) << ", ";
1711 f << wire->start_offset;
1712 bool first = true;
1713 for (auto flag : flags) {
1714 if (first) {
1715 first = false;
1716 f << ", ";
1717 } else {
1718 f << "|";
1719 }
1720 f << "debug_item::" << flag;
1721 }
1722 f << "));\n";
1723 count_member_wires++;
1724 } else {
1725 count_skipped_wires++;
1726 }
1727 }
1728 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1729 for (auto &memory_it : module->memories) {
1730 if (memory_it.first[0] != '\\')
1731 continue;
1732 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1733 f << ", debug_item(" << mangle(memory_it.second) << ", ";
1734 f << memory_it.second->start_offset << "));\n";
1735 }
1736 for (auto cell : module->cells()) {
1737 if (is_internal_cell(cell->type))
1738 continue;
1739 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1740 f << indent << mangle(cell) << access << "debug_info(items, ";
1741 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1742 }
1743 }
1744 dec_indent();
1745
1746 log_debug("Debug information statistics for module `%s':\n", log_id(module));
1747 log_debug(" Public wires: %zu, of which:\n", count_public_wires);
1748 log_debug(" Const wires: %zu\n", count_const_wires);
1749 log_debug(" Alias wires: %zu\n", count_alias_wires);
1750 log_debug(" Member wires: %zu, of which:\n", count_member_wires);
1751 log_debug(" Driven sync: %zu\n", count_driven_sync);
1752 log_debug(" Driven comb: %zu\n", count_driven_comb);
1753 log_debug(" Undriven: %zu\n", count_undriven);
1754 log_debug(" Mixed driver: %zu\n", count_mixed_driver);
1755 log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
1756 }
1757
1758 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1759 {
1760 if (metadata_map.empty()) {
1761 f << "metadata_map()";
1762 return;
1763 }
1764 f << "metadata_map({\n";
1765 inc_indent();
1766 for (auto metadata_item : metadata_map) {
1767 if (!metadata_item.first.begins_with("\\"))
1768 continue;
1769 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1770 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1771 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1772 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1773 f << escape_cxx_string(metadata_item.second.decode_string());
1774 } else {
1775 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1776 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1777 f << "u";
1778 }
1779 f << " },\n";
1780 }
1781 dec_indent();
1782 f << indent << "})";
1783 }
1784
1785 void dump_module_intf(RTLIL::Module *module)
1786 {
1787 dump_attrs(module);
1788 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1789 if (module->has_attribute(ID(cxxrtl_template)))
1790 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1791 f << indent << "struct " << mangle(module) << " : public module {\n";
1792 inc_indent();
1793 for (auto wire : module->wires()) {
1794 if (wire->port_id != 0)
1795 dump_wire(wire, /*is_local_context=*/false);
1796 }
1797 f << "\n";
1798 f << indent << "bool eval() override {\n";
1799 dump_eval_method(module);
1800 f << indent << "}\n";
1801 f << "\n";
1802 f << indent << "bool commit() override {\n";
1803 dump_commit_method(module);
1804 f << indent << "}\n";
1805 f << "\n";
1806 if (debug_info) {
1807 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1808 dump_debug_info_method(module);
1809 f << indent << "}\n";
1810 f << "\n";
1811 }
1812 f << indent << "static std::unique_ptr<" << mangle(module);
1813 f << template_params(module, /*is_decl=*/false) << "> ";
1814 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1815 dec_indent();
1816 f << indent << "}; // struct " << mangle(module) << "\n";
1817 f << "\n";
1818 if (blackbox_specializations.count(module)) {
1819 // If templated black boxes are used, the constructor of any module which includes the black box cell
1820 // (which calls the declared but not defined in the generated code `create` function) may only be used
1821 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1822 // a forward-declared explicit specialization.
1823 //
1824 // Option (b) makes it possible to have the generated code and the black box implementation in different
1825 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1826 // a specialization for every combination of parameters the generated code may use; but since the main
1827 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1828 // be very few such combinations anyway.
1829 for (auto specialization : blackbox_specializations[module]) {
1830 f << indent << "template<>\n";
1831 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1832 f << mangle(module) << specialization << "::";
1833 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1834 f << "\n";
1835 }
1836 }
1837 } else {
1838 f << indent << "struct " << mangle(module) << " : public module {\n";
1839 inc_indent();
1840 for (auto wire : module->wires())
1841 dump_wire(wire, /*is_local_context=*/false);
1842 f << "\n";
1843 bool has_memories = false;
1844 for (auto memory : module->memories) {
1845 dump_memory(module, memory.second);
1846 has_memories = true;
1847 }
1848 if (has_memories)
1849 f << "\n";
1850 bool has_cells = false;
1851 for (auto cell : module->cells()) {
1852 if (is_internal_cell(cell->type))
1853 continue;
1854 dump_attrs(cell);
1855 RTLIL::Module *cell_module = module->design->module(cell->type);
1856 log_assert(cell_module != nullptr);
1857 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1858 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1859 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1860 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1861 dump_metadata_map(cell->parameters);
1862 f << ", ";
1863 dump_metadata_map(cell->attributes);
1864 f << ");\n";
1865 } else {
1866 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1867 }
1868 has_cells = true;
1869 }
1870 if (has_cells)
1871 f << "\n";
1872 f << indent << "bool eval() override;\n";
1873 f << indent << "bool commit() override;\n";
1874 if (debug_info)
1875 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
1876 dec_indent();
1877 f << indent << "}; // struct " << mangle(module) << "\n";
1878 f << "\n";
1879 }
1880 }
1881
1882 void dump_module_impl(RTLIL::Module *module)
1883 {
1884 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1885 return;
1886 f << indent << "bool " << mangle(module) << "::eval() {\n";
1887 dump_eval_method(module);
1888 f << indent << "}\n";
1889 f << "\n";
1890 f << indent << "bool " << mangle(module) << "::commit() {\n";
1891 dump_commit_method(module);
1892 f << indent << "}\n";
1893 f << "\n";
1894 if (debug_info) {
1895 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
1896 dump_debug_info_method(module);
1897 f << indent << "}\n";
1898 f << "\n";
1899 }
1900 }
1901
1902 void dump_design(RTLIL::Design *design)
1903 {
1904 RTLIL::Module *top_module = nullptr;
1905 std::vector<RTLIL::Module*> modules;
1906 TopoSort<RTLIL::Module*> topo_design;
1907 for (auto module : design->modules()) {
1908 if (!design->selected_module(module))
1909 continue;
1910 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1911 modules.push_back(module); // cxxrtl blackboxes first
1912 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
1913 continue;
1914 if (module->get_bool_attribute(ID::top))
1915 top_module = module;
1916
1917 topo_design.node(module);
1918 for (auto cell : module->cells()) {
1919 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
1920 continue;
1921 RTLIL::Module *cell_module = design->module(cell->type);
1922 log_assert(cell_module != nullptr);
1923 topo_design.edge(cell_module, module);
1924 }
1925 }
1926 bool no_loops = topo_design.sort();
1927 log_assert(no_loops);
1928 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
1929
1930 if (split_intf) {
1931 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
1932 std::string include_guard = design_ns + "_header";
1933 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
1934
1935 f << "#ifndef " << include_guard << "\n";
1936 f << "#define " << include_guard << "\n";
1937 f << "\n";
1938 if (top_module != nullptr && debug_info) {
1939 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
1940 f << "\n";
1941 f << "#ifdef __cplusplus\n";
1942 f << "extern \"C\" {\n";
1943 f << "#endif\n";
1944 f << "\n";
1945 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
1946 f << "\n";
1947 f << "#ifdef __cplusplus\n";
1948 f << "}\n";
1949 f << "#endif\n";
1950 f << "\n";
1951 } else {
1952 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
1953 f << "\n";
1954 }
1955 f << "#ifdef __cplusplus\n";
1956 f << "\n";
1957 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1958 f << "\n";
1959 f << "using namespace cxxrtl;\n";
1960 f << "\n";
1961 f << "namespace " << design_ns << " {\n";
1962 f << "\n";
1963 for (auto module : modules)
1964 dump_module_intf(module);
1965 f << "} // namespace " << design_ns << "\n";
1966 f << "\n";
1967 f << "#endif // __cplusplus\n";
1968 f << "\n";
1969 f << "#endif\n";
1970 *intf_f << f.str(); f.str("");
1971 }
1972
1973 if (split_intf)
1974 f << "#include \"" << intf_filename << "\"\n";
1975 else
1976 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1977 f << "\n";
1978 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
1979 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1980 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
1981 f << "#endif\n";
1982 f << "\n";
1983 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1984 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
1985 f << "#endif\n";
1986 f << "\n";
1987 f << "using namespace cxxrtl_yosys;\n";
1988 f << "\n";
1989 f << "namespace " << design_ns << " {\n";
1990 f << "\n";
1991 for (auto module : modules) {
1992 if (!split_intf)
1993 dump_module_intf(module);
1994 dump_module_impl(module);
1995 }
1996 f << "} // namespace " << design_ns << "\n";
1997 f << "\n";
1998 if (top_module != nullptr && debug_info) {
1999 f << "extern \"C\"\n";
2000 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
2001 inc_indent();
2002 std::string top_type = design_ns + "::" + mangle(top_module);
2003 f << indent << "return new _cxxrtl_toplevel { ";
2004 f << "std::unique_ptr<" << top_type << ">(new " + top_type + ")";
2005 f << " };\n";
2006 dec_indent();
2007 f << "}\n";
2008 }
2009
2010 *impl_f << f.str(); f.str("");
2011 }
2012
2013 // Edge-type sync rules require us to emit edge detectors, which require coordination between
2014 // eval and commit phases. To do this we need to collect them upfront.
2015 //
2016 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
2017 // operate at wire bit granularity; it is possible to have code similar to:
2018 // wire [3:0] clocks;
2019 // always @(posedge clocks[0]) ...
2020 // To handle this we track edge sensitivity both for wires and wire bits.
2021 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
2022 {
2023 signal = sigmap(signal);
2024 log_assert(signal.is_wire() && signal.is_bit());
2025 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
2026
2027 RTLIL::SigBit sigbit = signal[0];
2028 if (!edge_types.count(sigbit))
2029 edge_types[sigbit] = type;
2030 else if (edge_types[sigbit] != type)
2031 edge_types[sigbit] = RTLIL::STe;
2032 edge_wires.insert(signal.as_wire());
2033 }
2034
2035 void analyze_design(RTLIL::Design *design)
2036 {
2037 bool has_feedback_arcs = false;
2038 bool has_buffered_comb_wires = false;
2039
2040 for (auto module : design->modules()) {
2041 if (!design->selected_module(module))
2042 continue;
2043
2044 SigMap &sigmap = sigmaps[module];
2045 sigmap.set(module);
2046
2047 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
2048 for (auto port : module->ports) {
2049 RTLIL::Wire *wire = module->wire(port);
2050 if (wire->port_input && !wire->port_output)
2051 unbuffered_wires.insert(wire);
2052 if (wire->has_attribute(ID(cxxrtl_edge))) {
2053 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
2054 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
2055 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
2056 log_id(module), log_signal(wire));
2057
2058 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
2059 for (int i = 0; i < GetSize(wire); i++) {
2060 RTLIL::SigSpec wire_sig = wire;
2061 switch (edges[i]) {
2062 case '-': break;
2063 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
2064 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
2065 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
2066 default:
2067 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
2068 "other than '-', 'p', 'n', or 'a'.\n",
2069 log_id(module), log_signal(wire));
2070 }
2071 }
2072 }
2073 }
2074
2075 // Black boxes converge by default, since their implementations are quite unlikely to require
2076 // internal propagation of comb signals.
2077 eval_converges[module] = true;
2078 continue;
2079 }
2080
2081 FlowGraph flow;
2082
2083 for (auto conn : module->connections())
2084 flow.add_node(conn);
2085
2086 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
2087 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
2088 pool<const RTLIL::Cell*>> memwr_per_domain;
2089 for (auto cell : module->cells()) {
2090 if (!cell->known())
2091 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2092
2093 RTLIL::Module *cell_module = design->module(cell->type);
2094 if (cell_module &&
2095 cell_module->get_blackbox_attribute() &&
2096 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2097 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2098
2099 if (cell_module &&
2100 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2101 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2102 blackbox_specializations[cell_module].insert(template_args(cell));
2103
2104 FlowGraph::Node *node = flow.add_node(cell);
2105
2106 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2107 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
2108 if (cell->getPort(ID::CLK).is_wire())
2109 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2110 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2111 }
2112 // Similar for memory port cells.
2113 if (cell->type.in(ID($memrd), ID($memwr))) {
2114 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2115 if (cell->getPort(ID::CLK).is_wire())
2116 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2117 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2118 }
2119 memrw_cell_nodes[cell] = node;
2120 }
2121 // Optimize access to read-only memories.
2122 if (cell->type == ID($memwr))
2123 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2124 // Collect groups of memory write ports in the same domain.
2125 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2126 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2127 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2128 memwr_per_domain[{clk_bit, memory}].insert(cell);
2129 }
2130 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2131 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2132 if (cell->type.in(ID($mem)))
2133 log_assert(false);
2134 }
2135 for (auto cell : module->cells()) {
2136 // Collect groups of memory write ports read by every transparent read port.
2137 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2138 cell->getParam(ID::TRANSPARENT).as_bool()) {
2139 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2140 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2141 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2142 transparent_for[cell].insert(memwr_cell);
2143 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2144 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2145 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2146 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2147 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2148 }
2149 }
2150 }
2151
2152 for (auto proc : module->processes) {
2153 flow.add_node(proc.second);
2154
2155 for (auto sync : proc.second->syncs)
2156 switch (sync->type) {
2157 // Edge-type sync rules require pre-registration.
2158 case RTLIL::STp:
2159 case RTLIL::STn:
2160 case RTLIL::STe:
2161 register_edge_signal(sigmap, sync->signal, sync->type);
2162 break;
2163
2164 // Level-type sync rules require no special handling.
2165 case RTLIL::ST0:
2166 case RTLIL::ST1:
2167 case RTLIL::STa:
2168 break;
2169
2170 case RTLIL::STg:
2171 log_cmd_error("Global clock is not supported.\n");
2172
2173 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2174 // attribute regardless of input.
2175 case RTLIL::STi:
2176 log_assert(false);
2177 }
2178 }
2179
2180 for (auto wire : module->wires()) {
2181 if (!flow.is_elidable(wire)) continue;
2182 if (wire->port_id != 0) continue;
2183 if (wire->get_bool_attribute(ID::keep)) continue;
2184 if (wire->name.begins_with("$") && !elide_internal) continue;
2185 if (wire->name.begins_with("\\") && !elide_public) continue;
2186 if (edge_wires[wire]) continue;
2187 if (flow.wire_comb_defs[wire].size() > 1)
2188 log_cmd_error("Wire %s.%s has multiple drivers.\n", log_id(module), log_id(wire));
2189 log_assert(flow.wire_comb_defs[wire].size() == 1);
2190 elided_wires[wire] = **flow.wire_comb_defs[wire].begin();
2191 }
2192
2193 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2194 for (auto wire_comb_def : flow.wire_comb_defs)
2195 for (auto node : wire_comb_def.second)
2196 node_defs[node].insert(wire_comb_def.first);
2197
2198 Scheduler<FlowGraph::Node> scheduler;
2199 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2200 for (auto node : flow.nodes)
2201 node_map[node] = scheduler.add(node);
2202 for (auto node_def : node_defs) {
2203 auto vertex = node_map[node_def.first];
2204 for (auto wire : node_def.second)
2205 for (auto succ_node : flow.wire_uses[wire]) {
2206 auto succ_vertex = node_map[succ_node];
2207 vertex->succs.insert(succ_vertex);
2208 succ_vertex->preds.insert(vertex);
2209 }
2210 }
2211
2212 auto eval_order = scheduler.schedule();
2213 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2214 pool<const RTLIL::Wire*> feedback_wires;
2215 for (auto vertex : eval_order) {
2216 auto node = vertex->data;
2217 schedule[module].push_back(*node);
2218 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2219 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2220 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2221 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2222 evaluated.insert(node);
2223 for (auto wire : node_defs[node])
2224 for (auto succ_node : flow.wire_uses[wire])
2225 if (evaluated[succ_node]) {
2226 feedback_wires.insert(wire);
2227 // Feedback wires may never be elided because feedback requires state, but the point of elision
2228 // (and localization) is to eliminate state.
2229 elided_wires.erase(wire);
2230 }
2231 }
2232
2233 if (!feedback_wires.empty()) {
2234 has_feedback_arcs = true;
2235 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2236 for (auto wire : feedback_wires)
2237 log(" %s\n", log_id(wire));
2238 }
2239
2240 for (auto wire : module->wires()) {
2241 if (feedback_wires[wire]) continue;
2242 if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
2243 if (wire->name.begins_with("$") && !unbuffer_internal) continue;
2244 if (wire->name.begins_with("\\") && !unbuffer_public) continue;
2245 if (flow.wire_sync_defs.count(wire) > 0) continue;
2246 unbuffered_wires.insert(wire);
2247 if (edge_wires[wire]) continue;
2248 if (wire->get_bool_attribute(ID::keep)) continue;
2249 if (wire->port_input || wire->port_output) continue;
2250 if (wire->name.begins_with("$") && !localize_internal) continue;
2251 if (wire->name.begins_with("\\") && !localize_public) continue;
2252 localized_wires.insert(wire);
2253 }
2254
2255 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2256 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2257 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2258 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2259 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2260 // also require more than one delta cycle to converge.
2261 pool<const RTLIL::Wire*> buffered_comb_wires;
2262 for (auto wire : module->wires()) {
2263 if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
2264 buffered_comb_wires.insert(wire);
2265 }
2266 if (!buffered_comb_wires.empty()) {
2267 has_buffered_comb_wires = true;
2268 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2269 for (auto wire : buffered_comb_wires)
2270 log(" %s\n", log_id(wire));
2271 }
2272
2273 eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
2274
2275 for (auto item : flow.bit_has_state)
2276 bit_has_state.insert(item);
2277
2278 if (debug_info) {
2279 // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
2280 // at essentially zero additional cost.
2281 //
2282 // Note that the information collected here can't be used for optimizing the netlist: debug information queries
2283 // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
2284 for (auto wire : module->wires()) {
2285 if (wire->name[0] != '\\')
2286 continue;
2287 if (!unbuffered_wires[wire])
2288 continue;
2289 const RTLIL::Wire *wire_it = wire;
2290 while (1) {
2291 if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it]))
2292 break; // not an alias: complex def
2293 log_assert(flow.wire_comb_defs[wire_it].size() == 1);
2294 FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin();
2295 if (node->type != FlowGraph::Node::Type::CONNECT)
2296 break; // not an alias: def by cell
2297 RTLIL::SigSpec rhs_sig = node->connect.second;
2298 if (rhs_sig.is_wire()) {
2299 RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
2300 if (unbuffered_wires[rhs_wire]) {
2301 wire_it = rhs_wire; // maybe an alias
2302 } else {
2303 debug_alias_wires[wire] = rhs_wire; // is an alias
2304 break;
2305 }
2306 } else if (rhs_sig.is_fully_const()) {
2307 debug_const_wires[wire] = rhs_sig.as_const(); // is a const
2308 break;
2309 } else {
2310 break; // not an alias: complex rhs
2311 }
2312 }
2313 }
2314 }
2315 }
2316 if (has_feedback_arcs || has_buffered_comb_wires) {
2317 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2318 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2319 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2320 const char *why_pessimistic = nullptr;
2321 if (has_feedback_arcs)
2322 why_pessimistic = "feedback wires";
2323 else if (has_buffered_comb_wires)
2324 why_pessimistic = "buffered combinatorial wires";
2325 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2326 if (!run_flatten)
2327 log("Flattening may eliminate %s from the design.\n", why_pessimistic);
2328 if (!run_proc)
2329 log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic);
2330 }
2331 }
2332
2333 void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init, bool &has_packed_mem)
2334 {
2335 has_sync_init = has_packed_mem = has_top = false;
2336
2337 for (auto module : design->modules()) {
2338 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2339 continue;
2340
2341 if (!design->selected_whole_module(module))
2342 if (design->selected_module(module))
2343 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2344 if (!design->selected_module(module))
2345 continue;
2346
2347 if (module->get_bool_attribute(ID::top))
2348 has_top = true;
2349
2350 for (auto proc : module->processes)
2351 for (auto sync : proc.second->syncs)
2352 if (sync->type == RTLIL::STi)
2353 has_sync_init = true;
2354
2355 // The Mem constructor also checks for well-formedness of $meminit cells, if any.
2356 for (auto &mem : Mem::get_all_memories(module))
2357 if (mem.packed)
2358 has_packed_mem = true;
2359 }
2360 }
2361
2362 void prepare_design(RTLIL::Design *design)
2363 {
2364 bool did_anything = false;
2365 bool has_top, has_sync_init, has_packed_mem;
2366 log_push();
2367 check_design(design, has_top, has_sync_init, has_packed_mem);
2368 if (run_hierarchy && !has_top) {
2369 Pass::call(design, "hierarchy -auto-top");
2370 did_anything = true;
2371 }
2372 if (run_flatten) {
2373 Pass::call(design, "flatten");
2374 did_anything = true;
2375 }
2376 if (run_proc) {
2377 Pass::call(design, "proc");
2378 did_anything = true;
2379 } else if (has_sync_init) {
2380 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2381 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2382 Pass::call(design, "proc_prune");
2383 Pass::call(design, "proc_clean");
2384 Pass::call(design, "proc_init");
2385 did_anything = true;
2386 }
2387 if (has_packed_mem) {
2388 Pass::call(design, "memory_unpack");
2389 did_anything = true;
2390 }
2391 // Recheck the design if it was modified.
2392 if (did_anything)
2393 check_design(design, has_top, has_sync_init, has_packed_mem);
2394 log_assert(has_top && !has_sync_init && !has_packed_mem);
2395 log_pop();
2396 if (did_anything)
2397 log_spacer();
2398 analyze_design(design);
2399 }
2400 };
2401
2402 struct CxxrtlBackend : public Backend {
2403 static const int DEFAULT_OPT_LEVEL = 6;
2404 static const int OPT_LEVEL_DEBUG = 4;
2405 static const int DEFAULT_DEBUG_LEVEL = 1;
2406
2407 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2408 void help() override
2409 {
2410 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2411 log("\n");
2412 log(" write_cxxrtl [options] [filename]\n");
2413 log("\n");
2414 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2415 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2416 log("\n");
2417 log("The following driver may be used as an example for a design with a single clock\n");
2418 log("driving rising edge triggered flip-flops:\n");
2419 log("\n");
2420 log(" #include \"top.cc\"\n");
2421 log("\n");
2422 log(" int main() {\n");
2423 log(" cxxrtl_design::p_top top;\n");
2424 log(" top.step();\n");
2425 log(" while (1) {\n");
2426 log(" /* user logic */\n");
2427 log(" top.p_clk.set(false);\n");
2428 log(" top.step();\n");
2429 log(" top.p_clk.set(true);\n");
2430 log(" top.step();\n");
2431 log(" }\n");
2432 log(" }\n");
2433 log("\n");
2434 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2435 log("subject to race conditions. If, in the example above, the user logic would run\n");
2436 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2437 log("\n");
2438 log("This backend supports replacing parts of the design with black boxes implemented\n");
2439 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2440 log("and the generated code consists only of an interface and a factory function.\n");
2441 log("The driver must implement the factory function that creates an implementation of\n");
2442 log("the black box, taking into account the parameters it is instantiated with.\n");
2443 log("\n");
2444 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2445 log("a synchronous debug sink:\n");
2446 log("\n");
2447 log(" (* cxxrtl_blackbox *)\n");
2448 log(" module debug(...);\n");
2449 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2450 log(" input en;\n");
2451 log(" input [7:0] i_data;\n");
2452 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2453 log(" endmodule\n");
2454 log("\n");
2455 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2456 log("\n");
2457 log(" struct bb_p_debug : public module {\n");
2458 log(" value<1> p_clk;\n");
2459 log(" bool posedge_p_clk() const { /* ... */ }\n");
2460 log(" value<1> p_en;\n");
2461 log(" value<8> p_i_data;\n");
2462 log(" wire<8> p_o_data;\n");
2463 log("\n");
2464 log(" bool eval() override;\n");
2465 log(" bool commit() override;\n");
2466 log("\n");
2467 log(" static std::unique_ptr<bb_p_debug>\n");
2468 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2469 log(" };\n");
2470 log("\n");
2471 log("The `create' function must be implemented by the driver. For example, it could\n");
2472 log("always provide an implementation logging the values to standard error stream:\n");
2473 log("\n");
2474 log(" namespace cxxrtl_design {\n");
2475 log("\n");
2476 log(" struct stderr_debug : public bb_p_debug {\n");
2477 log(" bool eval() override {\n");
2478 log(" if (posedge_p_clk() && p_en)\n");
2479 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2480 log(" p_o_data.next = p_i_data;\n");
2481 log(" return bb_p_debug::eval();\n");
2482 log(" }\n");
2483 log(" };\n");
2484 log("\n");
2485 log(" std::unique_ptr<bb_p_debug>\n");
2486 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2487 log(" cxxrtl::metadata_map attributes) {\n");
2488 log(" return std::make_unique<stderr_debug>();\n");
2489 log(" }\n");
2490 log("\n");
2491 log(" }\n");
2492 log("\n");
2493 log("For complex applications of black boxes, it is possible to parameterize their\n");
2494 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2495 log("interface for a configurable width debug sink:\n");
2496 log("\n");
2497 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2498 log(" module debug(...);\n");
2499 log(" parameter WIDTH = 8;\n");
2500 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2501 log(" input en;\n");
2502 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2503 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2504 log(" endmodule\n");
2505 log("\n");
2506 log("For this parametric HDL interface, this backend will generate the following C++\n");
2507 log("interface (only the differences are shown):\n");
2508 log("\n");
2509 log(" template<size_t WIDTH>\n");
2510 log(" struct bb_p_debug : public module {\n");
2511 log(" // ...\n");
2512 log(" value<WIDTH> p_i_data;\n");
2513 log(" wire<WIDTH> p_o_data;\n");
2514 log(" // ...\n");
2515 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2516 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2517 log(" };\n");
2518 log("\n");
2519 log("The `create' function must be implemented by the driver, specialized for every\n");
2520 log("possible combination of template parameters. (Specialization is necessary to\n");
2521 log("enable separate compilation of generated code and black box implementations.)\n");
2522 log("\n");
2523 log(" template<size_t SIZE>\n");
2524 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2525 log(" // ...\n");
2526 log(" };\n");
2527 log("\n");
2528 log(" template<>\n");
2529 log(" std::unique_ptr<bb_p_debug<8>>\n");
2530 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2531 log(" cxxrtl::metadata_map attributes) {\n");
2532 log(" return std::make_unique<stderr_debug<8>>();\n");
2533 log(" }\n");
2534 log("\n");
2535 log("The following attributes are recognized by this backend:\n");
2536 log("\n");
2537 log(" cxxrtl_blackbox\n");
2538 log(" only valid on modules. if specified, the module contents are ignored,\n");
2539 log(" and the generated code includes only the module interface and a factory\n");
2540 log(" function, which will be called to instantiate the module.\n");
2541 log("\n");
2542 log(" cxxrtl_edge\n");
2543 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2544 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2545 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2546 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2547 log("\n");
2548 log(" cxxrtl_template\n");
2549 log(" only valid on black boxes. must contain a space separated sequence of\n");
2550 log(" identifiers that have a corresponding black box parameters. for each\n");
2551 log(" of them, the generated code includes a `size_t` template parameter.\n");
2552 log("\n");
2553 log(" cxxrtl_width\n");
2554 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2555 log(" is directly inserted into generated code.\n");
2556 log("\n");
2557 log(" cxxrtl_comb, cxxrtl_sync\n");
2558 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2559 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2560 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2561 log(" if neither is specified, the output will be pessimistically treated as\n");
2562 log(" driven by both combinatorial and synchronous logic.\n");
2563 log("\n");
2564 log("The following options are supported by this backend:\n");
2565 log("\n");
2566 log(" -header\n");
2567 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2568 log(" if specified, the backend must be called with a filename, and filename\n");
2569 log(" of the interface is derived from filename of the implementation.\n");
2570 log(" otherwise, interface and implementation are generated together.\n");
2571 log("\n");
2572 log(" -namespace <ns-name>\n");
2573 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2574 log(" \"cxxrtl_design\" is used.\n");
2575 log("\n");
2576 log(" -nohierarchy\n");
2577 log(" use design hierarchy as-is. in most designs, a top module should be\n");
2578 log(" present as it is exposed through the C API and has unbuffered outputs\n");
2579 log(" for improved performance; it will be determined automatically if absent.\n");
2580 log("\n");
2581 log(" -noflatten\n");
2582 log(" don't flatten the design. fully flattened designs can evaluate within\n");
2583 log(" one delta cycle if they have no combinatorial feedback.\n");
2584 log(" note that the debug interface and waveform dumps use full hierarchical\n");
2585 log(" names for all wires even in flattened designs.\n");
2586 log("\n");
2587 log(" -noproc\n");
2588 log(" don't convert processes to netlists. in most designs, converting\n");
2589 log(" processes significantly improves evaluation performance at the cost of\n");
2590 log(" slight increase in compilation time.\n");
2591 log("\n");
2592 log(" -O <level>\n");
2593 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2594 log(" levels dramatically decrease compile and run time, and highest level\n");
2595 log(" possible for a design should be used.\n");
2596 log("\n");
2597 log(" -O0\n");
2598 log(" no optimization.\n");
2599 log("\n");
2600 log(" -O1\n");
2601 log(" localize internal wires if possible.\n");
2602 log("\n");
2603 log(" -O2\n");
2604 log(" like -O1, and unbuffer internal wires if possible.\n");
2605 log("\n");
2606 log(" -O3\n");
2607 log(" like -O2, and elide internal wires if possible.\n");
2608 log("\n");
2609 log(" -O4\n");
2610 log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
2611 log("\n");
2612 log(" -O5\n");
2613 log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
2614 log("\n");
2615 log(" -O6\n");
2616 log(" like -O5, and elide public wires not marked (*keep*) if possible.\n");
2617 log("\n");
2618 log(" -Og\n");
2619 log(" highest optimization level that provides debug information for all\n");
2620 log(" public wires. currently, alias for -O%d.\n", OPT_LEVEL_DEBUG);
2621 log("\n");
2622 log(" -g <level>\n");
2623 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2624 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2625 log("\n");
2626 log(" -g0\n");
2627 log(" no debug information.\n");
2628 log("\n");
2629 log(" -g1\n");
2630 log(" debug information for non-optimized public wires. this also makes it\n");
2631 log(" possible to use the C API.\n");
2632 log("\n");
2633 }
2634
2635 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
2636 {
2637 bool nohierarchy = false;
2638 bool noflatten = false;
2639 bool noproc = false;
2640 int opt_level = DEFAULT_OPT_LEVEL;
2641 int debug_level = DEFAULT_DEBUG_LEVEL;
2642 CxxrtlWorker worker;
2643
2644 log_header(design, "Executing CXXRTL backend.\n");
2645
2646 size_t argidx;
2647 for (argidx = 1; argidx < args.size(); argidx++)
2648 {
2649 if (args[argidx] == "-nohierarchy") {
2650 nohierarchy = true;
2651 continue;
2652 }
2653 if (args[argidx] == "-noflatten") {
2654 noflatten = true;
2655 continue;
2656 }
2657 if (args[argidx] == "-noproc") {
2658 noproc = true;
2659 continue;
2660 }
2661 if (args[argidx] == "-Og") {
2662 opt_level = OPT_LEVEL_DEBUG;
2663 continue;
2664 }
2665 if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
2666 argidx++;
2667 opt_level = OPT_LEVEL_DEBUG;
2668 continue;
2669 }
2670 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2671 opt_level = std::stoi(args[++argidx]);
2672 continue;
2673 }
2674 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2675 opt_level = std::stoi(args[argidx].substr(2));
2676 continue;
2677 }
2678 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2679 debug_level = std::stoi(args[++argidx]);
2680 continue;
2681 }
2682 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2683 debug_level = std::stoi(args[argidx].substr(2));
2684 continue;
2685 }
2686 if (args[argidx] == "-header") {
2687 worker.split_intf = true;
2688 continue;
2689 }
2690 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2691 worker.design_ns = args[++argidx];
2692 continue;
2693 }
2694 break;
2695 }
2696 extra_args(f, filename, args, argidx);
2697
2698 worker.run_hierarchy = !nohierarchy;
2699 worker.run_flatten = !noflatten;
2700 worker.run_proc = !noproc;
2701 switch (opt_level) {
2702 // the highest level here must match DEFAULT_OPT_LEVEL
2703 case 6:
2704 worker.elide_public = true;
2705 YS_FALLTHROUGH
2706 case 5:
2707 worker.localize_public = true;
2708 YS_FALLTHROUGH
2709 case 4:
2710 worker.unbuffer_public = true;
2711 YS_FALLTHROUGH
2712 case 3:
2713 worker.elide_internal = true;
2714 YS_FALLTHROUGH
2715 case 2:
2716 worker.localize_internal = true;
2717 YS_FALLTHROUGH
2718 case 1:
2719 worker.unbuffer_internal = true;
2720 YS_FALLTHROUGH
2721 case 0:
2722 break;
2723 default:
2724 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2725 }
2726 switch (debug_level) {
2727 // the highest level here must match DEFAULT_DEBUG_LEVEL
2728 case 1:
2729 worker.debug_info = true;
2730 YS_FALLTHROUGH
2731 case 0:
2732 break;
2733 default:
2734 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2735 }
2736
2737 std::ofstream intf_f;
2738 if (worker.split_intf) {
2739 if (filename == "<stdout>")
2740 log_cmd_error("Option -header must be used with a filename.\n");
2741
2742 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2743 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2744 if (intf_f.fail())
2745 log_cmd_error("Can't open file `%s' for writing: %s\n",
2746 worker.intf_filename.c_str(), strerror(errno));
2747
2748 worker.intf_f = &intf_f;
2749 }
2750 worker.impl_f = f;
2751
2752 worker.prepare_design(design);
2753 worker.dump_design(design);
2754 }
2755 } CxxrtlBackend;
2756
2757 PRIVATE_NAMESPACE_END