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Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/log.h"
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 // [[CITE]]
31 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
32 // Information Processing Letters, Vol. 47, pp 319-323, 1993
33 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
34
35 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
36 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
37 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
38 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
39 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
40 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
41 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
42 template<class T>
43 struct Scheduler {
44 struct Vertex {
45 T *data;
46 Vertex *prev, *next;
47 pool<Vertex*, hash_ptr_ops> preds, succs;
48
49 Vertex() : data(NULL), prev(this), next(this) {}
50 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
51
52 bool empty() const
53 {
54 log_assert(data == NULL);
55 if (next == this) {
56 log_assert(prev == next);
57 return true;
58 }
59 return false;
60 }
61
62 void link(Vertex *list)
63 {
64 log_assert(prev == NULL && next == NULL);
65 next = list;
66 prev = list->prev;
67 list->prev->next = this;
68 list->prev = this;
69 }
70
71 void unlink()
72 {
73 log_assert(prev->next == this && next->prev == this);
74 prev->next = next;
75 next->prev = prev;
76 next = prev = NULL;
77 }
78
79 int delta() const
80 {
81 return succs.size() - preds.size();
82 }
83 };
84
85 std::vector<Vertex*> vertices;
86 Vertex *sources = new Vertex;
87 Vertex *sinks = new Vertex;
88 dict<int, Vertex*> bins;
89
90 ~Scheduler()
91 {
92 delete sources;
93 delete sinks;
94 for (auto bin : bins)
95 delete bin.second;
96 for (auto vertex : vertices)
97 delete vertex;
98 }
99
100 Vertex *add(T *data)
101 {
102 Vertex *vertex = new Vertex(data);
103 vertices.push_back(vertex);
104 return vertex;
105 }
106
107 void relink(Vertex *vertex)
108 {
109 if (vertex->succs.empty())
110 vertex->link(sinks);
111 else if (vertex->preds.empty())
112 vertex->link(sources);
113 else {
114 int delta = vertex->delta();
115 if (!bins.count(delta))
116 bins[delta] = new Vertex;
117 vertex->link(bins[delta]);
118 }
119 }
120
121 Vertex *remove(Vertex *vertex)
122 {
123 vertex->unlink();
124 for (auto pred : vertex->preds) {
125 if (pred == vertex)
126 continue;
127 log_assert(pred->succs[vertex]);
128 pred->unlink();
129 pred->succs.erase(vertex);
130 relink(pred);
131 }
132 for (auto succ : vertex->succs) {
133 if (succ == vertex)
134 continue;
135 log_assert(succ->preds[vertex]);
136 succ->unlink();
137 succ->preds.erase(vertex);
138 relink(succ);
139 }
140 vertex->preds.clear();
141 vertex->succs.clear();
142 return vertex;
143 }
144
145 std::vector<Vertex*> schedule()
146 {
147 std::vector<Vertex*> s1, s2r;
148 for (auto vertex : vertices)
149 relink(vertex);
150 bool bins_empty = false;
151 while (!(sinks->empty() && sources->empty() && bins_empty)) {
152 while (!sinks->empty())
153 s2r.push_back(remove(sinks->next));
154 while (!sources->empty())
155 s1.push_back(remove(sources->next));
156 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
157 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
158 // naive implementation of find-max-key.
159 bins_empty = true;
160 bins.template sort<std::greater<int>>();
161 for (auto bin : bins) {
162 if (!bin.second->empty()) {
163 bins_empty = false;
164 s1.push_back(remove(bin.second->next));
165 break;
166 }
167 }
168 }
169 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
170 return s1;
171 }
172 };
173
174 bool is_input_wire(const RTLIL::Wire *wire)
175 {
176 return wire->port_input && !wire->port_output;
177 }
178
179 bool is_unary_cell(RTLIL::IdString type)
180 {
181 return type.in(
182 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
183 ID($pos), ID($neg));
184 }
185
186 bool is_binary_cell(RTLIL::IdString type)
187 {
188 return type.in(
189 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
190 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
191 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
192 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
193 }
194
195 bool is_extending_cell(RTLIL::IdString type)
196 {
197 return !type.in(
198 ID($logic_not), ID($logic_and), ID($logic_or),
199 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
200 }
201
202 bool is_elidable_cell(RTLIL::IdString type)
203 {
204 return is_unary_cell(type) || is_binary_cell(type) || type.in(
205 ID($mux), ID($concat), ID($slice));
206 }
207
208 bool is_sync_ff_cell(RTLIL::IdString type)
209 {
210 return type.in(
211 ID($dff), ID($dffe));
212 }
213
214 bool is_ff_cell(RTLIL::IdString type)
215 {
216 return is_sync_ff_cell(type) || type.in(
217 ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
218 }
219
220 bool is_internal_cell(RTLIL::IdString type)
221 {
222 return type[0] == '$' && !type.begins_with("$paramod");
223 }
224
225 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
226 {
227 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
228 log_assert(cell_module != nullptr);
229 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
230 }
231
232 enum class CxxrtlPortType {
233 UNKNOWN = 0, // or mixed comb/sync
234 COMB = 1,
235 SYNC = 2,
236 };
237
238 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
239 {
240 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
241 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
242 return CxxrtlPortType::UNKNOWN;
243 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
244 log_assert(cell_output_wire != nullptr);
245 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
246 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
247 if (is_comb && is_sync)
248 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
249 log_id(cell_module), log_signal(cell_output_wire));
250 else if (is_comb)
251 return CxxrtlPortType::COMB;
252 else if (is_sync)
253 return CxxrtlPortType::SYNC;
254 return CxxrtlPortType::UNKNOWN;
255 }
256
257 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
258 {
259 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
260 }
261
262 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
263 {
264 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
265 }
266
267 struct FlowGraph {
268 struct Node {
269 enum class Type {
270 CONNECT,
271 CELL_SYNC,
272 CELL_EVAL,
273 PROCESS
274 };
275
276 Type type;
277 RTLIL::SigSig connect = {};
278 const RTLIL::Cell *cell = NULL;
279 const RTLIL::Process *process = NULL;
280 };
281
282 std::vector<Node*> nodes;
283 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
284 dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
285
286 ~FlowGraph()
287 {
288 for (auto node : nodes)
289 delete node;
290 }
291
292 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool fully_sync, bool elidable)
293 {
294 for (auto chunk : sig.chunks())
295 if (chunk.wire) {
296 if (fully_sync)
297 wire_sync_defs[chunk.wire].insert(node);
298 else
299 wire_comb_defs[chunk.wire].insert(node);
300 }
301 // Only comb defs of an entire wire in the right order can be elided.
302 if (!fully_sync && sig.is_wire())
303 wire_def_elidable[sig.as_wire()] = elidable;
304 }
305
306 void add_uses(Node *node, const RTLIL::SigSpec &sig)
307 {
308 for (auto chunk : sig.chunks())
309 if (chunk.wire) {
310 wire_uses[chunk.wire].insert(node);
311 // Only a single use of an entire wire in the right order can be elided.
312 // (But the use can include other chunks.)
313 if (!wire_use_elidable.count(chunk.wire))
314 wire_use_elidable[chunk.wire] = true;
315 else
316 wire_use_elidable[chunk.wire] = false;
317 }
318 }
319
320 bool is_elidable(const RTLIL::Wire *wire) const
321 {
322 if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire))
323 return wire_def_elidable.at(wire) && wire_use_elidable.at(wire);
324 return false;
325 }
326
327 // Connections
328 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
329 {
330 add_defs(node, conn.first, /*fully_sync=*/false, /*elidable=*/true);
331 add_uses(node, conn.second);
332 }
333
334 Node *add_node(const RTLIL::SigSig &conn)
335 {
336 Node *node = new Node;
337 node->type = Node::Type::CONNECT;
338 node->connect = conn;
339 nodes.push_back(node);
340 add_connect_defs_uses(node, conn);
341 return node;
342 }
343
344 // Cells
345 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
346 {
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
352 //
353 // wire<1> i_tmp;
354 // cell->p_i = i_tmp.curr;
355 // cell->eval();
356 // i_tmp.next = cell->p_o.curr;
357 //
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
361 //
362 // value<1> i_tmp;
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
365 // cell->eval();
366 //
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn : cell->connections())
374 if (cell->output(conn.first))
375 if (is_cxxrtl_sync_port(cell, conn.first)) {
376 // See note regarding elidability below.
377 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
378 }
379 }
380
381 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
382 {
383 for (auto conn : cell->connections()) {
384 if (cell->output(conn.first)) {
385 if (is_elidable_cell(cell->type))
386 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/true);
387 else if (is_sync_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
388 add_defs(node, conn.second, /*fully_sync=*/true, /*elidable=*/false);
389 else if (is_internal_cell(cell->type))
390 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
391 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
392 // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
396 // the infrastructure required to elide outputs of cells with many of them.
397 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
398 }
399 }
400 if (cell->input(conn.first))
401 add_uses(node, conn.second);
402 }
403 }
404
405 Node *add_node(const RTLIL::Cell *cell)
406 {
407 log_assert(cell->known());
408
409 bool has_fully_sync_outputs = false;
410 for (auto conn : cell->connections())
411 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
412 has_fully_sync_outputs = true;
413 break;
414 }
415 if (has_fully_sync_outputs) {
416 Node *node = new Node;
417 node->type = Node::Type::CELL_SYNC;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_sync_defs(node, cell);
421 }
422
423 Node *node = new Node;
424 node->type = Node::Type::CELL_EVAL;
425 node->cell = cell;
426 nodes.push_back(node);
427 add_cell_eval_defs_uses(node, cell);
428 return node;
429 }
430
431 // Processes
432 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
433 {
434 for (auto &action : case_->actions) {
435 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
436 add_uses(node, action.second);
437 }
438 for (auto sub_switch : case_->switches) {
439 add_uses(node, sub_switch->signal);
440 for (auto sub_case : sub_switch->cases) {
441 for (auto &compare : sub_case->compare)
442 add_uses(node, compare);
443 add_case_defs_uses(node, sub_case);
444 }
445 }
446 }
447
448 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
449 {
450 add_case_defs_uses(node, &process->root_case);
451 for (auto sync : process->syncs)
452 for (auto action : sync->actions) {
453 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
454 add_defs(node, action.first, /*is_sync=*/true, /*elidable=*/false);
455 else
456 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
457 add_uses(node, action.second);
458 }
459 }
460
461 Node *add_node(const RTLIL::Process *process)
462 {
463 Node *node = new Node;
464 node->type = Node::Type::PROCESS;
465 node->process = process;
466 nodes.push_back(node);
467 add_process_defs_uses(node, process);
468 return node;
469 }
470 };
471
472 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
473 {
474 std::vector<std::string> result;
475 size_t prev = 0;
476 while (true) {
477 size_t curr = str.find_first_of(sep, prev + 1);
478 if (curr > str.size())
479 curr = str.size();
480 if (curr > prev + 1)
481 result.push_back(str.substr(prev, curr - prev));
482 if (curr == str.size())
483 break;
484 prev = curr;
485 }
486 return result;
487 }
488
489 std::string escape_cxx_string(const std::string &input)
490 {
491 std::string output = "\"";
492 for (auto c : input) {
493 if (::isprint(c)) {
494 if (c == '\\')
495 output.push_back('\\');
496 output.push_back(c);
497 } else {
498 char l = c & 0xf, h = (c >> 4) & 0xf;
499 output.append("\\x");
500 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
501 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
502 }
503 }
504 output.push_back('"');
505 if (output.find('\0') != std::string::npos) {
506 output.insert(0, "std::string {");
507 output.append(stringf(", %zu}", input.size()));
508 }
509 return output;
510 }
511
512 template<class T>
513 std::string get_hdl_name(T *object)
514 {
515 if (object->has_attribute(ID::hdlname))
516 return object->get_string_attribute(ID::hdlname);
517 else
518 return object->name.str().substr(1);
519 }
520
521 struct CxxrtlWorker {
522 bool split_intf = false;
523 std::string intf_filename;
524 std::string design_ns = "cxxrtl_design";
525 std::ostream *impl_f = nullptr;
526 std::ostream *intf_f = nullptr;
527
528 bool elide_internal = false;
529 bool elide_public = false;
530 bool localize_internal = false;
531 bool localize_public = false;
532 bool run_proc_flatten = false;
533 bool max_opt_level = false;
534
535 bool debug_info = false;
536
537 std::ostringstream f;
538 std::string indent;
539 int temporary = 0;
540
541 dict<const RTLIL::Module*, SigMap> sigmaps;
542 pool<const RTLIL::Wire*> edge_wires;
543 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
544 pool<const RTLIL::Memory*> writable_memories;
545 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
546 dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
547 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
548 pool<const RTLIL::Wire*> localized_wires;
549 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
550 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
551 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
552 dict<const RTLIL::Module*, bool> eval_converges;
553
554 void inc_indent() {
555 indent += "\t";
556 }
557 void dec_indent() {
558 indent.resize(indent.size() - 1);
559 }
560
561 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
562 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
563 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
564 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
565 // 1. All generated identifiers start with `_`.
566 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
567 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
568 // 2. An underscore is escaped with another underscore, i.e. `__`.
569 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
570 std::string mangle_name(const RTLIL::IdString &name)
571 {
572 std::string mangled;
573 bool first = true;
574 for (char c : name.str()) {
575 if (first) {
576 first = false;
577 if (c == '\\')
578 mangled += "p_";
579 else if (c == '$')
580 mangled += "i_";
581 else
582 log_assert(false);
583 } else {
584 if (isalnum(c)) {
585 mangled += c;
586 } else if (c == '_') {
587 mangled += "__";
588 } else {
589 char l = c & 0xf, h = (c >> 4) & 0xf;
590 mangled += '_';
591 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
592 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
593 mangled += '_';
594 }
595 }
596 }
597 return mangled;
598 }
599
600 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
601 {
602 // Class namespace.
603 if (is_blackbox)
604 return "bb_" + mangle_name(name);
605 return mangle_name(name);
606 }
607
608 std::string mangle_memory_name(const RTLIL::IdString &name)
609 {
610 // Class member namespace.
611 return "memory_" + mangle_name(name);
612 }
613
614 std::string mangle_cell_name(const RTLIL::IdString &name)
615 {
616 // Class member namespace.
617 return "cell_" + mangle_name(name);
618 }
619
620 std::string mangle_wire_name(const RTLIL::IdString &name)
621 {
622 // Class member namespace.
623 return mangle_name(name);
624 }
625
626 std::string mangle(const RTLIL::Module *module)
627 {
628 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
629 }
630
631 std::string mangle(const RTLIL::Memory *memory)
632 {
633 return mangle_memory_name(memory->name);
634 }
635
636 std::string mangle(const RTLIL::Cell *cell)
637 {
638 return mangle_cell_name(cell->name);
639 }
640
641 std::string mangle(const RTLIL::Wire *wire)
642 {
643 return mangle_wire_name(wire->name);
644 }
645
646 std::string mangle(RTLIL::SigBit sigbit)
647 {
648 log_assert(sigbit.wire != NULL);
649 if (sigbit.wire->width == 1)
650 return mangle(sigbit.wire);
651 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
652 }
653
654 std::vector<std::string> template_param_names(const RTLIL::Module *module)
655 {
656 if (!module->has_attribute(ID(cxxrtl_template)))
657 return {};
658
659 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
660 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
661
662 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
663 for (const auto &param_name : param_names) {
664 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
665 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
666 // in both Verilog and C++, anyway.)
667 if (!isupper(param_name[0]))
668 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
669 "which does not start with an uppercase letter.\n",
670 log_id(module), param_name.c_str());
671 }
672 return param_names;
673 }
674
675 std::string template_params(const RTLIL::Module *module, bool is_decl)
676 {
677 std::vector<std::string> param_names = template_param_names(module);
678 if (param_names.empty())
679 return "";
680
681 std::string params = "<";
682 bool first = true;
683 for (const auto &param_name : param_names) {
684 if (!first)
685 params += ", ";
686 first = false;
687 if (is_decl)
688 params += "size_t ";
689 params += param_name;
690 }
691 params += ">";
692 return params;
693 }
694
695 std::string template_args(const RTLIL::Cell *cell)
696 {
697 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
698 log_assert(cell_module != nullptr);
699 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
700 return "";
701
702 std::vector<std::string> param_names = template_param_names(cell_module);
703 if (param_names.empty())
704 return "";
705
706 std::string params = "<";
707 bool first = true;
708 for (const auto &param_name : param_names) {
709 if (!first)
710 params += ", ";
711 first = false;
712 params += "/*" + param_name + "=*/";
713 RTLIL::IdString id_param_name = '\\' + param_name;
714 if (!cell->hasParam(id_param_name))
715 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
716 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
717 RTLIL::Const param_value = cell->getParam(id_param_name);
718 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
719 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
720 "is not a positive integer.\n",
721 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
722 params += std::to_string(cell->getParam(id_param_name).as_int());
723 }
724 params += ">";
725 return params;
726 }
727
728 std::string fresh_temporary()
729 {
730 return stringf("tmp_%d", temporary++);
731 }
732
733 void dump_attrs(const RTLIL::AttrObject *object)
734 {
735 for (auto attr : object->attributes) {
736 f << indent << "// " << attr.first.str() << ": ";
737 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
738 f << attr.second.decode_string();
739 } else {
740 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
741 }
742 f << "\n";
743 }
744 }
745
746 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
747 {
748 const int CHUNK_SIZE = 32;
749 f << "{";
750 while (width > 0) {
751 int chunk_width = min(width, CHUNK_SIZE);
752 uint32_t chunk = data.extract(offset, chunk_width).as_int();
753 if (fixed_width)
754 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
755 else
756 f << stringf("%#xu", chunk);
757 if (width > CHUNK_SIZE)
758 f << ',';
759 offset += CHUNK_SIZE;
760 width -= CHUNK_SIZE;
761 }
762 f << "}";
763 }
764
765 void dump_const_init(const RTLIL::Const &data)
766 {
767 dump_const_init(data, data.size());
768 }
769
770 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
771 {
772 f << "value<" << width << ">";
773 dump_const_init(data, width, offset, fixed_width);
774 }
775
776 void dump_const(const RTLIL::Const &data)
777 {
778 dump_const(data, data.size());
779 }
780
781 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs)
782 {
783 if (chunk.wire == NULL) {
784 dump_const(chunk.data, chunk.width, chunk.offset);
785 return false;
786 } else {
787 if (!is_lhs && elided_wires.count(chunk.wire)) {
788 const FlowGraph::Node &node = elided_wires[chunk.wire];
789 switch (node.type) {
790 case FlowGraph::Node::Type::CONNECT:
791 dump_connect_elided(node.connect);
792 break;
793 case FlowGraph::Node::Type::CELL_EVAL:
794 log_assert(is_elidable_cell(node.cell->type));
795 dump_cell_elided(node.cell);
796 break;
797 default:
798 log_assert(false);
799 }
800 } else if (localized_wires[chunk.wire] || is_input_wire(chunk.wire)) {
801 f << mangle(chunk.wire);
802 } else {
803 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
804 }
805 if (chunk.width == chunk.wire->width && chunk.offset == 0)
806 return false;
807 else if (chunk.width == 1)
808 f << ".slice<" << chunk.offset << ">()";
809 else
810 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
811 return true;
812 }
813 }
814
815 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs)
816 {
817 if (sig.empty()) {
818 f << "value<0>()";
819 return false;
820 } else if (sig.is_chunk()) {
821 return dump_sigchunk(sig.as_chunk(), is_lhs);
822 } else {
823 dump_sigchunk(*sig.chunks().rbegin(), is_lhs);
824 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
825 f << ".concat(";
826 dump_sigchunk(*it, is_lhs);
827 f << ")";
828 }
829 return true;
830 }
831 }
832
833 void dump_sigspec_lhs(const RTLIL::SigSpec &sig)
834 {
835 dump_sigspec(sig, /*is_lhs=*/true);
836 }
837
838 void dump_sigspec_rhs(const RTLIL::SigSpec &sig)
839 {
840 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
841 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
842 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
843 // type conversion, but only if the expression needs it.
844 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false);
845 if (is_complex)
846 f << ".val()";
847 }
848
849 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
850 {
851 for (auto chunk : sig.chunks()) {
852 if (!chunk.wire || !elided_wires.count(chunk.wire))
853 continue;
854
855 const FlowGraph::Node &node = elided_wires[chunk.wire];
856 switch (node.type) {
857 case FlowGraph::Node::Type::CONNECT:
858 collect_connect(node.connect, cells);
859 break;
860 case FlowGraph::Node::Type::CELL_EVAL:
861 collect_cell_eval(node.cell, cells);
862 break;
863 default:
864 log_assert(false);
865 }
866 }
867 }
868
869 void dump_connect_elided(const RTLIL::SigSig &conn)
870 {
871 dump_sigspec_rhs(conn.second);
872 }
873
874 bool is_connect_elided(const RTLIL::SigSig &conn)
875 {
876 return conn.first.is_wire() && elided_wires.count(conn.first.as_wire());
877 }
878
879 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
880 {
881 if (!is_connect_elided(conn))
882 return;
883
884 collect_sigspec_rhs(conn.second, cells);
885 }
886
887 void dump_connect(const RTLIL::SigSig &conn)
888 {
889 if (is_connect_elided(conn))
890 return;
891
892 f << indent << "// connection\n";
893 f << indent;
894 dump_sigspec_lhs(conn.first);
895 f << " = ";
896 dump_connect_elided(conn);
897 f << ";\n";
898 }
899
900 void dump_cell_sync(const RTLIL::Cell *cell)
901 {
902 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
903 f << indent << "// cell " << cell->name.str() << " syncs\n";
904 for (auto conn : cell->connections())
905 if (cell->output(conn.first))
906 if (is_cxxrtl_sync_port(cell, conn.first)) {
907 f << indent;
908 dump_sigspec_lhs(conn.second);
909 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
910 }
911 }
912
913 void dump_cell_elided(const RTLIL::Cell *cell)
914 {
915 // Unary cells
916 if (is_unary_cell(cell->type)) {
917 f << cell->type.substr(1);
918 if (is_extending_cell(cell->type))
919 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
920 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
921 dump_sigspec_rhs(cell->getPort(ID::A));
922 f << ")";
923 // Binary cells
924 } else if (is_binary_cell(cell->type)) {
925 f << cell->type.substr(1);
926 if (is_extending_cell(cell->type))
927 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
928 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
929 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
930 dump_sigspec_rhs(cell->getPort(ID::A));
931 f << ", ";
932 dump_sigspec_rhs(cell->getPort(ID::B));
933 f << ")";
934 // Muxes
935 } else if (cell->type == ID($mux)) {
936 f << "(";
937 dump_sigspec_rhs(cell->getPort(ID::S));
938 f << " ? ";
939 dump_sigspec_rhs(cell->getPort(ID::B));
940 f << " : ";
941 dump_sigspec_rhs(cell->getPort(ID::A));
942 f << ")";
943 // Concats
944 } else if (cell->type == ID($concat)) {
945 dump_sigspec_rhs(cell->getPort(ID::B));
946 f << ".concat(";
947 dump_sigspec_rhs(cell->getPort(ID::A));
948 f << ").val()";
949 // Slices
950 } else if (cell->type == ID($slice)) {
951 dump_sigspec_rhs(cell->getPort(ID::A));
952 f << ".slice<";
953 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
954 f << ",";
955 f << cell->getParam(ID::OFFSET).as_int();
956 f << ">().val()";
957 } else {
958 log_assert(false);
959 }
960 }
961
962 bool is_cell_elided(const RTLIL::Cell *cell)
963 {
964 return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
965 elided_wires.count(cell->getPort(ID::Y).as_wire());
966 }
967
968 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
969 {
970 if (!is_cell_elided(cell))
971 return;
972
973 cells.push_back(cell->name);
974 for (auto port : cell->connections())
975 if (port.first != ID::Y)
976 collect_sigspec_rhs(port.second, cells);
977 }
978
979 void dump_cell_eval(const RTLIL::Cell *cell)
980 {
981 if (is_cell_elided(cell))
982 return;
983 if (cell->type == ID($meminit))
984 return; // Handled elsewhere.
985
986 std::vector<RTLIL::IdString> elided_cells;
987 if (is_elidable_cell(cell->type)) {
988 for (auto port : cell->connections())
989 if (port.first != ID::Y)
990 collect_sigspec_rhs(port.second, elided_cells);
991 }
992 if (elided_cells.empty()) {
993 dump_attrs(cell);
994 f << indent << "// cell " << cell->name.str() << "\n";
995 } else {
996 f << indent << "// cells";
997 for (auto elided_cell : elided_cells)
998 f << " " << elided_cell.str();
999 f << "\n";
1000 }
1001
1002 // Elidable cells
1003 if (is_elidable_cell(cell->type)) {
1004 f << indent;
1005 dump_sigspec_lhs(cell->getPort(ID::Y));
1006 f << " = ";
1007 dump_cell_elided(cell);
1008 f << ";\n";
1009 // Parallel (one-hot) muxes
1010 } else if (cell->type == ID($pmux)) {
1011 int width = cell->getParam(ID::WIDTH).as_int();
1012 int s_width = cell->getParam(ID::S_WIDTH).as_int();
1013 bool first = true;
1014 for (int part = 0; part < s_width; part++) {
1015 f << (first ? indent : " else ");
1016 first = false;
1017 f << "if (";
1018 dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
1019 f << ") {\n";
1020 inc_indent();
1021 f << indent;
1022 dump_sigspec_lhs(cell->getPort(ID::Y));
1023 f << " = ";
1024 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
1025 f << ";\n";
1026 dec_indent();
1027 f << indent << "}";
1028 }
1029 f << " else {\n";
1030 inc_indent();
1031 f << indent;
1032 dump_sigspec_lhs(cell->getPort(ID::Y));
1033 f << " = ";
1034 dump_sigspec_rhs(cell->getPort(ID::A));
1035 f << ";\n";
1036 dec_indent();
1037 f << indent << "}\n";
1038 // Flip-flops
1039 } else if (is_ff_cell(cell->type)) {
1040 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1041 // Edge-sensitive logic
1042 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1043 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1044 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1045 << mangle(clk_bit) << ") {\n";
1046 inc_indent();
1047 if (cell->type == ID($dffe)) {
1048 f << indent << "if (";
1049 dump_sigspec_rhs(cell->getPort(ID::EN));
1050 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1051 inc_indent();
1052 }
1053 f << indent;
1054 dump_sigspec_lhs(cell->getPort(ID::Q));
1055 f << " = ";
1056 dump_sigspec_rhs(cell->getPort(ID::D));
1057 f << ";\n";
1058 if (cell->type == ID($dffe)) {
1059 dec_indent();
1060 f << indent << "}\n";
1061 }
1062 dec_indent();
1063 f << indent << "}\n";
1064 } else if (cell->hasPort(ID::EN)) {
1065 // Level-sensitive logic
1066 f << indent << "if (";
1067 dump_sigspec_rhs(cell->getPort(ID::EN));
1068 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1069 inc_indent();
1070 f << indent;
1071 dump_sigspec_lhs(cell->getPort(ID::Q));
1072 f << " = ";
1073 dump_sigspec_rhs(cell->getPort(ID::D));
1074 f << ";\n";
1075 dec_indent();
1076 f << indent << "}\n";
1077 }
1078 if (cell->hasPort(ID::ARST)) {
1079 // Asynchronous reset (entire coarse cell at once)
1080 f << indent << "if (";
1081 dump_sigspec_rhs(cell->getPort(ID::ARST));
1082 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1083 inc_indent();
1084 f << indent;
1085 dump_sigspec_lhs(cell->getPort(ID::Q));
1086 f << " = ";
1087 dump_const(cell->getParam(ID::ARST_VALUE));
1088 f << ";\n";
1089 dec_indent();
1090 f << indent << "}\n";
1091 }
1092 if (cell->hasPort(ID::SET)) {
1093 // Asynchronous set (for individual bits)
1094 f << indent;
1095 dump_sigspec_lhs(cell->getPort(ID::Q));
1096 f << " = ";
1097 dump_sigspec_lhs(cell->getPort(ID::Q));
1098 f << ".update(";
1099 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1100 f << ", ";
1101 dump_sigspec_rhs(cell->getPort(ID::SET));
1102 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1103 }
1104 if (cell->hasPort(ID::CLR)) {
1105 // Asynchronous clear (for individual bits; priority over set)
1106 f << indent;
1107 dump_sigspec_lhs(cell->getPort(ID::Q));
1108 f << " = ";
1109 dump_sigspec_lhs(cell->getPort(ID::Q));
1110 f << ".update(";
1111 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1112 f << ", ";
1113 dump_sigspec_rhs(cell->getPort(ID::CLR));
1114 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1115 }
1116 // Memory ports
1117 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1118 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1119 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1120 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1121 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1122 << mangle(clk_bit) << ") {\n";
1123 inc_indent();
1124 }
1125 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1126 std::string valid_index_temp = fresh_temporary();
1127 f << indent << "auto " << valid_index_temp << " = memory_index(";
1128 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1129 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1130 if (cell->type == ID($memrd)) {
1131 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1132 if (has_enable) {
1133 f << indent << "if (";
1134 dump_sigspec_rhs(cell->getPort(ID::EN));
1135 f << ") {\n";
1136 inc_indent();
1137 }
1138 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1139 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1140 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -NDEBUG not
1141 // just for release builds, but also to make sure the simulator (which is presumably embedded in some
1142 // larger program) will never crash the code that calls into it.
1143 //
1144 // If assertions are disabled, out of bounds reads are defined to return zero.
1145 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1146 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1147 inc_indent();
1148 if (writable_memories[memory]) {
1149 std::string addr_temp = fresh_temporary();
1150 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1151 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1152 f << ";\n";
1153 std::string lhs_temp = fresh_temporary();
1154 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1155 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1156 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1157 std::sort(memwr_cells.begin(), memwr_cells.end(),
1158 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1159 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1160 });
1161 for (auto memwr_cell : memwr_cells) {
1162 f << indent << "if (" << addr_temp << " == ";
1163 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1164 f << ") {\n";
1165 inc_indent();
1166 f << indent << lhs_temp << " = " << lhs_temp;
1167 f << ".update(";
1168 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1169 f << ", ";
1170 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1171 f << ");\n";
1172 dec_indent();
1173 f << indent << "}\n";
1174 }
1175 f << indent;
1176 dump_sigspec_lhs(cell->getPort(ID::DATA));
1177 f << " = " << lhs_temp << ";\n";
1178 } else {
1179 f << indent;
1180 dump_sigspec_lhs(cell->getPort(ID::DATA));
1181 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1182 }
1183 dec_indent();
1184 f << indent << "} else {\n";
1185 inc_indent();
1186 f << indent;
1187 dump_sigspec_lhs(cell->getPort(ID::DATA));
1188 f << " = value<" << memory->width << "> {};\n";
1189 dec_indent();
1190 f << indent << "}\n";
1191 if (has_enable) {
1192 dec_indent();
1193 f << indent << "}\n";
1194 }
1195 } else /*if (cell->type == ID($memwr))*/ {
1196 log_assert(writable_memories[memory]);
1197 // See above for rationale of having both the assert and the condition.
1198 //
1199 // If assertions are disabled, out of bounds writes are defined to do nothing.
1200 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1201 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1202 inc_indent();
1203 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1204 dump_sigspec_rhs(cell->getPort(ID::DATA));
1205 f << ", ";
1206 dump_sigspec_rhs(cell->getPort(ID::EN));
1207 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1208 dec_indent();
1209 f << indent << "}\n";
1210 }
1211 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1212 dec_indent();
1213 f << indent << "}\n";
1214 }
1215 // Internal cells
1216 } else if (is_internal_cell(cell->type)) {
1217 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1218 // User cells
1219 } else {
1220 log_assert(cell->known());
1221 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1222 for (auto conn : cell->connections())
1223 if (cell->input(conn.first) && !cell->output(conn.first)) {
1224 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = ";
1225 dump_sigspec_rhs(conn.second);
1226 f << ";\n";
1227 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1228 // Until we have proper clock tree detection, this really awful hack that opportunistically
1229 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1230 // be if only one clock edge was simulated by replacing:
1231 // top.p_clk = value<1>{0u}; top.step();
1232 // top.p_clk = value<1>{1u}; top.step();
1233 // with:
1234 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1235 // Don't rely on this; it will be removed without warning.
1236 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1237 if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) {
1238 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1239 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1240 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1241 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1242 }
1243 }
1244 }
1245 } else if (cell->input(conn.first)) {
1246 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = ";
1247 dump_sigspec_rhs(conn.second);
1248 f << ";\n";
1249 }
1250 auto assign_from_outputs = [&](bool cell_converged) {
1251 for (auto conn : cell->connections()) {
1252 if (cell->output(conn.first)) {
1253 if (conn.second.empty())
1254 continue; // ignore disconnected ports
1255 if (is_cxxrtl_sync_port(cell, conn.first))
1256 continue; // fully sync ports are handled in CELL_SYNC nodes
1257 f << indent;
1258 dump_sigspec_lhs(conn.second);
1259 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1260 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1261 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1262 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1263 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1264 // and consider the fate of the localized wires that used to be output ports.)
1265 //
1266 // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell
1267 // (which may be late bound) will converge immediately. Because of this, the choice between using .curr
1268 // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime.
1269 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1270 f << ".next;\n";
1271 else
1272 f << ".curr;\n";
1273 }
1274 }
1275 };
1276 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1277 inc_indent();
1278 assign_from_outputs(/*cell_converged=*/true);
1279 dec_indent();
1280 f << indent << "} else {\n";
1281 inc_indent();
1282 f << indent << "converged = false;\n";
1283 assign_from_outputs(/*cell_converged=*/false);
1284 dec_indent();
1285 f << indent << "}\n";
1286 }
1287 }
1288
1289 void dump_assign(const RTLIL::SigSig &sigsig)
1290 {
1291 f << indent;
1292 dump_sigspec_lhs(sigsig.first);
1293 f << " = ";
1294 dump_sigspec_rhs(sigsig.second);
1295 f << ";\n";
1296 }
1297
1298 void dump_case_rule(const RTLIL::CaseRule *rule)
1299 {
1300 for (auto action : rule->actions)
1301 dump_assign(action);
1302 for (auto switch_ : rule->switches)
1303 dump_switch_rule(switch_);
1304 }
1305
1306 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1307 {
1308 // The switch attributes are printed before the switch condition is captured.
1309 dump_attrs(rule);
1310 std::string signal_temp = fresh_temporary();
1311 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1312 dump_sigspec(rule->signal, /*is_lhs=*/false);
1313 f << ";\n";
1314
1315 bool first = true;
1316 for (auto case_ : rule->cases) {
1317 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1318 dump_attrs(rule);
1319 f << indent;
1320 if (!first)
1321 f << "} else ";
1322 first = false;
1323 if (!case_->compare.empty()) {
1324 f << "if (";
1325 bool first = true;
1326 for (auto &compare : case_->compare) {
1327 if (!first)
1328 f << " || ";
1329 first = false;
1330 if (compare.is_fully_def()) {
1331 f << signal_temp << " == ";
1332 dump_sigspec(compare, /*is_lhs=*/false);
1333 } else if (compare.is_fully_const()) {
1334 RTLIL::Const compare_mask, compare_value;
1335 for (auto bit : compare.as_const()) {
1336 switch (bit) {
1337 case RTLIL::S0:
1338 case RTLIL::S1:
1339 compare_mask.bits.push_back(RTLIL::S1);
1340 compare_value.bits.push_back(bit);
1341 break;
1342
1343 case RTLIL::Sx:
1344 case RTLIL::Sz:
1345 case RTLIL::Sa:
1346 compare_mask.bits.push_back(RTLIL::S0);
1347 compare_value.bits.push_back(RTLIL::S0);
1348 break;
1349
1350 default:
1351 log_assert(false);
1352 }
1353 }
1354 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1355 dump_const(compare_mask);
1356 f << ") == ";
1357 dump_const(compare_value);
1358 } else {
1359 log_assert(false);
1360 }
1361 }
1362 f << ") ";
1363 }
1364 f << "{\n";
1365 inc_indent();
1366 dump_case_rule(case_);
1367 dec_indent();
1368 }
1369 f << indent << "}\n";
1370 }
1371
1372 void dump_process(const RTLIL::Process *proc)
1373 {
1374 dump_attrs(proc);
1375 f << indent << "// process " << proc->name.str() << "\n";
1376 // The case attributes (for root case) are always empty.
1377 log_assert(proc->root_case.attributes.empty());
1378 dump_case_rule(&proc->root_case);
1379 for (auto sync : proc->syncs) {
1380 RTLIL::SigBit sync_bit;
1381 if (!sync->signal.empty()) {
1382 sync_bit = sync->signal[0];
1383 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1384 }
1385
1386 pool<std::string> events;
1387 switch (sync->type) {
1388 case RTLIL::STp:
1389 log_assert(sync_bit.wire != nullptr);
1390 events.insert("posedge_" + mangle(sync_bit));
1391 break;
1392 case RTLIL::STn:
1393 log_assert(sync_bit.wire != nullptr);
1394 events.insert("negedge_" + mangle(sync_bit));
1395 break;
1396 case RTLIL::STe:
1397 log_assert(sync_bit.wire != nullptr);
1398 events.insert("posedge_" + mangle(sync_bit));
1399 events.insert("negedge_" + mangle(sync_bit));
1400 break;
1401
1402 case RTLIL::STa:
1403 events.insert("true");
1404 break;
1405
1406 case RTLIL::ST0:
1407 case RTLIL::ST1:
1408 case RTLIL::STg:
1409 case RTLIL::STi:
1410 log_assert(false);
1411 }
1412 if (!events.empty()) {
1413 f << indent << "if (";
1414 bool first = true;
1415 for (auto &event : events) {
1416 if (!first)
1417 f << " || ";
1418 first = false;
1419 f << event;
1420 }
1421 f << ") {\n";
1422 inc_indent();
1423 for (auto action : sync->actions)
1424 dump_assign(action);
1425 dec_indent();
1426 f << indent << "}\n";
1427 }
1428 }
1429 }
1430
1431 void dump_wire(const RTLIL::Wire *wire, bool is_local_context)
1432 {
1433 if (elided_wires.count(wire))
1434 return;
1435 if (localized_wires.count(wire) != is_local_context)
1436 return;
1437
1438 if (is_local_context) {
1439 dump_attrs(wire);
1440 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1441 } else {
1442 std::string width;
1443 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1444 width = wire->get_string_attribute(ID(cxxrtl_width));
1445 } else {
1446 width = std::to_string(wire->width);
1447 }
1448
1449 dump_attrs(wire);
1450 f << indent << (is_input_wire(wire) ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1451 if (wire->has_attribute(ID::init)) {
1452 f << " ";
1453 dump_const_init(wire->attributes.at(ID::init));
1454 }
1455 f << ";\n";
1456 if (edge_wires[wire]) {
1457 if (is_input_wire(wire)) {
1458 f << indent << "value<" << width << "> prev_" << mangle(wire);
1459 if (wire->has_attribute(ID::init)) {
1460 f << " ";
1461 dump_const_init(wire->attributes.at(ID::init));
1462 }
1463 f << ";\n";
1464 }
1465 for (auto edge_type : edge_types) {
1466 if (edge_type.first.wire == wire) {
1467 std::string prev, next;
1468 if (is_input_wire(wire)) {
1469 prev = "prev_" + mangle(edge_type.first.wire);
1470 next = mangle(edge_type.first.wire);
1471 } else {
1472 prev = mangle(edge_type.first.wire) + ".curr";
1473 next = mangle(edge_type.first.wire) + ".next";
1474 }
1475 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1476 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1477 if (edge_type.second != RTLIL::STn) {
1478 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1479 inc_indent();
1480 f << indent << "return !" << prev << " && " << next << ";\n";
1481 dec_indent();
1482 f << indent << "}\n";
1483 }
1484 if (edge_type.second != RTLIL::STp) {
1485 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1486 inc_indent();
1487 f << indent << "return " << prev << " && !" << next << ";\n";
1488 dec_indent();
1489 f << indent << "}\n";
1490 }
1491 }
1492 }
1493 }
1494 }
1495 }
1496
1497 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1498 {
1499 vector<const RTLIL::Cell*> init_cells;
1500 for (auto cell : module->cells())
1501 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1502 init_cells.push_back(cell);
1503
1504 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1505 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1506 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1507 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1508 });
1509
1510 dump_attrs(memory);
1511 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1512 << " { " << memory->size << "u";
1513 if (init_cells.empty()) {
1514 f << " };\n";
1515 } else {
1516 f << ",\n";
1517 inc_indent();
1518 for (auto cell : init_cells) {
1519 dump_attrs(cell);
1520 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1521 size_t width = cell->getParam(ID::WIDTH).as_int();
1522 size_t words = cell->getParam(ID::WORDS).as_int();
1523 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1524 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1525 inc_indent();
1526 for (size_t n = 0; n < words; n++) {
1527 if (n % 4 == 0)
1528 f << "\n" << indent;
1529 else
1530 f << " ";
1531 dump_const(data, width, n * width, /*fixed_width=*/true);
1532 f << ",";
1533 }
1534 dec_indent();
1535 f << "\n" << indent << "}},\n";
1536 }
1537 dec_indent();
1538 f << indent << "};\n";
1539 }
1540 }
1541
1542 void dump_eval_method(RTLIL::Module *module)
1543 {
1544 inc_indent();
1545 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1546 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1547 for (auto wire : module->wires()) {
1548 if (edge_wires[wire]) {
1549 for (auto edge_type : edge_types) {
1550 if (edge_type.first.wire == wire) {
1551 if (edge_type.second != RTLIL::STn) {
1552 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1553 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1554 }
1555 if (edge_type.second != RTLIL::STp) {
1556 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1557 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1558 }
1559 }
1560 }
1561 }
1562 }
1563 for (auto wire : module->wires())
1564 dump_wire(wire, /*is_local_context=*/true);
1565 for (auto node : schedule[module]) {
1566 switch (node.type) {
1567 case FlowGraph::Node::Type::CONNECT:
1568 dump_connect(node.connect);
1569 break;
1570 case FlowGraph::Node::Type::CELL_SYNC:
1571 dump_cell_sync(node.cell);
1572 break;
1573 case FlowGraph::Node::Type::CELL_EVAL:
1574 dump_cell_eval(node.cell);
1575 break;
1576 case FlowGraph::Node::Type::PROCESS:
1577 dump_process(node.process);
1578 break;
1579 }
1580 }
1581 }
1582 f << indent << "return converged;\n";
1583 dec_indent();
1584 }
1585
1586 void dump_commit_method(RTLIL::Module *module)
1587 {
1588 inc_indent();
1589 f << indent << "bool changed = false;\n";
1590 for (auto wire : module->wires()) {
1591 if (elided_wires.count(wire) || localized_wires.count(wire))
1592 continue;
1593 if (is_input_wire(wire)) {
1594 if (edge_wires[wire])
1595 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1596 continue;
1597 }
1598 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1599 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1600 }
1601 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1602 for (auto memory : module->memories) {
1603 if (!writable_memories[memory.second])
1604 continue;
1605 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1606 }
1607 for (auto cell : module->cells()) {
1608 if (is_internal_cell(cell->type))
1609 continue;
1610 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1611 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1612 }
1613 }
1614 f << indent << "return changed;\n";
1615 dec_indent();
1616 }
1617
1618 void dump_debug_info_method(RTLIL::Module *module)
1619 {
1620 size_t count_const_wires = 0;
1621 size_t count_alias_wires = 0;
1622 size_t count_member_wires = 0;
1623 size_t count_skipped_wires = 0;
1624 inc_indent();
1625 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1626 for (auto wire : module->wires()) {
1627 if (wire->name[0] != '\\')
1628 continue;
1629 if (debug_const_wires.count(wire)) {
1630 // Wire tied to a constant
1631 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1632 dump_const(debug_const_wires[wire]);
1633 f << ";\n";
1634 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1635 f << ", debug_item(const_" << mangle(wire) << "));\n";
1636 count_const_wires++;
1637 } else if (debug_alias_wires.count(wire)) {
1638 // Alias of a member wire
1639 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1640 f << ", debug_item(" << mangle(debug_alias_wires[wire]) << "));\n";
1641 count_alias_wires++;
1642 } else if (!localized_wires.count(wire)) {
1643 // Member wire
1644 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1645 f << ", debug_item(" << mangle(wire) << "));\n";
1646 count_member_wires++;
1647 } else {
1648 count_skipped_wires++;
1649 }
1650 }
1651 for (auto &memory_it : module->memories) {
1652 if (memory_it.first[0] != '\\')
1653 continue;
1654 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1655 f << ", debug_item(" << mangle(memory_it.second) << "));\n";
1656 }
1657 for (auto cell : module->cells()) {
1658 if (is_internal_cell(cell->type))
1659 continue;
1660 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1661 f << indent << mangle(cell) << access << "debug_info(items, ";
1662 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1663 }
1664 dec_indent();
1665
1666 log_debug("Debug information statistics for module %s:\n", log_id(module));
1667 log_debug(" Const wires: %zu\n", count_const_wires);
1668 log_debug(" Alias wires: %zu\n", count_alias_wires);
1669 log_debug(" Member wires: %zu\n", count_member_wires);
1670 log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
1671 }
1672
1673 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1674 {
1675 if (metadata_map.empty()) {
1676 f << "metadata_map()";
1677 return;
1678 }
1679 f << "metadata_map({\n";
1680 inc_indent();
1681 for (auto metadata_item : metadata_map) {
1682 if (!metadata_item.first.begins_with("\\"))
1683 continue;
1684 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1685 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1686 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1687 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1688 f << escape_cxx_string(metadata_item.second.decode_string());
1689 } else {
1690 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1691 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1692 f << "u";
1693 }
1694 f << " },\n";
1695 }
1696 dec_indent();
1697 f << indent << "})";
1698 }
1699
1700 void dump_module_intf(RTLIL::Module *module)
1701 {
1702 dump_attrs(module);
1703 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1704 if (module->has_attribute(ID(cxxrtl_template)))
1705 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1706 f << indent << "struct " << mangle(module) << " : public module {\n";
1707 inc_indent();
1708 for (auto wire : module->wires()) {
1709 if (wire->port_id != 0)
1710 dump_wire(wire, /*is_local_context=*/false);
1711 }
1712 f << "\n";
1713 f << indent << "bool eval() override {\n";
1714 dump_eval_method(module);
1715 f << indent << "}\n";
1716 f << "\n";
1717 f << indent << "bool commit() override {\n";
1718 dump_commit_method(module);
1719 f << indent << "}\n";
1720 f << "\n";
1721 if (debug_info) {
1722 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1723 dump_debug_info_method(module);
1724 f << indent << "}\n";
1725 f << "\n";
1726 }
1727 f << indent << "static std::unique_ptr<" << mangle(module);
1728 f << template_params(module, /*is_decl=*/false) << "> ";
1729 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1730 dec_indent();
1731 f << indent << "}; // struct " << mangle(module) << "\n";
1732 f << "\n";
1733 if (blackbox_specializations.count(module)) {
1734 // If templated black boxes are used, the constructor of any module which includes the black box cell
1735 // (which calls the declared but not defined in the generated code `create` function) may only be used
1736 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1737 // a forward-declared explicit specialization.
1738 //
1739 // Option (b) makes it possible to have the generated code and the black box implementation in different
1740 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1741 // a specialization for every combination of parameters the generated code may use; but since the main
1742 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1743 // be very few such combinations anyway.
1744 for (auto specialization : blackbox_specializations[module]) {
1745 f << indent << "template<>\n";
1746 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1747 f << mangle(module) << specialization << "::";
1748 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1749 f << "\n";
1750 }
1751 }
1752 } else {
1753 f << indent << "struct " << mangle(module) << " : public module {\n";
1754 inc_indent();
1755 for (auto wire : module->wires())
1756 dump_wire(wire, /*is_local_context=*/false);
1757 f << "\n";
1758 bool has_memories = false;
1759 for (auto memory : module->memories) {
1760 dump_memory(module, memory.second);
1761 has_memories = true;
1762 }
1763 if (has_memories)
1764 f << "\n";
1765 bool has_cells = false;
1766 for (auto cell : module->cells()) {
1767 if (is_internal_cell(cell->type))
1768 continue;
1769 dump_attrs(cell);
1770 RTLIL::Module *cell_module = module->design->module(cell->type);
1771 log_assert(cell_module != nullptr);
1772 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1773 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1774 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1775 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1776 dump_metadata_map(cell->parameters);
1777 f << ", ";
1778 dump_metadata_map(cell->attributes);
1779 f << ");\n";
1780 } else {
1781 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1782 }
1783 has_cells = true;
1784 }
1785 if (has_cells)
1786 f << "\n";
1787 f << indent << "bool eval() override;\n";
1788 f << indent << "bool commit() override;\n";
1789 if (debug_info)
1790 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
1791 dec_indent();
1792 f << indent << "}; // struct " << mangle(module) << "\n";
1793 f << "\n";
1794 }
1795 }
1796
1797 void dump_module_impl(RTLIL::Module *module)
1798 {
1799 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1800 return;
1801 f << indent << "bool " << mangle(module) << "::eval() {\n";
1802 dump_eval_method(module);
1803 f << indent << "}\n";
1804 f << "\n";
1805 f << indent << "bool " << mangle(module) << "::commit() {\n";
1806 dump_commit_method(module);
1807 f << indent << "}\n";
1808 f << "\n";
1809 if (debug_info) {
1810 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
1811 dump_debug_info_method(module);
1812 f << indent << "}\n";
1813 f << "\n";
1814 }
1815 }
1816
1817 void dump_design(RTLIL::Design *design)
1818 {
1819 RTLIL::Module *top_module = nullptr;
1820 std::vector<RTLIL::Module*> modules;
1821 TopoSort<RTLIL::Module*> topo_design;
1822 for (auto module : design->modules()) {
1823 if (!design->selected_module(module))
1824 continue;
1825 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1826 modules.push_back(module); // cxxrtl blackboxes first
1827 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
1828 continue;
1829 if (module->get_bool_attribute(ID::top))
1830 top_module = module;
1831
1832 topo_design.node(module);
1833 for (auto cell : module->cells()) {
1834 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
1835 continue;
1836 RTLIL::Module *cell_module = design->module(cell->type);
1837 log_assert(cell_module != nullptr);
1838 topo_design.edge(cell_module, module);
1839 }
1840 }
1841 log_assert(topo_design.sort());
1842 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
1843
1844 if (split_intf) {
1845 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
1846 std::string include_guard = design_ns + "_header";
1847 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
1848
1849 f << "#ifndef " << include_guard << "\n";
1850 f << "#define " << include_guard << "\n";
1851 f << "\n";
1852 if (top_module != nullptr && debug_info) {
1853 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
1854 f << "\n";
1855 f << "#ifdef __cplusplus\n";
1856 f << "extern \"C\" {\n";
1857 f << "#endif\n";
1858 f << "\n";
1859 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
1860 f << "\n";
1861 f << "#ifdef __cplusplus\n";
1862 f << "}\n";
1863 f << "#endif\n";
1864 f << "\n";
1865 } else {
1866 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
1867 f << "\n";
1868 }
1869 f << "#ifdef __cplusplus\n";
1870 f << "\n";
1871 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1872 f << "\n";
1873 f << "using namespace cxxrtl;\n";
1874 f << "\n";
1875 f << "namespace " << design_ns << " {\n";
1876 f << "\n";
1877 for (auto module : modules)
1878 dump_module_intf(module);
1879 f << "} // namespace " << design_ns << "\n";
1880 f << "\n";
1881 f << "#endif // __cplusplus\n";
1882 f << "\n";
1883 f << "#endif\n";
1884 *intf_f << f.str(); f.str("");
1885 }
1886
1887 if (split_intf)
1888 f << "#include \"" << intf_filename << "\"\n";
1889 else
1890 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1891 f << "\n";
1892 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
1893 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1894 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
1895 f << "#endif\n";
1896 f << "\n";
1897 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1898 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
1899 f << "#endif\n";
1900 f << "\n";
1901 f << "using namespace cxxrtl_yosys;\n";
1902 f << "\n";
1903 f << "namespace " << design_ns << " {\n";
1904 f << "\n";
1905 for (auto module : modules) {
1906 if (!split_intf)
1907 dump_module_intf(module);
1908 dump_module_impl(module);
1909 }
1910 f << "} // namespace " << design_ns << "\n";
1911 f << "\n";
1912 if (top_module != nullptr && debug_info) {
1913 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
1914 inc_indent();
1915 f << indent << "return new _cxxrtl_toplevel { ";
1916 f << "std::make_unique<" << design_ns << "::" << mangle(top_module) << ">()";
1917 f << " };\n";
1918 dec_indent();
1919 f << "}\n";
1920 }
1921
1922 *impl_f << f.str(); f.str("");
1923 }
1924
1925 // Edge-type sync rules require us to emit edge detectors, which require coordination between
1926 // eval and commit phases. To do this we need to collect them upfront.
1927 //
1928 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
1929 // operate at wire bit granularity; it is possible to have code similar to:
1930 // wire [3:0] clocks;
1931 // always @(posedge clocks[0]) ...
1932 // To handle this we track edge sensitivity both for wires and wire bits.
1933 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
1934 {
1935 signal = sigmap(signal);
1936 log_assert(signal.is_wire() && signal.is_bit());
1937 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
1938
1939 RTLIL::SigBit sigbit = signal[0];
1940 if (!edge_types.count(sigbit))
1941 edge_types[sigbit] = type;
1942 else if (edge_types[sigbit] != type)
1943 edge_types[sigbit] = RTLIL::STe;
1944 edge_wires.insert(signal.as_wire());
1945 }
1946
1947 void analyze_design(RTLIL::Design *design)
1948 {
1949 bool has_feedback_arcs = false;
1950 bool has_buffered_wires = false;
1951
1952 for (auto module : design->modules()) {
1953 if (!design->selected_module(module))
1954 continue;
1955
1956 SigMap &sigmap = sigmaps[module];
1957 sigmap.set(module);
1958
1959 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1960 for (auto port : module->ports) {
1961 RTLIL::Wire *wire = module->wire(port);
1962 if (wire->has_attribute(ID(cxxrtl_edge))) {
1963 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
1964 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
1965 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
1966 log_id(module), log_signal(wire));
1967
1968 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
1969 for (int i = 0; i < GetSize(wire); i++) {
1970 RTLIL::SigSpec wire_sig = wire;
1971 switch (edges[i]) {
1972 case '-': break;
1973 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
1974 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
1975 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
1976 default:
1977 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
1978 "other than '-', 'p', 'n', or 'a'.\n",
1979 log_id(module), log_signal(wire));
1980 }
1981 }
1982 }
1983 }
1984
1985 // Black boxes converge by default, since their implementations are quite unlikely to require
1986 // internal propagation of comb signals.
1987 eval_converges[module] = true;
1988 continue;
1989 }
1990
1991 FlowGraph flow;
1992
1993 for (auto conn : module->connections())
1994 flow.add_node(conn);
1995
1996 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
1997 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
1998 pool<const RTLIL::Cell*>> memwr_per_domain;
1999 for (auto cell : module->cells()) {
2000 if (!cell->known())
2001 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2002
2003 RTLIL::Module *cell_module = design->module(cell->type);
2004 if (cell_module &&
2005 cell_module->get_blackbox_attribute() &&
2006 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2007 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2008
2009 if (cell_module &&
2010 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2011 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2012 blackbox_specializations[cell_module].insert(template_args(cell));
2013
2014 FlowGraph::Node *node = flow.add_node(cell);
2015
2016 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2017 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
2018 if (cell->getPort(ID::CLK).is_wire())
2019 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2020 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2021 }
2022 // Similar for memory port cells.
2023 if (cell->type.in(ID($memrd), ID($memwr))) {
2024 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2025 if (cell->getPort(ID::CLK).is_wire())
2026 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2027 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2028 }
2029 memrw_cell_nodes[cell] = node;
2030 }
2031 // Optimize access to read-only memories.
2032 if (cell->type == ID($memwr))
2033 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2034 // Collect groups of memory write ports in the same domain.
2035 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2036 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2037 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2038 memwr_per_domain[{clk_bit, memory}].insert(cell);
2039 }
2040 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2041 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2042 if (cell->type.in(ID($mem)))
2043 log_assert(false);
2044 }
2045 for (auto cell : module->cells()) {
2046 // Collect groups of memory write ports read by every transparent read port.
2047 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2048 cell->getParam(ID::TRANSPARENT).as_bool()) {
2049 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2050 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2051 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2052 transparent_for[cell].insert(memwr_cell);
2053 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2054 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2055 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2056 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2057 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2058 }
2059 }
2060 }
2061
2062 for (auto proc : module->processes) {
2063 flow.add_node(proc.second);
2064
2065 for (auto sync : proc.second->syncs)
2066 switch (sync->type) {
2067 // Edge-type sync rules require pre-registration.
2068 case RTLIL::STp:
2069 case RTLIL::STn:
2070 case RTLIL::STe:
2071 register_edge_signal(sigmap, sync->signal, sync->type);
2072 break;
2073
2074 // Level-type sync rules require no special handling.
2075 case RTLIL::ST0:
2076 case RTLIL::ST1:
2077 case RTLIL::STa:
2078 break;
2079
2080 case RTLIL::STg:
2081 log_cmd_error("Global clock is not supported.\n");
2082
2083 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2084 // attribute regardless of input.
2085 case RTLIL::STi:
2086 log_assert(false);
2087 }
2088 }
2089
2090 for (auto wire : module->wires()) {
2091 if (!flow.is_elidable(wire)) continue;
2092 if (wire->port_id != 0) continue;
2093 if (wire->get_bool_attribute(ID::keep)) continue;
2094 if (wire->name.begins_with("$") && !elide_internal) continue;
2095 if (wire->name.begins_with("\\") && !elide_public) continue;
2096 if (edge_wires[wire]) continue;
2097 log_assert(flow.wire_comb_defs[wire].size() == 1);
2098 elided_wires[wire] = **flow.wire_comb_defs[wire].begin();
2099 }
2100
2101 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2102 for (auto wire_comb_def : flow.wire_comb_defs)
2103 for (auto node : wire_comb_def.second)
2104 node_defs[node].insert(wire_comb_def.first);
2105
2106 Scheduler<FlowGraph::Node> scheduler;
2107 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2108 for (auto node : flow.nodes)
2109 node_map[node] = scheduler.add(node);
2110 for (auto node_def : node_defs) {
2111 auto vertex = node_map[node_def.first];
2112 for (auto wire : node_def.second)
2113 for (auto succ_node : flow.wire_uses[wire]) {
2114 auto succ_vertex = node_map[succ_node];
2115 vertex->succs.insert(succ_vertex);
2116 succ_vertex->preds.insert(vertex);
2117 }
2118 }
2119
2120 auto eval_order = scheduler.schedule();
2121 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2122 pool<const RTLIL::Wire*> feedback_wires;
2123 for (auto vertex : eval_order) {
2124 auto node = vertex->data;
2125 schedule[module].push_back(*node);
2126 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2127 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2128 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2129 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2130 evaluated.insert(node);
2131 for (auto wire : node_defs[node])
2132 for (auto succ_node : flow.wire_uses[wire])
2133 if (evaluated[succ_node]) {
2134 feedback_wires.insert(wire);
2135 // Feedback wires may never be elided because feedback requires state, but the point of elision
2136 // (and localization) is to eliminate state.
2137 elided_wires.erase(wire);
2138 }
2139 }
2140
2141 if (!feedback_wires.empty()) {
2142 has_feedback_arcs = true;
2143 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2144 for (auto wire : feedback_wires)
2145 log(" %s\n", log_id(wire));
2146 log("\n");
2147 }
2148
2149 for (auto wire : module->wires()) {
2150 if (feedback_wires[wire]) continue;
2151 if (wire->port_id != 0) continue;
2152 if (wire->get_bool_attribute(ID::keep)) continue;
2153 if (wire->name.begins_with("$") && !localize_internal) continue;
2154 if (wire->name.begins_with("\\") && !localize_public) continue;
2155 if (edge_wires[wire]) continue;
2156 if (flow.wire_sync_defs.count(wire) > 0) continue;
2157 localized_wires.insert(wire);
2158 }
2159
2160 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2161 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2162 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2163 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2164 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2165 // also require more than one delta cycle to converge.
2166 pool<const RTLIL::Wire*> buffered_wires;
2167 for (auto wire : module->wires()) {
2168 if (flow.wire_comb_defs[wire].size() > 0 && !elided_wires.count(wire) && !localized_wires[wire]) {
2169 if (!feedback_wires[wire])
2170 buffered_wires.insert(wire);
2171 }
2172 }
2173 if (!buffered_wires.empty()) {
2174 has_buffered_wires = true;
2175 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2176 for (auto wire : buffered_wires)
2177 log(" %s\n", log_id(wire));
2178 log("\n");
2179 }
2180
2181 eval_converges[module] = feedback_wires.empty() && buffered_wires.empty();
2182
2183 if (debug_info) {
2184 // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
2185 // at essentially zero additional cost.
2186 //
2187 // Note that the information collected here can't be used for optimizing the netlist: debug information queries
2188 // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
2189 for (auto wire : module->wires()) {
2190 if (wire->name[0] != '\\')
2191 continue;
2192 if (!localized_wires[wire])
2193 continue;
2194 const RTLIL::Wire *wire_it = wire;
2195 while (1) {
2196 if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it]))
2197 break; // not an alias: complex def
2198 log_assert(flow.wire_comb_defs[wire_it].size() == 1);
2199 FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin();
2200 if (node->type != FlowGraph::Node::Type::CONNECT)
2201 break; // not an alias: def by cell
2202 RTLIL::SigSpec rhs_sig = node->connect.second;
2203 if (rhs_sig.is_wire()) {
2204 RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
2205 if (localized_wires[rhs_wire]) {
2206 wire_it = rhs_wire; // maybe an alias
2207 } else {
2208 debug_alias_wires[wire] = rhs_wire; // is an alias
2209 break;
2210 }
2211 } else if (rhs_sig.is_fully_const()) {
2212 debug_const_wires[wire] = rhs_sig.as_const(); // is a const
2213 break;
2214 } else {
2215 break; // not an alias: complex rhs
2216 }
2217 }
2218 }
2219 }
2220 }
2221 if (has_feedback_arcs || has_buffered_wires) {
2222 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2223 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2224 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2225 const char *why_pessimistic = nullptr;
2226 if (has_feedback_arcs)
2227 why_pessimistic = "feedback wires";
2228 else if (has_buffered_wires)
2229 why_pessimistic = "buffered combinatorial wires";
2230 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2231 if (!max_opt_level)
2232 log("Increasing the optimization level may eliminate %s from the design.\n", why_pessimistic);
2233 }
2234 }
2235
2236 void check_design(RTLIL::Design *design, bool &has_sync_init, bool &has_packed_mem)
2237 {
2238 has_sync_init = has_packed_mem = false;
2239
2240 for (auto module : design->modules()) {
2241 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2242 continue;
2243
2244 if (!design->selected_whole_module(module))
2245 if (design->selected_module(module))
2246 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2247 if (!design->selected_module(module))
2248 continue;
2249
2250 for (auto proc : module->processes)
2251 for (auto sync : proc.second->syncs)
2252 if (sync->type == RTLIL::STi)
2253 has_sync_init = true;
2254
2255 for (auto cell : module->cells())
2256 if (cell->type == ID($mem))
2257 has_packed_mem = true;
2258 }
2259 }
2260
2261 void prepare_design(RTLIL::Design *design)
2262 {
2263 bool did_anything = false;
2264 bool has_sync_init, has_packed_mem;
2265 log_push();
2266 check_design(design, has_sync_init, has_packed_mem);
2267 if (run_proc_flatten) {
2268 Pass::call(design, "proc");
2269 Pass::call(design, "flatten");
2270 did_anything = true;
2271 } else if (has_sync_init) {
2272 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2273 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2274 Pass::call(design, "proc_prune");
2275 Pass::call(design, "proc_clean");
2276 Pass::call(design, "proc_init");
2277 did_anything = true;
2278 }
2279 if (has_packed_mem) {
2280 Pass::call(design, "memory_unpack");
2281 did_anything = true;
2282 }
2283 // Recheck the design if it was modified.
2284 if (has_sync_init || has_packed_mem)
2285 check_design(design, has_sync_init, has_packed_mem);
2286 log_assert(!(has_sync_init || has_packed_mem));
2287 log_pop();
2288 if (did_anything)
2289 log_spacer();
2290 analyze_design(design);
2291 }
2292 };
2293
2294 struct CxxrtlBackend : public Backend {
2295 static const int DEFAULT_OPT_LEVEL = 5;
2296 static const int DEFAULT_DEBUG_LEVEL = 1;
2297
2298 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2299 void help() YS_OVERRIDE
2300 {
2301 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2302 log("\n");
2303 log(" write_cxxrtl [options] [filename]\n");
2304 log("\n");
2305 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2306 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2307 log("\n");
2308 log("The following driver may be used as an example for a design with a single clock\n");
2309 log("driving rising edge triggered flip-flops:\n");
2310 log("\n");
2311 log(" #include \"top.cc\"\n");
2312 log("\n");
2313 log(" int main() {\n");
2314 log(" cxxrtl_design::p_top top;\n");
2315 log(" top.step();\n");
2316 log(" while (1) {\n");
2317 log(" /* user logic */\n");
2318 log(" top.p_clk = value<1> {0u};\n");
2319 log(" top.step();\n");
2320 log(" top.p_clk = value<1> {1u};\n");
2321 log(" top.step();\n");
2322 log(" }\n");
2323 log(" }\n");
2324 log("\n");
2325 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2326 log("subject to race conditions. If, in the example above, the user logic would run\n");
2327 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2328 log("\n");
2329 log("This backend supports replacing parts of the design with black boxes implemented\n");
2330 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2331 log("and the generated code consists only of an interface and a factory function.\n");
2332 log("The driver must implement the factory function that creates an implementation of\n");
2333 log("the black box, taking into account the parameters it is instantiated with.\n");
2334 log("\n");
2335 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2336 log("a synchronous debug sink:\n");
2337 log("\n");
2338 log(" (* cxxrtl_blackbox *)\n");
2339 log(" module debug(...);\n");
2340 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2341 log(" input en;\n");
2342 log(" input [7:0] i_data;\n");
2343 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2344 log(" endmodule\n");
2345 log("\n");
2346 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2347 log("\n");
2348 log(" struct bb_p_debug : public module {\n");
2349 log(" value<1> p_clk;\n");
2350 log(" bool posedge_p_clk() const { /* ... */ }\n");
2351 log(" value<1> p_en;\n");
2352 log(" value<8> p_i_data;\n");
2353 log(" wire<8> p_o_data;\n");
2354 log("\n");
2355 log(" bool eval() override;\n");
2356 log(" bool commit() override;\n");
2357 log("\n");
2358 log(" static std::unique_ptr<bb_p_debug>\n");
2359 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2360 log(" };\n");
2361 log("\n");
2362 log("The `create' function must be implemented by the driver. For example, it could\n");
2363 log("always provide an implementation logging the values to standard error stream:\n");
2364 log("\n");
2365 log(" namespace cxxrtl_design {\n");
2366 log("\n");
2367 log(" struct stderr_debug : public bb_p_debug {\n");
2368 log(" bool eval() override {\n");
2369 log(" if (posedge_p_clk() && p_en)\n");
2370 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2371 log(" p_o_data.next = p_i_data;\n");
2372 log(" return bb_p_debug::eval();\n");
2373 log(" }\n");
2374 log(" };\n");
2375 log("\n");
2376 log(" std::unique_ptr<bb_p_debug>\n");
2377 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2378 log(" cxxrtl::metadata_map attributes) {\n");
2379 log(" return std::make_unique<stderr_debug>();\n");
2380 log(" }\n");
2381 log("\n");
2382 log(" }\n");
2383 log("\n");
2384 log("For complex applications of black boxes, it is possible to parameterize their\n");
2385 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2386 log("interface for a configurable width debug sink:\n");
2387 log("\n");
2388 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2389 log(" module debug(...);\n");
2390 log(" parameter WIDTH = 8;\n");
2391 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2392 log(" input en;\n");
2393 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2394 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2395 log(" endmodule\n");
2396 log("\n");
2397 log("For this parametric HDL interface, this backend will generate the following C++\n");
2398 log("interface (only the differences are shown):\n");
2399 log("\n");
2400 log(" template<size_t WIDTH>\n");
2401 log(" struct bb_p_debug : public module {\n");
2402 log(" // ...\n");
2403 log(" value<WIDTH> p_i_data;\n");
2404 log(" wire<WIDTH> p_o_data;\n");
2405 log(" // ...\n");
2406 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2407 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2408 log(" };\n");
2409 log("\n");
2410 log("The `create' function must be implemented by the driver, specialized for every\n");
2411 log("possible combination of template parameters. (Specialization is necessary to\n");
2412 log("enable separate compilation of generated code and black box implementations.)\n");
2413 log("\n");
2414 log(" template<size_t SIZE>\n");
2415 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2416 log(" // ...\n");
2417 log(" };\n");
2418 log("\n");
2419 log(" template<>\n");
2420 log(" std::unique_ptr<bb_p_debug<8>>\n");
2421 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2422 log(" cxxrtl::metadata_map attributes) {\n");
2423 log(" return std::make_unique<stderr_debug<8>>();\n");
2424 log(" }\n");
2425 log("\n");
2426 log("The following attributes are recognized by this backend:\n");
2427 log("\n");
2428 log(" cxxrtl_blackbox\n");
2429 log(" only valid on modules. if specified, the module contents are ignored,\n");
2430 log(" and the generated code includes only the module interface and a factory\n");
2431 log(" function, which will be called to instantiate the module.\n");
2432 log("\n");
2433 log(" cxxrtl_edge\n");
2434 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2435 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2436 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2437 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2438 log("\n");
2439 log(" cxxrtl_template\n");
2440 log(" only valid on black boxes. must contain a space separated sequence of\n");
2441 log(" identifiers that have a corresponding black box parameters. for each\n");
2442 log(" of them, the generated code includes a `size_t` template parameter.\n");
2443 log("\n");
2444 log(" cxxrtl_width\n");
2445 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2446 log(" is directly inserted into generated code.\n");
2447 log("\n");
2448 log(" cxxrtl_comb, cxxrtl_sync\n");
2449 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2450 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2451 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2452 log(" if neither is specified, the output will be pessimistically treated as\n");
2453 log(" driven by both combinatorial and synchronous logic.\n");
2454 log("\n");
2455 log("The following options are supported by this backend:\n");
2456 log("\n");
2457 log(" -header\n");
2458 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2459 log(" if specified, the backend must be called with a filename, and filename\n");
2460 log(" of the interface is derived from filename of the implementation.\n");
2461 log(" otherwise, interface and implementation are generated together.\n");
2462 log("\n");
2463 log(" -namespace <ns-name>\n");
2464 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2465 log(" \"cxxrtl_design\" is used.\n");
2466 log("\n");
2467 log(" -O <level>\n");
2468 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2469 log(" levels dramatically decrease compile and run time, and highest level\n");
2470 log(" possible for a design should be used.\n");
2471 log("\n");
2472 log(" -O0\n");
2473 log(" no optimization.\n");
2474 log("\n");
2475 log(" -O1\n");
2476 log(" elide internal wires if possible.\n");
2477 log("\n");
2478 log(" -O2\n");
2479 log(" like -O1, and localize internal wires if possible.\n");
2480 log("\n");
2481 log(" -O3\n");
2482 log(" like -O2, and elide public wires not marked (*keep*) if possible.\n");
2483 log("\n");
2484 log(" -O4\n");
2485 log(" like -O3, and localize public wires not marked (*keep*) if possible.\n");
2486 log("\n");
2487 log(" -O5\n");
2488 log(" like -O4, and run `proc; flatten` first.\n");
2489 log("\n");
2490 log(" -g <level>\n");
2491 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2492 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2493 log("\n");
2494 log(" -g0\n");
2495 log(" no debug information.\n");
2496 log("\n");
2497 log(" -g1\n");
2498 log(" debug information for non-optimized public wires. this also makes it\n");
2499 log(" possible to use the C API.\n");
2500 log("\n");
2501 }
2502
2503 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
2504 {
2505 int opt_level = DEFAULT_OPT_LEVEL;
2506 int debug_level = DEFAULT_DEBUG_LEVEL;
2507 CxxrtlWorker worker;
2508
2509 log_header(design, "Executing CXXRTL backend.\n");
2510
2511 size_t argidx;
2512 for (argidx = 1; argidx < args.size(); argidx++)
2513 {
2514 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2515 opt_level = std::stoi(args[++argidx]);
2516 continue;
2517 }
2518 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2519 opt_level = std::stoi(args[argidx].substr(2));
2520 continue;
2521 }
2522 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2523 debug_level = std::stoi(args[++argidx]);
2524 continue;
2525 }
2526 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2527 debug_level = std::stoi(args[argidx].substr(2));
2528 continue;
2529 }
2530 if (args[argidx] == "-header") {
2531 worker.split_intf = true;
2532 continue;
2533 }
2534 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2535 worker.design_ns = args[++argidx];
2536 continue;
2537 }
2538 break;
2539 }
2540 extra_args(f, filename, args, argidx);
2541
2542 switch (opt_level) {
2543 // the highest level here must match DEFAULT_OPT_LEVEL
2544 case 5:
2545 worker.max_opt_level = true;
2546 worker.run_proc_flatten = true;
2547 YS_FALLTHROUGH
2548 case 4:
2549 worker.localize_public = true;
2550 YS_FALLTHROUGH
2551 case 3:
2552 worker.elide_public = true;
2553 YS_FALLTHROUGH
2554 case 2:
2555 worker.localize_internal = true;
2556 YS_FALLTHROUGH
2557 case 1:
2558 worker.elide_internal = true;
2559 YS_FALLTHROUGH
2560 case 0:
2561 break;
2562 default:
2563 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2564 }
2565
2566 switch (debug_level) {
2567 // the highest level here must match DEFAULT_DEBUG_LEVEL
2568 case 1:
2569 worker.debug_info = true;
2570 YS_FALLTHROUGH
2571 case 0:
2572 break;
2573 default:
2574 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2575 }
2576
2577 std::ofstream intf_f;
2578 if (worker.split_intf) {
2579 if (filename == "<stdout>")
2580 log_cmd_error("Option -header must be used with a filename.\n");
2581
2582 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2583 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2584 if (intf_f.fail())
2585 log_cmd_error("Can't open file `%s' for writing: %s\n",
2586 worker.intf_filename.c_str(), strerror(errno));
2587
2588 worker.intf_f = &intf_f;
2589 }
2590 worker.impl_f = f;
2591
2592 worker.prepare_design(design);
2593 worker.dump_design(design);
2594 }
2595 } CxxrtlBackend;
2596
2597 PRIVATE_NAMESPACE_END