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Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/log.h"
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 // [[CITE]]
31 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
32 // Information Processing Letters, Vol. 47, pp 319-323, 1993
33 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
34
35 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
36 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
37 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
38 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
39 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
40 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
41 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
42 template<class T>
43 struct Scheduler {
44 struct Vertex {
45 T *data;
46 Vertex *prev, *next;
47 pool<Vertex*, hash_ptr_ops> preds, succs;
48
49 Vertex() : data(NULL), prev(this), next(this) {}
50 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
51
52 bool empty() const
53 {
54 log_assert(data == NULL);
55 if (next == this) {
56 log_assert(prev == next);
57 return true;
58 }
59 return false;
60 }
61
62 void link(Vertex *list)
63 {
64 log_assert(prev == NULL && next == NULL);
65 next = list;
66 prev = list->prev;
67 list->prev->next = this;
68 list->prev = this;
69 }
70
71 void unlink()
72 {
73 log_assert(prev->next == this && next->prev == this);
74 prev->next = next;
75 next->prev = prev;
76 next = prev = NULL;
77 }
78
79 int delta() const
80 {
81 return succs.size() - preds.size();
82 }
83 };
84
85 std::vector<Vertex*> vertices;
86 Vertex *sources = new Vertex;
87 Vertex *sinks = new Vertex;
88 dict<int, Vertex*> bins;
89
90 ~Scheduler()
91 {
92 delete sources;
93 delete sinks;
94 for (auto bin : bins)
95 delete bin.second;
96 for (auto vertex : vertices)
97 delete vertex;
98 }
99
100 Vertex *add(T *data)
101 {
102 Vertex *vertex = new Vertex(data);
103 vertices.push_back(vertex);
104 return vertex;
105 }
106
107 void relink(Vertex *vertex)
108 {
109 if (vertex->succs.empty())
110 vertex->link(sinks);
111 else if (vertex->preds.empty())
112 vertex->link(sources);
113 else {
114 int delta = vertex->delta();
115 if (!bins.count(delta))
116 bins[delta] = new Vertex;
117 vertex->link(bins[delta]);
118 }
119 }
120
121 Vertex *remove(Vertex *vertex)
122 {
123 vertex->unlink();
124 for (auto pred : vertex->preds) {
125 if (pred == vertex)
126 continue;
127 log_assert(pred->succs[vertex]);
128 pred->unlink();
129 pred->succs.erase(vertex);
130 relink(pred);
131 }
132 for (auto succ : vertex->succs) {
133 if (succ == vertex)
134 continue;
135 log_assert(succ->preds[vertex]);
136 succ->unlink();
137 succ->preds.erase(vertex);
138 relink(succ);
139 }
140 vertex->preds.clear();
141 vertex->succs.clear();
142 return vertex;
143 }
144
145 std::vector<Vertex*> schedule()
146 {
147 std::vector<Vertex*> s1, s2r;
148 for (auto vertex : vertices)
149 relink(vertex);
150 bool bins_empty = false;
151 while (!(sinks->empty() && sources->empty() && bins_empty)) {
152 while (!sinks->empty())
153 s2r.push_back(remove(sinks->next));
154 while (!sources->empty())
155 s1.push_back(remove(sources->next));
156 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
157 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
158 // naive implementation of find-max-key.
159 bins_empty = true;
160 bins.template sort<std::greater<int>>();
161 for (auto bin : bins) {
162 if (!bin.second->empty()) {
163 bins_empty = false;
164 s1.push_back(remove(bin.second->next));
165 break;
166 }
167 }
168 }
169 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
170 return s1;
171 }
172 };
173
174 bool is_unary_cell(RTLIL::IdString type)
175 {
176 return type.in(
177 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
178 ID($pos), ID($neg));
179 }
180
181 bool is_binary_cell(RTLIL::IdString type)
182 {
183 return type.in(
184 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
185 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
186 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
187 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
188 }
189
190 bool is_extending_cell(RTLIL::IdString type)
191 {
192 return !type.in(
193 ID($logic_not), ID($logic_and), ID($logic_or),
194 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
195 }
196
197 bool is_elidable_cell(RTLIL::IdString type)
198 {
199 return is_unary_cell(type) || is_binary_cell(type) || type.in(
200 ID($mux), ID($concat), ID($slice), ID($pmux));
201 }
202
203 bool is_sync_ff_cell(RTLIL::IdString type)
204 {
205 return type.in(
206 ID($dff), ID($dffe));
207 }
208
209 bool is_ff_cell(RTLIL::IdString type)
210 {
211 return is_sync_ff_cell(type) || type.in(
212 ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
213 }
214
215 bool is_internal_cell(RTLIL::IdString type)
216 {
217 return type[0] == '$' && !type.begins_with("$paramod");
218 }
219
220 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
221 {
222 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
223 log_assert(cell_module != nullptr);
224 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
225 }
226
227 enum class CxxrtlPortType {
228 UNKNOWN = 0, // or mixed comb/sync
229 COMB = 1,
230 SYNC = 2,
231 };
232
233 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
234 {
235 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
236 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
237 return CxxrtlPortType::UNKNOWN;
238 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
239 log_assert(cell_output_wire != nullptr);
240 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
241 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
242 if (is_comb && is_sync)
243 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
244 log_id(cell_module), log_signal(cell_output_wire));
245 else if (is_comb)
246 return CxxrtlPortType::COMB;
247 else if (is_sync)
248 return CxxrtlPortType::SYNC;
249 return CxxrtlPortType::UNKNOWN;
250 }
251
252 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
253 {
254 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
255 }
256
257 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
258 {
259 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
260 }
261
262 struct FlowGraph {
263 struct Node {
264 enum class Type {
265 CONNECT,
266 CELL_SYNC,
267 CELL_EVAL,
268 PROCESS
269 };
270
271 Type type;
272 RTLIL::SigSig connect = {};
273 const RTLIL::Cell *cell = NULL;
274 const RTLIL::Process *process = NULL;
275 };
276
277 std::vector<Node*> nodes;
278 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
279 dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
280
281 ~FlowGraph()
282 {
283 for (auto node : nodes)
284 delete node;
285 }
286
287 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool fully_sync, bool elidable)
288 {
289 for (auto chunk : sig.chunks())
290 if (chunk.wire) {
291 if (fully_sync)
292 wire_sync_defs[chunk.wire].insert(node);
293 else
294 wire_comb_defs[chunk.wire].insert(node);
295 }
296 // Only comb defs of an entire wire in the right order can be elided.
297 if (!fully_sync && sig.is_wire())
298 wire_def_elidable[sig.as_wire()] = elidable;
299 }
300
301 void add_uses(Node *node, const RTLIL::SigSpec &sig)
302 {
303 for (auto chunk : sig.chunks())
304 if (chunk.wire) {
305 wire_uses[chunk.wire].insert(node);
306 // Only a single use of an entire wire in the right order can be elided.
307 // (But the use can include other chunks.)
308 if (!wire_use_elidable.count(chunk.wire))
309 wire_use_elidable[chunk.wire] = true;
310 else
311 wire_use_elidable[chunk.wire] = false;
312 }
313 }
314
315 bool is_elidable(const RTLIL::Wire *wire) const
316 {
317 if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire))
318 return wire_def_elidable.at(wire) && wire_use_elidable.at(wire);
319 return false;
320 }
321
322 // Connections
323 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
324 {
325 add_defs(node, conn.first, /*fully_sync=*/false, /*elidable=*/true);
326 add_uses(node, conn.second);
327 }
328
329 Node *add_node(const RTLIL::SigSig &conn)
330 {
331 Node *node = new Node;
332 node->type = Node::Type::CONNECT;
333 node->connect = conn;
334 nodes.push_back(node);
335 add_connect_defs_uses(node, conn);
336 return node;
337 }
338
339 // Cells
340 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
341 {
342 // To understand why this node type is necessary and why it produces comb defs, consider a cell
343 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
344 // not result in a feedback arc because the output is synchronous. However, a naive implementation
345 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
346 // would not be able to immediately converge...
347 //
348 // wire<1> i_tmp;
349 // cell->p_i = i_tmp.curr;
350 // cell->eval();
351 // i_tmp.next = cell->p_o.curr;
352 //
353 // ... since the wire connecting the input and output ports would not be localizable. To solve
354 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
355 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
356 //
357 // value<1> i_tmp;
358 // i_tmp = cell->p_o.curr;
359 // cell->p_i = i_tmp;
360 // cell->eval();
361 //
362 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
363 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
364 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
365 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
366 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
367 // and the left-hand side has a comb def.
368 for (auto conn : cell->connections())
369 if (cell->output(conn.first))
370 if (is_cxxrtl_sync_port(cell, conn.first)) {
371 // See note regarding elidability below.
372 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
373 }
374 }
375
376 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
377 {
378 for (auto conn : cell->connections()) {
379 if (cell->output(conn.first)) {
380 if (is_elidable_cell(cell->type))
381 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/true);
382 else if (is_sync_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
383 add_defs(node, conn.second, /*fully_sync=*/true, /*elidable=*/false);
384 else if (is_internal_cell(cell->type))
385 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
386 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
387 // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
388 // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
389 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
390 // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
391 // the infrastructure required to elide outputs of cells with many of them.
392 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
393 }
394 }
395 if (cell->input(conn.first))
396 add_uses(node, conn.second);
397 }
398 }
399
400 Node *add_node(const RTLIL::Cell *cell)
401 {
402 log_assert(cell->known());
403
404 bool has_fully_sync_outputs = false;
405 for (auto conn : cell->connections())
406 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
407 has_fully_sync_outputs = true;
408 break;
409 }
410 if (has_fully_sync_outputs) {
411 Node *node = new Node;
412 node->type = Node::Type::CELL_SYNC;
413 node->cell = cell;
414 nodes.push_back(node);
415 add_cell_sync_defs(node, cell);
416 }
417
418 Node *node = new Node;
419 node->type = Node::Type::CELL_EVAL;
420 node->cell = cell;
421 nodes.push_back(node);
422 add_cell_eval_defs_uses(node, cell);
423 return node;
424 }
425
426 // Processes
427 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
428 {
429 for (auto &action : case_->actions) {
430 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
431 add_uses(node, action.second);
432 }
433 for (auto sub_switch : case_->switches) {
434 add_uses(node, sub_switch->signal);
435 for (auto sub_case : sub_switch->cases) {
436 for (auto &compare : sub_case->compare)
437 add_uses(node, compare);
438 add_case_defs_uses(node, sub_case);
439 }
440 }
441 }
442
443 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
444 {
445 add_case_defs_uses(node, &process->root_case);
446 for (auto sync : process->syncs)
447 for (auto action : sync->actions) {
448 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
449 add_defs(node, action.first, /*is_sync=*/true, /*elidable=*/false);
450 else
451 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
452 add_uses(node, action.second);
453 }
454 }
455
456 Node *add_node(const RTLIL::Process *process)
457 {
458 Node *node = new Node;
459 node->type = Node::Type::PROCESS;
460 node->process = process;
461 nodes.push_back(node);
462 add_process_defs_uses(node, process);
463 return node;
464 }
465 };
466
467 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
468 {
469 std::vector<std::string> result;
470 size_t prev = 0;
471 while (true) {
472 size_t curr = str.find_first_of(sep, prev);
473 if (curr == std::string::npos) {
474 std::string part = str.substr(prev);
475 if (!part.empty()) result.push_back(part);
476 break;
477 } else {
478 std::string part = str.substr(prev, curr - prev);
479 if (!part.empty()) result.push_back(part);
480 prev = curr + 1;
481 }
482 }
483 return result;
484 }
485
486 std::string escape_cxx_string(const std::string &input)
487 {
488 std::string output = "\"";
489 for (auto c : input) {
490 if (::isprint(c)) {
491 if (c == '\\')
492 output.push_back('\\');
493 output.push_back(c);
494 } else {
495 char l = c & 0xf, h = (c >> 4) & 0xf;
496 output.append("\\x");
497 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
498 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
499 }
500 }
501 output.push_back('"');
502 if (output.find('\0') != std::string::npos) {
503 output.insert(0, "std::string {");
504 output.append(stringf(", %zu}", input.size()));
505 }
506 return output;
507 }
508
509 template<class T>
510 std::string get_hdl_name(T *object)
511 {
512 if (object->has_attribute(ID::hdlname))
513 return object->get_string_attribute(ID::hdlname);
514 else
515 return object->name.str().substr(1);
516 }
517
518 struct CxxrtlWorker {
519 bool split_intf = false;
520 std::string intf_filename;
521 std::string design_ns = "cxxrtl_design";
522 std::ostream *impl_f = nullptr;
523 std::ostream *intf_f = nullptr;
524
525 bool run_flatten = false;
526 bool run_proc = false;
527
528 bool unbuffer_internal = false;
529 bool unbuffer_public = false;
530 bool localize_internal = false;
531 bool localize_public = false;
532 bool elide_internal = false;
533 bool elide_public = false;
534
535 bool debug_info = false;
536
537 std::ostringstream f;
538 std::string indent;
539 int temporary = 0;
540
541 dict<const RTLIL::Module*, SigMap> sigmaps;
542 pool<const RTLIL::Wire*> edge_wires;
543 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
544 pool<const RTLIL::Memory*> writable_memories;
545 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
546 dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
547 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
548 pool<const RTLIL::Wire*> unbuffered_wires;
549 pool<const RTLIL::Wire*> localized_wires;
550 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
551 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
552 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
553 dict<const RTLIL::Module*, bool> eval_converges;
554
555 void inc_indent() {
556 indent += "\t";
557 }
558 void dec_indent() {
559 indent.resize(indent.size() - 1);
560 }
561
562 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
563 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
564 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
565 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
566 // 1. All generated identifiers start with `_`.
567 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
568 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
569 // 2. An underscore is escaped with another underscore, i.e. `__`.
570 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
571 std::string mangle_name(const RTLIL::IdString &name)
572 {
573 std::string mangled;
574 bool first = true;
575 for (char c : name.str()) {
576 if (first) {
577 first = false;
578 if (c == '\\')
579 mangled += "p_";
580 else if (c == '$')
581 mangled += "i_";
582 else
583 log_assert(false);
584 } else {
585 if (isalnum(c)) {
586 mangled += c;
587 } else if (c == '_') {
588 mangled += "__";
589 } else {
590 char l = c & 0xf, h = (c >> 4) & 0xf;
591 mangled += '_';
592 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
593 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
594 mangled += '_';
595 }
596 }
597 }
598 return mangled;
599 }
600
601 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
602 {
603 // Class namespace.
604 if (is_blackbox)
605 return "bb_" + mangle_name(name);
606 return mangle_name(name);
607 }
608
609 std::string mangle_memory_name(const RTLIL::IdString &name)
610 {
611 // Class member namespace.
612 return "memory_" + mangle_name(name);
613 }
614
615 std::string mangle_cell_name(const RTLIL::IdString &name)
616 {
617 // Class member namespace.
618 return "cell_" + mangle_name(name);
619 }
620
621 std::string mangle_wire_name(const RTLIL::IdString &name)
622 {
623 // Class member namespace.
624 return mangle_name(name);
625 }
626
627 std::string mangle(const RTLIL::Module *module)
628 {
629 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
630 }
631
632 std::string mangle(const RTLIL::Memory *memory)
633 {
634 return mangle_memory_name(memory->name);
635 }
636
637 std::string mangle(const RTLIL::Cell *cell)
638 {
639 return mangle_cell_name(cell->name);
640 }
641
642 std::string mangle(const RTLIL::Wire *wire)
643 {
644 return mangle_wire_name(wire->name);
645 }
646
647 std::string mangle(RTLIL::SigBit sigbit)
648 {
649 log_assert(sigbit.wire != NULL);
650 if (sigbit.wire->width == 1)
651 return mangle(sigbit.wire);
652 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
653 }
654
655 std::vector<std::string> template_param_names(const RTLIL::Module *module)
656 {
657 if (!module->has_attribute(ID(cxxrtl_template)))
658 return {};
659
660 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
661 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
662
663 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
664 for (const auto &param_name : param_names) {
665 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
666 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
667 // in both Verilog and C++, anyway.)
668 if (!isupper(param_name[0]))
669 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
670 "which does not start with an uppercase letter.\n",
671 log_id(module), param_name.c_str());
672 }
673 return param_names;
674 }
675
676 std::string template_params(const RTLIL::Module *module, bool is_decl)
677 {
678 std::vector<std::string> param_names = template_param_names(module);
679 if (param_names.empty())
680 return "";
681
682 std::string params = "<";
683 bool first = true;
684 for (const auto &param_name : param_names) {
685 if (!first)
686 params += ", ";
687 first = false;
688 if (is_decl)
689 params += "size_t ";
690 params += param_name;
691 }
692 params += ">";
693 return params;
694 }
695
696 std::string template_args(const RTLIL::Cell *cell)
697 {
698 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
699 log_assert(cell_module != nullptr);
700 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
701 return "";
702
703 std::vector<std::string> param_names = template_param_names(cell_module);
704 if (param_names.empty())
705 return "";
706
707 std::string params = "<";
708 bool first = true;
709 for (const auto &param_name : param_names) {
710 if (!first)
711 params += ", ";
712 first = false;
713 params += "/*" + param_name + "=*/";
714 RTLIL::IdString id_param_name = '\\' + param_name;
715 if (!cell->hasParam(id_param_name))
716 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
717 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
718 RTLIL::Const param_value = cell->getParam(id_param_name);
719 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
720 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
721 "is not a positive integer.\n",
722 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
723 params += std::to_string(cell->getParam(id_param_name).as_int());
724 }
725 params += ">";
726 return params;
727 }
728
729 std::string fresh_temporary()
730 {
731 return stringf("tmp_%d", temporary++);
732 }
733
734 void dump_attrs(const RTLIL::AttrObject *object)
735 {
736 for (auto attr : object->attributes) {
737 f << indent << "// " << attr.first.str() << ": ";
738 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
739 f << attr.second.decode_string();
740 } else {
741 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
742 }
743 f << "\n";
744 }
745 }
746
747 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
748 {
749 const int CHUNK_SIZE = 32;
750 f << "{";
751 while (width > 0) {
752 int chunk_width = min(width, CHUNK_SIZE);
753 uint32_t chunk = data.extract(offset, chunk_width).as_int();
754 if (fixed_width)
755 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
756 else
757 f << stringf("%#xu", chunk);
758 if (width > CHUNK_SIZE)
759 f << ',';
760 offset += CHUNK_SIZE;
761 width -= CHUNK_SIZE;
762 }
763 f << "}";
764 }
765
766 void dump_const_init(const RTLIL::Const &data)
767 {
768 dump_const_init(data, data.size());
769 }
770
771 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
772 {
773 f << "value<" << width << ">";
774 dump_const_init(data, width, offset, fixed_width);
775 }
776
777 void dump_const(const RTLIL::Const &data)
778 {
779 dump_const(data, data.size());
780 }
781
782 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs)
783 {
784 if (chunk.wire == NULL) {
785 dump_const(chunk.data, chunk.width, chunk.offset);
786 return false;
787 } else {
788 if (elided_wires.count(chunk.wire)) {
789 log_assert(!is_lhs);
790 const FlowGraph::Node &node = elided_wires[chunk.wire];
791 switch (node.type) {
792 case FlowGraph::Node::Type::CONNECT:
793 dump_connect_elided(node.connect);
794 break;
795 case FlowGraph::Node::Type::CELL_EVAL:
796 log_assert(is_elidable_cell(node.cell->type));
797 dump_cell_elided(node.cell);
798 break;
799 default:
800 log_assert(false);
801 }
802 } else if (unbuffered_wires[chunk.wire]) {
803 f << mangle(chunk.wire);
804 } else {
805 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
806 }
807 if (chunk.width == chunk.wire->width && chunk.offset == 0)
808 return false;
809 else if (chunk.width == 1)
810 f << ".slice<" << chunk.offset << ">()";
811 else
812 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
813 return true;
814 }
815 }
816
817 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs)
818 {
819 if (sig.empty()) {
820 f << "value<0>()";
821 return false;
822 } else if (sig.is_chunk()) {
823 return dump_sigchunk(sig.as_chunk(), is_lhs);
824 } else {
825 dump_sigchunk(*sig.chunks().rbegin(), is_lhs);
826 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
827 f << ".concat(";
828 dump_sigchunk(*it, is_lhs);
829 f << ")";
830 }
831 return true;
832 }
833 }
834
835 void dump_sigspec_lhs(const RTLIL::SigSpec &sig)
836 {
837 dump_sigspec(sig, /*is_lhs=*/true);
838 }
839
840 void dump_sigspec_rhs(const RTLIL::SigSpec &sig)
841 {
842 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
843 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
844 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
845 // type conversion, but only if the expression needs it.
846 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false);
847 if (is_complex)
848 f << ".val()";
849 }
850
851 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
852 {
853 for (auto chunk : sig.chunks()) {
854 if (!chunk.wire || !elided_wires.count(chunk.wire))
855 continue;
856
857 const FlowGraph::Node &node = elided_wires[chunk.wire];
858 switch (node.type) {
859 case FlowGraph::Node::Type::CONNECT:
860 collect_connect(node.connect, cells);
861 break;
862 case FlowGraph::Node::Type::CELL_EVAL:
863 collect_cell_eval(node.cell, cells);
864 break;
865 default:
866 log_assert(false);
867 }
868 }
869 }
870
871 void dump_connect_elided(const RTLIL::SigSig &conn)
872 {
873 dump_sigspec_rhs(conn.second);
874 }
875
876 bool is_connect_elided(const RTLIL::SigSig &conn)
877 {
878 return conn.first.is_wire() && elided_wires.count(conn.first.as_wire());
879 }
880
881 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
882 {
883 if (!is_connect_elided(conn))
884 return;
885
886 collect_sigspec_rhs(conn.second, cells);
887 }
888
889 void dump_connect(const RTLIL::SigSig &conn)
890 {
891 if (is_connect_elided(conn))
892 return;
893
894 f << indent << "// connection\n";
895 f << indent;
896 dump_sigspec_lhs(conn.first);
897 f << " = ";
898 dump_connect_elided(conn);
899 f << ";\n";
900 }
901
902 void dump_cell_sync(const RTLIL::Cell *cell)
903 {
904 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
905 f << indent << "// cell " << cell->name.str() << " syncs\n";
906 for (auto conn : cell->connections())
907 if (cell->output(conn.first))
908 if (is_cxxrtl_sync_port(cell, conn.first)) {
909 f << indent;
910 dump_sigspec_lhs(conn.second);
911 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
912 }
913 }
914
915 void dump_cell_elided(const RTLIL::Cell *cell)
916 {
917 // Unary cells
918 if (is_unary_cell(cell->type)) {
919 f << cell->type.substr(1);
920 if (is_extending_cell(cell->type))
921 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
922 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
923 dump_sigspec_rhs(cell->getPort(ID::A));
924 f << ")";
925 // Binary cells
926 } else if (is_binary_cell(cell->type)) {
927 f << cell->type.substr(1);
928 if (is_extending_cell(cell->type))
929 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
930 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
931 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
932 dump_sigspec_rhs(cell->getPort(ID::A));
933 f << ", ";
934 dump_sigspec_rhs(cell->getPort(ID::B));
935 f << ")";
936 // Muxes
937 } else if (cell->type == ID($mux)) {
938 f << "(";
939 dump_sigspec_rhs(cell->getPort(ID::S));
940 f << " ? ";
941 dump_sigspec_rhs(cell->getPort(ID::B));
942 f << " : ";
943 dump_sigspec_rhs(cell->getPort(ID::A));
944 f << ")";
945 // Parallel (one-hot) muxes
946 } else if (cell->type == ID($pmux)) {
947 int width = cell->getParam(ID::WIDTH).as_int();
948 int s_width = cell->getParam(ID::S_WIDTH).as_int();
949 for (int part = 0; part < s_width; part++) {
950 f << "(";
951 dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
952 f << " ? ";
953 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
954 f << " : ";
955 }
956 dump_sigspec_rhs(cell->getPort(ID::A));
957 for (int part = 0; part < s_width; part++) {
958 f << ")";
959 }
960 // Concats
961 } else if (cell->type == ID($concat)) {
962 dump_sigspec_rhs(cell->getPort(ID::B));
963 f << ".concat(";
964 dump_sigspec_rhs(cell->getPort(ID::A));
965 f << ").val()";
966 // Slices
967 } else if (cell->type == ID($slice)) {
968 dump_sigspec_rhs(cell->getPort(ID::A));
969 f << ".slice<";
970 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
971 f << ",";
972 f << cell->getParam(ID::OFFSET).as_int();
973 f << ">().val()";
974 } else {
975 log_assert(false);
976 }
977 }
978
979 bool is_cell_elided(const RTLIL::Cell *cell)
980 {
981 return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
982 elided_wires.count(cell->getPort(ID::Y).as_wire());
983 }
984
985 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
986 {
987 if (!is_cell_elided(cell))
988 return;
989
990 cells.push_back(cell->name);
991 for (auto port : cell->connections())
992 if (port.first != ID::Y)
993 collect_sigspec_rhs(port.second, cells);
994 }
995
996 void dump_cell_eval(const RTLIL::Cell *cell)
997 {
998 if (is_cell_elided(cell))
999 return;
1000 if (cell->type == ID($meminit))
1001 return; // Handled elsewhere.
1002
1003 std::vector<RTLIL::IdString> elided_cells;
1004 if (is_elidable_cell(cell->type)) {
1005 for (auto port : cell->connections())
1006 if (port.first != ID::Y)
1007 collect_sigspec_rhs(port.second, elided_cells);
1008 }
1009 if (elided_cells.empty()) {
1010 dump_attrs(cell);
1011 f << indent << "// cell " << cell->name.str() << "\n";
1012 } else {
1013 f << indent << "// cells";
1014 for (auto elided_cell : elided_cells)
1015 f << " " << elided_cell.str();
1016 f << "\n";
1017 }
1018
1019 // Elidable cells
1020 if (is_elidable_cell(cell->type)) {
1021 f << indent;
1022 dump_sigspec_lhs(cell->getPort(ID::Y));
1023 f << " = ";
1024 dump_cell_elided(cell);
1025 f << ";\n";
1026 // Flip-flops
1027 } else if (is_ff_cell(cell->type)) {
1028 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1029 // Edge-sensitive logic
1030 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1031 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1032 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1033 << mangle(clk_bit) << ") {\n";
1034 inc_indent();
1035 if (cell->type == ID($dffe)) {
1036 f << indent << "if (";
1037 dump_sigspec_rhs(cell->getPort(ID::EN));
1038 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1039 inc_indent();
1040 }
1041 f << indent;
1042 dump_sigspec_lhs(cell->getPort(ID::Q));
1043 f << " = ";
1044 dump_sigspec_rhs(cell->getPort(ID::D));
1045 f << ";\n";
1046 if (cell->type == ID($dffe)) {
1047 dec_indent();
1048 f << indent << "}\n";
1049 }
1050 dec_indent();
1051 f << indent << "}\n";
1052 } else if (cell->hasPort(ID::EN)) {
1053 // Level-sensitive logic
1054 f << indent << "if (";
1055 dump_sigspec_rhs(cell->getPort(ID::EN));
1056 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1057 inc_indent();
1058 f << indent;
1059 dump_sigspec_lhs(cell->getPort(ID::Q));
1060 f << " = ";
1061 dump_sigspec_rhs(cell->getPort(ID::D));
1062 f << ";\n";
1063 dec_indent();
1064 f << indent << "}\n";
1065 }
1066 if (cell->hasPort(ID::ARST)) {
1067 // Asynchronous reset (entire coarse cell at once)
1068 f << indent << "if (";
1069 dump_sigspec_rhs(cell->getPort(ID::ARST));
1070 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1071 inc_indent();
1072 f << indent;
1073 dump_sigspec_lhs(cell->getPort(ID::Q));
1074 f << " = ";
1075 dump_const(cell->getParam(ID::ARST_VALUE));
1076 f << ";\n";
1077 dec_indent();
1078 f << indent << "}\n";
1079 }
1080 if (cell->hasPort(ID::SET)) {
1081 // Asynchronous set (for individual bits)
1082 f << indent;
1083 dump_sigspec_lhs(cell->getPort(ID::Q));
1084 f << " = ";
1085 dump_sigspec_lhs(cell->getPort(ID::Q));
1086 f << ".update(";
1087 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1088 f << ", ";
1089 dump_sigspec_rhs(cell->getPort(ID::SET));
1090 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1091 }
1092 if (cell->hasPort(ID::CLR)) {
1093 // Asynchronous clear (for individual bits; priority over set)
1094 f << indent;
1095 dump_sigspec_lhs(cell->getPort(ID::Q));
1096 f << " = ";
1097 dump_sigspec_lhs(cell->getPort(ID::Q));
1098 f << ".update(";
1099 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1100 f << ", ";
1101 dump_sigspec_rhs(cell->getPort(ID::CLR));
1102 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1103 }
1104 // Memory ports
1105 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1106 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1107 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1108 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1109 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1110 << mangle(clk_bit) << ") {\n";
1111 inc_indent();
1112 }
1113 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1114 std::string valid_index_temp = fresh_temporary();
1115 f << indent << "auto " << valid_index_temp << " = memory_index(";
1116 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1117 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1118 if (cell->type == ID($memrd)) {
1119 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1120 if (has_enable) {
1121 f << indent << "if (";
1122 dump_sigspec_rhs(cell->getPort(ID::EN));
1123 f << ") {\n";
1124 inc_indent();
1125 }
1126 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1127 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1128 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -NDEBUG not
1129 // just for release builds, but also to make sure the simulator (which is presumably embedded in some
1130 // larger program) will never crash the code that calls into it.
1131 //
1132 // If assertions are disabled, out of bounds reads are defined to return zero.
1133 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1134 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1135 inc_indent();
1136 if (writable_memories[memory]) {
1137 std::string lhs_temp = fresh_temporary();
1138 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1139 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1140 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1141 if (!memwr_cells.empty()) {
1142 std::string addr_temp = fresh_temporary();
1143 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1144 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1145 f << ";\n";
1146 std::sort(memwr_cells.begin(), memwr_cells.end(),
1147 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1148 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1149 });
1150 for (auto memwr_cell : memwr_cells) {
1151 f << indent << "if (" << addr_temp << " == ";
1152 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1153 f << ") {\n";
1154 inc_indent();
1155 f << indent << lhs_temp << " = " << lhs_temp;
1156 f << ".update(";
1157 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1158 f << ", ";
1159 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1160 f << ");\n";
1161 dec_indent();
1162 f << indent << "}\n";
1163 }
1164 }
1165 f << indent;
1166 dump_sigspec_lhs(cell->getPort(ID::DATA));
1167 f << " = " << lhs_temp << ";\n";
1168 } else {
1169 f << indent;
1170 dump_sigspec_lhs(cell->getPort(ID::DATA));
1171 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1172 }
1173 dec_indent();
1174 f << indent << "} else {\n";
1175 inc_indent();
1176 f << indent;
1177 dump_sigspec_lhs(cell->getPort(ID::DATA));
1178 f << " = value<" << memory->width << "> {};\n";
1179 dec_indent();
1180 f << indent << "}\n";
1181 if (has_enable) {
1182 dec_indent();
1183 f << indent << "}\n";
1184 }
1185 } else /*if (cell->type == ID($memwr))*/ {
1186 log_assert(writable_memories[memory]);
1187 // See above for rationale of having both the assert and the condition.
1188 //
1189 // If assertions are disabled, out of bounds writes are defined to do nothing.
1190 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1191 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1192 inc_indent();
1193 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1194 dump_sigspec_rhs(cell->getPort(ID::DATA));
1195 f << ", ";
1196 dump_sigspec_rhs(cell->getPort(ID::EN));
1197 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1198 dec_indent();
1199 f << indent << "}\n";
1200 }
1201 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1202 dec_indent();
1203 f << indent << "}\n";
1204 }
1205 // Internal cells
1206 } else if (is_internal_cell(cell->type)) {
1207 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1208 // User cells
1209 } else {
1210 log_assert(cell->known());
1211 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1212 for (auto conn : cell->connections())
1213 if (cell->input(conn.first) && !cell->output(conn.first)) {
1214 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = ";
1215 dump_sigspec_rhs(conn.second);
1216 f << ";\n";
1217 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1218 // Until we have proper clock tree detection, this really awful hack that opportunistically
1219 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1220 // be if only one clock edge was simulated by replacing:
1221 // top.p_clk = value<1>{0u}; top.step();
1222 // top.p_clk = value<1>{1u}; top.step();
1223 // with:
1224 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1225 // Don't rely on this; it will be removed without warning.
1226 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1227 if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) {
1228 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1229 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1230 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1231 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1232 }
1233 }
1234 }
1235 } else if (cell->input(conn.first)) {
1236 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = ";
1237 dump_sigspec_rhs(conn.second);
1238 f << ";\n";
1239 }
1240 auto assign_from_outputs = [&](bool cell_converged) {
1241 for (auto conn : cell->connections()) {
1242 if (cell->output(conn.first)) {
1243 if (conn.second.empty())
1244 continue; // ignore disconnected ports
1245 if (is_cxxrtl_sync_port(cell, conn.first))
1246 continue; // fully sync ports are handled in CELL_SYNC nodes
1247 f << indent;
1248 dump_sigspec_lhs(conn.second);
1249 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1250 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1251 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1252 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1253 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1254 // and consider the fate of the localized wires that used to be output ports.)
1255 //
1256 // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell
1257 // (which may be late bound) will converge immediately. Because of this, the choice between using .curr
1258 // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime.
1259 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1260 f << ".next;\n";
1261 else
1262 f << ".curr;\n";
1263 }
1264 }
1265 };
1266 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1267 inc_indent();
1268 assign_from_outputs(/*cell_converged=*/true);
1269 dec_indent();
1270 f << indent << "} else {\n";
1271 inc_indent();
1272 f << indent << "converged = false;\n";
1273 assign_from_outputs(/*cell_converged=*/false);
1274 dec_indent();
1275 f << indent << "}\n";
1276 }
1277 }
1278
1279 void dump_assign(const RTLIL::SigSig &sigsig)
1280 {
1281 f << indent;
1282 dump_sigspec_lhs(sigsig.first);
1283 f << " = ";
1284 dump_sigspec_rhs(sigsig.second);
1285 f << ";\n";
1286 }
1287
1288 void dump_case_rule(const RTLIL::CaseRule *rule)
1289 {
1290 for (auto action : rule->actions)
1291 dump_assign(action);
1292 for (auto switch_ : rule->switches)
1293 dump_switch_rule(switch_);
1294 }
1295
1296 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1297 {
1298 // The switch attributes are printed before the switch condition is captured.
1299 dump_attrs(rule);
1300 std::string signal_temp = fresh_temporary();
1301 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1302 dump_sigspec(rule->signal, /*is_lhs=*/false);
1303 f << ";\n";
1304
1305 bool first = true;
1306 for (auto case_ : rule->cases) {
1307 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1308 dump_attrs(rule);
1309 f << indent;
1310 if (!first)
1311 f << "} else ";
1312 first = false;
1313 if (!case_->compare.empty()) {
1314 f << "if (";
1315 bool first = true;
1316 for (auto &compare : case_->compare) {
1317 if (!first)
1318 f << " || ";
1319 first = false;
1320 if (compare.is_fully_def()) {
1321 f << signal_temp << " == ";
1322 dump_sigspec(compare, /*is_lhs=*/false);
1323 } else if (compare.is_fully_const()) {
1324 RTLIL::Const compare_mask, compare_value;
1325 for (auto bit : compare.as_const()) {
1326 switch (bit) {
1327 case RTLIL::S0:
1328 case RTLIL::S1:
1329 compare_mask.bits.push_back(RTLIL::S1);
1330 compare_value.bits.push_back(bit);
1331 break;
1332
1333 case RTLIL::Sx:
1334 case RTLIL::Sz:
1335 case RTLIL::Sa:
1336 compare_mask.bits.push_back(RTLIL::S0);
1337 compare_value.bits.push_back(RTLIL::S0);
1338 break;
1339
1340 default:
1341 log_assert(false);
1342 }
1343 }
1344 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1345 dump_const(compare_mask);
1346 f << ") == ";
1347 dump_const(compare_value);
1348 } else {
1349 log_assert(false);
1350 }
1351 }
1352 f << ") ";
1353 }
1354 f << "{\n";
1355 inc_indent();
1356 dump_case_rule(case_);
1357 dec_indent();
1358 }
1359 f << indent << "}\n";
1360 }
1361
1362 void dump_process(const RTLIL::Process *proc)
1363 {
1364 dump_attrs(proc);
1365 f << indent << "// process " << proc->name.str() << "\n";
1366 // The case attributes (for root case) are always empty.
1367 log_assert(proc->root_case.attributes.empty());
1368 dump_case_rule(&proc->root_case);
1369 for (auto sync : proc->syncs) {
1370 RTLIL::SigBit sync_bit;
1371 if (!sync->signal.empty()) {
1372 sync_bit = sync->signal[0];
1373 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1374 }
1375
1376 pool<std::string> events;
1377 switch (sync->type) {
1378 case RTLIL::STp:
1379 log_assert(sync_bit.wire != nullptr);
1380 events.insert("posedge_" + mangle(sync_bit));
1381 break;
1382 case RTLIL::STn:
1383 log_assert(sync_bit.wire != nullptr);
1384 events.insert("negedge_" + mangle(sync_bit));
1385 break;
1386 case RTLIL::STe:
1387 log_assert(sync_bit.wire != nullptr);
1388 events.insert("posedge_" + mangle(sync_bit));
1389 events.insert("negedge_" + mangle(sync_bit));
1390 break;
1391
1392 case RTLIL::STa:
1393 events.insert("true");
1394 break;
1395
1396 case RTLIL::ST0:
1397 case RTLIL::ST1:
1398 case RTLIL::STg:
1399 case RTLIL::STi:
1400 log_assert(false);
1401 }
1402 if (!events.empty()) {
1403 f << indent << "if (";
1404 bool first = true;
1405 for (auto &event : events) {
1406 if (!first)
1407 f << " || ";
1408 first = false;
1409 f << event;
1410 }
1411 f << ") {\n";
1412 inc_indent();
1413 for (auto action : sync->actions)
1414 dump_assign(action);
1415 dec_indent();
1416 f << indent << "}\n";
1417 }
1418 }
1419 }
1420
1421 void dump_wire(const RTLIL::Wire *wire, bool is_local_context)
1422 {
1423 if (elided_wires.count(wire))
1424 return;
1425
1426 if (localized_wires[wire] && is_local_context) {
1427 dump_attrs(wire);
1428 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1429 }
1430 if (!localized_wires[wire] && !is_local_context) {
1431 std::string width;
1432 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1433 width = wire->get_string_attribute(ID(cxxrtl_width));
1434 } else {
1435 width = std::to_string(wire->width);
1436 }
1437
1438 dump_attrs(wire);
1439 f << indent;
1440 if (wire->port_input && wire->port_output)
1441 f << "/*inout*/ ";
1442 else if (wire->port_input)
1443 f << "/*input*/ ";
1444 else if (wire->port_output)
1445 f << "/*output*/ ";
1446 f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1447 if (wire->has_attribute(ID::init)) {
1448 f << " ";
1449 dump_const_init(wire->attributes.at(ID::init));
1450 }
1451 f << ";\n";
1452 if (edge_wires[wire]) {
1453 if (unbuffered_wires[wire]) {
1454 f << indent << "value<" << width << "> prev_" << mangle(wire);
1455 if (wire->has_attribute(ID::init)) {
1456 f << " ";
1457 dump_const_init(wire->attributes.at(ID::init));
1458 }
1459 f << ";\n";
1460 }
1461 for (auto edge_type : edge_types) {
1462 if (edge_type.first.wire == wire) {
1463 std::string prev, next;
1464 if (unbuffered_wires[wire]) {
1465 prev = "prev_" + mangle(edge_type.first.wire);
1466 next = mangle(edge_type.first.wire);
1467 } else {
1468 prev = mangle(edge_type.first.wire) + ".curr";
1469 next = mangle(edge_type.first.wire) + ".next";
1470 }
1471 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1472 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1473 if (edge_type.second != RTLIL::STn) {
1474 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1475 inc_indent();
1476 f << indent << "return !" << prev << " && " << next << ";\n";
1477 dec_indent();
1478 f << indent << "}\n";
1479 }
1480 if (edge_type.second != RTLIL::STp) {
1481 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1482 inc_indent();
1483 f << indent << "return " << prev << " && !" << next << ";\n";
1484 dec_indent();
1485 f << indent << "}\n";
1486 }
1487 }
1488 }
1489 }
1490 }
1491 }
1492
1493 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1494 {
1495 vector<const RTLIL::Cell*> init_cells;
1496 for (auto cell : module->cells())
1497 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1498 init_cells.push_back(cell);
1499
1500 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1501 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1502 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1503 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1504 });
1505
1506 dump_attrs(memory);
1507 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1508 << " { " << memory->size << "u";
1509 if (init_cells.empty()) {
1510 f << " };\n";
1511 } else {
1512 f << ",\n";
1513 inc_indent();
1514 for (auto cell : init_cells) {
1515 dump_attrs(cell);
1516 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1517 size_t width = cell->getParam(ID::WIDTH).as_int();
1518 size_t words = cell->getParam(ID::WORDS).as_int();
1519 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1520 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1521 inc_indent();
1522 for (size_t n = 0; n < words; n++) {
1523 if (n % 4 == 0)
1524 f << "\n" << indent;
1525 else
1526 f << " ";
1527 dump_const(data, width, n * width, /*fixed_width=*/true);
1528 f << ",";
1529 }
1530 dec_indent();
1531 f << "\n" << indent << "}},\n";
1532 }
1533 dec_indent();
1534 f << indent << "};\n";
1535 }
1536 }
1537
1538 void dump_eval_method(RTLIL::Module *module)
1539 {
1540 inc_indent();
1541 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1542 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1543 for (auto wire : module->wires()) {
1544 if (edge_wires[wire]) {
1545 for (auto edge_type : edge_types) {
1546 if (edge_type.first.wire == wire) {
1547 if (edge_type.second != RTLIL::STn) {
1548 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1549 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1550 }
1551 if (edge_type.second != RTLIL::STp) {
1552 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1553 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1554 }
1555 }
1556 }
1557 }
1558 }
1559 for (auto wire : module->wires())
1560 dump_wire(wire, /*is_local_context=*/true);
1561 for (auto node : schedule[module]) {
1562 switch (node.type) {
1563 case FlowGraph::Node::Type::CONNECT:
1564 dump_connect(node.connect);
1565 break;
1566 case FlowGraph::Node::Type::CELL_SYNC:
1567 dump_cell_sync(node.cell);
1568 break;
1569 case FlowGraph::Node::Type::CELL_EVAL:
1570 dump_cell_eval(node.cell);
1571 break;
1572 case FlowGraph::Node::Type::PROCESS:
1573 dump_process(node.process);
1574 break;
1575 }
1576 }
1577 }
1578 f << indent << "return converged;\n";
1579 dec_indent();
1580 }
1581
1582 void dump_commit_method(RTLIL::Module *module)
1583 {
1584 inc_indent();
1585 f << indent << "bool changed = false;\n";
1586 for (auto wire : module->wires()) {
1587 if (elided_wires.count(wire))
1588 continue;
1589 if (unbuffered_wires[wire]) {
1590 if (edge_wires[wire])
1591 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1592 continue;
1593 }
1594 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1595 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1596 }
1597 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1598 for (auto memory : module->memories) {
1599 if (!writable_memories[memory.second])
1600 continue;
1601 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1602 }
1603 for (auto cell : module->cells()) {
1604 if (is_internal_cell(cell->type))
1605 continue;
1606 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1607 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1608 }
1609 }
1610 f << indent << "return changed;\n";
1611 dec_indent();
1612 }
1613
1614 void dump_debug_info_method(RTLIL::Module *module)
1615 {
1616 size_t count_public_wires = 0;
1617 size_t count_const_wires = 0;
1618 size_t count_alias_wires = 0;
1619 size_t count_member_wires = 0;
1620 size_t count_skipped_wires = 0;
1621 inc_indent();
1622 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1623 for (auto wire : module->wires()) {
1624 if (wire->name[0] != '\\')
1625 continue;
1626 if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
1627 continue;
1628 count_public_wires++;
1629 if (debug_const_wires.count(wire)) {
1630 // Wire tied to a constant
1631 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1632 dump_const(debug_const_wires[wire]);
1633 f << ";\n";
1634 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1635 f << ", debug_item(const_" << mangle(wire) << ", ";
1636 f << wire->start_offset << "));\n";
1637 count_const_wires++;
1638 } else if (debug_alias_wires.count(wire)) {
1639 // Alias of a member wire
1640 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1641 f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
1642 f << wire->start_offset << "));\n";
1643 count_alias_wires++;
1644 } else if (!localized_wires.count(wire)) {
1645 // Member wire
1646 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1647 f << ", debug_item(" << mangle(wire) << ", ";
1648 f << wire->start_offset << "));\n";
1649 count_member_wires++;
1650 } else {
1651 count_skipped_wires++;
1652 }
1653 }
1654 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1655 for (auto &memory_it : module->memories) {
1656 if (memory_it.first[0] != '\\')
1657 continue;
1658 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1659 f << ", debug_item(" << mangle(memory_it.second) << ", ";
1660 f << memory_it.second->start_offset << "));\n";
1661 }
1662 for (auto cell : module->cells()) {
1663 if (is_internal_cell(cell->type))
1664 continue;
1665 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1666 f << indent << mangle(cell) << access << "debug_info(items, ";
1667 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1668 }
1669 }
1670 dec_indent();
1671
1672 log_debug("Debug information statistics for module `%s':\n", log_id(module));
1673 log_debug(" Public wires: %zu, of which:\n", count_public_wires);
1674 log_debug(" Const wires: %zu\n", count_const_wires);
1675 log_debug(" Alias wires: %zu\n", count_alias_wires);
1676 log_debug(" Member wires: %zu\n", count_member_wires);
1677 log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
1678 }
1679
1680 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1681 {
1682 if (metadata_map.empty()) {
1683 f << "metadata_map()";
1684 return;
1685 }
1686 f << "metadata_map({\n";
1687 inc_indent();
1688 for (auto metadata_item : metadata_map) {
1689 if (!metadata_item.first.begins_with("\\"))
1690 continue;
1691 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1692 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1693 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1694 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1695 f << escape_cxx_string(metadata_item.second.decode_string());
1696 } else {
1697 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1698 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1699 f << "u";
1700 }
1701 f << " },\n";
1702 }
1703 dec_indent();
1704 f << indent << "})";
1705 }
1706
1707 void dump_module_intf(RTLIL::Module *module)
1708 {
1709 dump_attrs(module);
1710 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1711 if (module->has_attribute(ID(cxxrtl_template)))
1712 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1713 f << indent << "struct " << mangle(module) << " : public module {\n";
1714 inc_indent();
1715 for (auto wire : module->wires()) {
1716 if (wire->port_id != 0)
1717 dump_wire(wire, /*is_local_context=*/false);
1718 }
1719 f << "\n";
1720 f << indent << "bool eval() override {\n";
1721 dump_eval_method(module);
1722 f << indent << "}\n";
1723 f << "\n";
1724 f << indent << "bool commit() override {\n";
1725 dump_commit_method(module);
1726 f << indent << "}\n";
1727 f << "\n";
1728 if (debug_info) {
1729 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1730 dump_debug_info_method(module);
1731 f << indent << "}\n";
1732 f << "\n";
1733 }
1734 f << indent << "static std::unique_ptr<" << mangle(module);
1735 f << template_params(module, /*is_decl=*/false) << "> ";
1736 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1737 dec_indent();
1738 f << indent << "}; // struct " << mangle(module) << "\n";
1739 f << "\n";
1740 if (blackbox_specializations.count(module)) {
1741 // If templated black boxes are used, the constructor of any module which includes the black box cell
1742 // (which calls the declared but not defined in the generated code `create` function) may only be used
1743 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1744 // a forward-declared explicit specialization.
1745 //
1746 // Option (b) makes it possible to have the generated code and the black box implementation in different
1747 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1748 // a specialization for every combination of parameters the generated code may use; but since the main
1749 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1750 // be very few such combinations anyway.
1751 for (auto specialization : blackbox_specializations[module]) {
1752 f << indent << "template<>\n";
1753 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1754 f << mangle(module) << specialization << "::";
1755 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1756 f << "\n";
1757 }
1758 }
1759 } else {
1760 f << indent << "struct " << mangle(module) << " : public module {\n";
1761 inc_indent();
1762 for (auto wire : module->wires())
1763 dump_wire(wire, /*is_local_context=*/false);
1764 f << "\n";
1765 bool has_memories = false;
1766 for (auto memory : module->memories) {
1767 dump_memory(module, memory.second);
1768 has_memories = true;
1769 }
1770 if (has_memories)
1771 f << "\n";
1772 bool has_cells = false;
1773 for (auto cell : module->cells()) {
1774 if (is_internal_cell(cell->type))
1775 continue;
1776 dump_attrs(cell);
1777 RTLIL::Module *cell_module = module->design->module(cell->type);
1778 log_assert(cell_module != nullptr);
1779 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1780 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1781 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1782 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1783 dump_metadata_map(cell->parameters);
1784 f << ", ";
1785 dump_metadata_map(cell->attributes);
1786 f << ");\n";
1787 } else {
1788 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1789 }
1790 has_cells = true;
1791 }
1792 if (has_cells)
1793 f << "\n";
1794 f << indent << "bool eval() override;\n";
1795 f << indent << "bool commit() override;\n";
1796 if (debug_info)
1797 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
1798 dec_indent();
1799 f << indent << "}; // struct " << mangle(module) << "\n";
1800 f << "\n";
1801 }
1802 }
1803
1804 void dump_module_impl(RTLIL::Module *module)
1805 {
1806 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1807 return;
1808 f << indent << "bool " << mangle(module) << "::eval() {\n";
1809 dump_eval_method(module);
1810 f << indent << "}\n";
1811 f << "\n";
1812 f << indent << "bool " << mangle(module) << "::commit() {\n";
1813 dump_commit_method(module);
1814 f << indent << "}\n";
1815 f << "\n";
1816 if (debug_info) {
1817 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
1818 dump_debug_info_method(module);
1819 f << indent << "}\n";
1820 f << "\n";
1821 }
1822 }
1823
1824 void dump_design(RTLIL::Design *design)
1825 {
1826 RTLIL::Module *top_module = nullptr;
1827 std::vector<RTLIL::Module*> modules;
1828 TopoSort<RTLIL::Module*> topo_design;
1829 for (auto module : design->modules()) {
1830 if (!design->selected_module(module))
1831 continue;
1832 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1833 modules.push_back(module); // cxxrtl blackboxes first
1834 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
1835 continue;
1836 if (module->get_bool_attribute(ID::top))
1837 top_module = module;
1838
1839 topo_design.node(module);
1840 for (auto cell : module->cells()) {
1841 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
1842 continue;
1843 RTLIL::Module *cell_module = design->module(cell->type);
1844 log_assert(cell_module != nullptr);
1845 topo_design.edge(cell_module, module);
1846 }
1847 }
1848 bool no_loops = topo_design.sort();
1849 log_assert(no_loops);
1850 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
1851
1852 if (split_intf) {
1853 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
1854 std::string include_guard = design_ns + "_header";
1855 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
1856
1857 f << "#ifndef " << include_guard << "\n";
1858 f << "#define " << include_guard << "\n";
1859 f << "\n";
1860 if (top_module != nullptr && debug_info) {
1861 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
1862 f << "\n";
1863 f << "#ifdef __cplusplus\n";
1864 f << "extern \"C\" {\n";
1865 f << "#endif\n";
1866 f << "\n";
1867 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
1868 f << "\n";
1869 f << "#ifdef __cplusplus\n";
1870 f << "}\n";
1871 f << "#endif\n";
1872 f << "\n";
1873 } else {
1874 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
1875 f << "\n";
1876 }
1877 f << "#ifdef __cplusplus\n";
1878 f << "\n";
1879 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1880 f << "\n";
1881 f << "using namespace cxxrtl;\n";
1882 f << "\n";
1883 f << "namespace " << design_ns << " {\n";
1884 f << "\n";
1885 for (auto module : modules)
1886 dump_module_intf(module);
1887 f << "} // namespace " << design_ns << "\n";
1888 f << "\n";
1889 f << "#endif // __cplusplus\n";
1890 f << "\n";
1891 f << "#endif\n";
1892 *intf_f << f.str(); f.str("");
1893 }
1894
1895 if (split_intf)
1896 f << "#include \"" << intf_filename << "\"\n";
1897 else
1898 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1899 f << "\n";
1900 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
1901 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1902 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
1903 f << "#endif\n";
1904 f << "\n";
1905 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1906 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
1907 f << "#endif\n";
1908 f << "\n";
1909 f << "using namespace cxxrtl_yosys;\n";
1910 f << "\n";
1911 f << "namespace " << design_ns << " {\n";
1912 f << "\n";
1913 for (auto module : modules) {
1914 if (!split_intf)
1915 dump_module_intf(module);
1916 dump_module_impl(module);
1917 }
1918 f << "} // namespace " << design_ns << "\n";
1919 f << "\n";
1920 if (top_module != nullptr && debug_info) {
1921 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
1922 inc_indent();
1923 std::string top_type = design_ns + "::" + mangle(top_module);
1924 f << indent << "return new _cxxrtl_toplevel { ";
1925 f << "std::unique_ptr<" << top_type << ">(new " + top_type + ")";
1926 f << " };\n";
1927 dec_indent();
1928 f << "}\n";
1929 }
1930
1931 *impl_f << f.str(); f.str("");
1932 }
1933
1934 // Edge-type sync rules require us to emit edge detectors, which require coordination between
1935 // eval and commit phases. To do this we need to collect them upfront.
1936 //
1937 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
1938 // operate at wire bit granularity; it is possible to have code similar to:
1939 // wire [3:0] clocks;
1940 // always @(posedge clocks[0]) ...
1941 // To handle this we track edge sensitivity both for wires and wire bits.
1942 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
1943 {
1944 signal = sigmap(signal);
1945 log_assert(signal.is_wire() && signal.is_bit());
1946 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
1947
1948 RTLIL::SigBit sigbit = signal[0];
1949 if (!edge_types.count(sigbit))
1950 edge_types[sigbit] = type;
1951 else if (edge_types[sigbit] != type)
1952 edge_types[sigbit] = RTLIL::STe;
1953 edge_wires.insert(signal.as_wire());
1954 }
1955
1956 void analyze_design(RTLIL::Design *design)
1957 {
1958 bool has_feedback_arcs = false;
1959 bool has_buffered_comb_wires = false;
1960
1961 for (auto module : design->modules()) {
1962 if (!design->selected_module(module))
1963 continue;
1964
1965 SigMap &sigmap = sigmaps[module];
1966 sigmap.set(module);
1967
1968 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1969 for (auto port : module->ports) {
1970 RTLIL::Wire *wire = module->wire(port);
1971 if (wire->port_input && !wire->port_output)
1972 unbuffered_wires.insert(wire);
1973 if (wire->has_attribute(ID(cxxrtl_edge))) {
1974 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
1975 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
1976 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
1977 log_id(module), log_signal(wire));
1978
1979 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
1980 for (int i = 0; i < GetSize(wire); i++) {
1981 RTLIL::SigSpec wire_sig = wire;
1982 switch (edges[i]) {
1983 case '-': break;
1984 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
1985 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
1986 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
1987 default:
1988 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
1989 "other than '-', 'p', 'n', or 'a'.\n",
1990 log_id(module), log_signal(wire));
1991 }
1992 }
1993 }
1994 }
1995
1996 // Black boxes converge by default, since their implementations are quite unlikely to require
1997 // internal propagation of comb signals.
1998 eval_converges[module] = true;
1999 continue;
2000 }
2001
2002 FlowGraph flow;
2003
2004 for (auto conn : module->connections())
2005 flow.add_node(conn);
2006
2007 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
2008 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
2009 pool<const RTLIL::Cell*>> memwr_per_domain;
2010 for (auto cell : module->cells()) {
2011 if (!cell->known())
2012 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2013
2014 RTLIL::Module *cell_module = design->module(cell->type);
2015 if (cell_module &&
2016 cell_module->get_blackbox_attribute() &&
2017 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2018 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2019
2020 if (cell_module &&
2021 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2022 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2023 blackbox_specializations[cell_module].insert(template_args(cell));
2024
2025 FlowGraph::Node *node = flow.add_node(cell);
2026
2027 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2028 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
2029 if (cell->getPort(ID::CLK).is_wire())
2030 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2031 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2032 }
2033 // Similar for memory port cells.
2034 if (cell->type.in(ID($memrd), ID($memwr))) {
2035 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2036 if (cell->getPort(ID::CLK).is_wire())
2037 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2038 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2039 }
2040 memrw_cell_nodes[cell] = node;
2041 }
2042 // Optimize access to read-only memories.
2043 if (cell->type == ID($memwr))
2044 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2045 // Collect groups of memory write ports in the same domain.
2046 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2047 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2048 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2049 memwr_per_domain[{clk_bit, memory}].insert(cell);
2050 }
2051 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2052 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2053 if (cell->type.in(ID($mem)))
2054 log_assert(false);
2055 }
2056 for (auto cell : module->cells()) {
2057 // Collect groups of memory write ports read by every transparent read port.
2058 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2059 cell->getParam(ID::TRANSPARENT).as_bool()) {
2060 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2061 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2062 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2063 transparent_for[cell].insert(memwr_cell);
2064 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2065 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2066 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2067 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2068 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2069 }
2070 }
2071 }
2072
2073 for (auto proc : module->processes) {
2074 flow.add_node(proc.second);
2075
2076 for (auto sync : proc.second->syncs)
2077 switch (sync->type) {
2078 // Edge-type sync rules require pre-registration.
2079 case RTLIL::STp:
2080 case RTLIL::STn:
2081 case RTLIL::STe:
2082 register_edge_signal(sigmap, sync->signal, sync->type);
2083 break;
2084
2085 // Level-type sync rules require no special handling.
2086 case RTLIL::ST0:
2087 case RTLIL::ST1:
2088 case RTLIL::STa:
2089 break;
2090
2091 case RTLIL::STg:
2092 log_cmd_error("Global clock is not supported.\n");
2093
2094 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2095 // attribute regardless of input.
2096 case RTLIL::STi:
2097 log_assert(false);
2098 }
2099 }
2100
2101 for (auto wire : module->wires()) {
2102 if (!flow.is_elidable(wire)) continue;
2103 if (wire->port_id != 0) continue;
2104 if (wire->get_bool_attribute(ID::keep)) continue;
2105 if (wire->name.begins_with("$") && !elide_internal) continue;
2106 if (wire->name.begins_with("\\") && !elide_public) continue;
2107 if (edge_wires[wire]) continue;
2108 log_assert(flow.wire_comb_defs[wire].size() == 1);
2109 elided_wires[wire] = **flow.wire_comb_defs[wire].begin();
2110 }
2111
2112 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2113 for (auto wire_comb_def : flow.wire_comb_defs)
2114 for (auto node : wire_comb_def.second)
2115 node_defs[node].insert(wire_comb_def.first);
2116
2117 Scheduler<FlowGraph::Node> scheduler;
2118 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2119 for (auto node : flow.nodes)
2120 node_map[node] = scheduler.add(node);
2121 for (auto node_def : node_defs) {
2122 auto vertex = node_map[node_def.first];
2123 for (auto wire : node_def.second)
2124 for (auto succ_node : flow.wire_uses[wire]) {
2125 auto succ_vertex = node_map[succ_node];
2126 vertex->succs.insert(succ_vertex);
2127 succ_vertex->preds.insert(vertex);
2128 }
2129 }
2130
2131 auto eval_order = scheduler.schedule();
2132 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2133 pool<const RTLIL::Wire*> feedback_wires;
2134 for (auto vertex : eval_order) {
2135 auto node = vertex->data;
2136 schedule[module].push_back(*node);
2137 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2138 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2139 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2140 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2141 evaluated.insert(node);
2142 for (auto wire : node_defs[node])
2143 for (auto succ_node : flow.wire_uses[wire])
2144 if (evaluated[succ_node]) {
2145 feedback_wires.insert(wire);
2146 // Feedback wires may never be elided because feedback requires state, but the point of elision
2147 // (and localization) is to eliminate state.
2148 elided_wires.erase(wire);
2149 }
2150 }
2151
2152 if (!feedback_wires.empty()) {
2153 has_feedback_arcs = true;
2154 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2155 for (auto wire : feedback_wires)
2156 log(" %s\n", log_id(wire));
2157 }
2158
2159 for (auto wire : module->wires()) {
2160 if (feedback_wires[wire]) continue;
2161 if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
2162 if (wire->name.begins_with("$") && !unbuffer_internal) continue;
2163 if (wire->name.begins_with("\\") && !unbuffer_public) continue;
2164 if (flow.wire_sync_defs.count(wire) > 0) continue;
2165 unbuffered_wires.insert(wire);
2166 if (edge_wires[wire]) continue;
2167 if (wire->get_bool_attribute(ID::keep)) continue;
2168 if (wire->port_input || wire->port_output) continue;
2169 if (wire->name.begins_with("$") && !localize_internal) continue;
2170 if (wire->name.begins_with("\\") && !localize_public) continue;
2171 localized_wires.insert(wire);
2172 }
2173
2174 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2175 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2176 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2177 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2178 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2179 // also require more than one delta cycle to converge.
2180 pool<const RTLIL::Wire*> buffered_comb_wires;
2181 for (auto wire : module->wires()) {
2182 if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
2183 buffered_comb_wires.insert(wire);
2184 }
2185 if (!buffered_comb_wires.empty()) {
2186 has_buffered_comb_wires = true;
2187 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2188 for (auto wire : buffered_comb_wires)
2189 log(" %s\n", log_id(wire));
2190 }
2191
2192 eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
2193
2194 if (debug_info) {
2195 // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
2196 // at essentially zero additional cost.
2197 //
2198 // Note that the information collected here can't be used for optimizing the netlist: debug information queries
2199 // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
2200 for (auto wire : module->wires()) {
2201 if (wire->name[0] != '\\')
2202 continue;
2203 if (!unbuffered_wires[wire])
2204 continue;
2205 const RTLIL::Wire *wire_it = wire;
2206 while (1) {
2207 if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it]))
2208 break; // not an alias: complex def
2209 log_assert(flow.wire_comb_defs[wire_it].size() == 1);
2210 FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin();
2211 if (node->type != FlowGraph::Node::Type::CONNECT)
2212 break; // not an alias: def by cell
2213 RTLIL::SigSpec rhs_sig = node->connect.second;
2214 if (rhs_sig.is_wire()) {
2215 RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
2216 if (unbuffered_wires[rhs_wire]) {
2217 wire_it = rhs_wire; // maybe an alias
2218 } else {
2219 debug_alias_wires[wire] = rhs_wire; // is an alias
2220 break;
2221 }
2222 } else if (rhs_sig.is_fully_const()) {
2223 debug_const_wires[wire] = rhs_sig.as_const(); // is a const
2224 break;
2225 } else {
2226 break; // not an alias: complex rhs
2227 }
2228 }
2229 }
2230 }
2231 }
2232 if (has_feedback_arcs || has_buffered_comb_wires) {
2233 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2234 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2235 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2236 const char *why_pessimistic = nullptr;
2237 if (has_feedback_arcs)
2238 why_pessimistic = "feedback wires";
2239 else if (has_buffered_comb_wires)
2240 why_pessimistic = "buffered combinatorial wires";
2241 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2242 if (!run_flatten)
2243 log("Flattening may eliminate %s from the design.\n", why_pessimistic);
2244 if (!run_proc)
2245 log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic);
2246 }
2247 }
2248
2249 void check_design(RTLIL::Design *design, bool &has_sync_init, bool &has_packed_mem)
2250 {
2251 has_sync_init = has_packed_mem = false;
2252
2253 for (auto module : design->modules()) {
2254 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2255 continue;
2256
2257 if (!design->selected_whole_module(module))
2258 if (design->selected_module(module))
2259 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2260 if (!design->selected_module(module))
2261 continue;
2262
2263 for (auto proc : module->processes)
2264 for (auto sync : proc.second->syncs)
2265 if (sync->type == RTLIL::STi)
2266 has_sync_init = true;
2267
2268 for (auto cell : module->cells())
2269 if (cell->type == ID($mem))
2270 has_packed_mem = true;
2271 }
2272 }
2273
2274 void prepare_design(RTLIL::Design *design)
2275 {
2276 bool did_anything = false;
2277 bool has_sync_init, has_packed_mem;
2278 log_push();
2279 check_design(design, has_sync_init, has_packed_mem);
2280 if (run_flatten) {
2281 Pass::call(design, "flatten");
2282 did_anything = true;
2283 }
2284 if (run_proc) {
2285 Pass::call(design, "proc");
2286 did_anything = true;
2287 } else if (has_sync_init) {
2288 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2289 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2290 Pass::call(design, "proc_prune");
2291 Pass::call(design, "proc_clean");
2292 Pass::call(design, "proc_init");
2293 did_anything = true;
2294 }
2295 if (has_packed_mem) {
2296 Pass::call(design, "memory_unpack");
2297 did_anything = true;
2298 }
2299 // Recheck the design if it was modified.
2300 if (has_sync_init || has_packed_mem)
2301 check_design(design, has_sync_init, has_packed_mem);
2302 log_assert(!(has_sync_init || has_packed_mem));
2303 log_pop();
2304 if (did_anything)
2305 log_spacer();
2306 analyze_design(design);
2307 }
2308 };
2309
2310 struct CxxrtlBackend : public Backend {
2311 static const int DEFAULT_OPT_LEVEL = 6;
2312 static const int OPT_LEVEL_DEBUG = 4;
2313 static const int DEFAULT_DEBUG_LEVEL = 1;
2314
2315 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2316 void help() YS_OVERRIDE
2317 {
2318 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2319 log("\n");
2320 log(" write_cxxrtl [options] [filename]\n");
2321 log("\n");
2322 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2323 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2324 log("\n");
2325 log("The following driver may be used as an example for a design with a single clock\n");
2326 log("driving rising edge triggered flip-flops:\n");
2327 log("\n");
2328 log(" #include \"top.cc\"\n");
2329 log("\n");
2330 log(" int main() {\n");
2331 log(" cxxrtl_design::p_top top;\n");
2332 log(" top.step();\n");
2333 log(" while (1) {\n");
2334 log(" /* user logic */\n");
2335 log(" top.p_clk = value<1> {0u};\n");
2336 log(" top.step();\n");
2337 log(" top.p_clk = value<1> {1u};\n");
2338 log(" top.step();\n");
2339 log(" }\n");
2340 log(" }\n");
2341 log("\n");
2342 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2343 log("subject to race conditions. If, in the example above, the user logic would run\n");
2344 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2345 log("\n");
2346 log("This backend supports replacing parts of the design with black boxes implemented\n");
2347 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2348 log("and the generated code consists only of an interface and a factory function.\n");
2349 log("The driver must implement the factory function that creates an implementation of\n");
2350 log("the black box, taking into account the parameters it is instantiated with.\n");
2351 log("\n");
2352 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2353 log("a synchronous debug sink:\n");
2354 log("\n");
2355 log(" (* cxxrtl_blackbox *)\n");
2356 log(" module debug(...);\n");
2357 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2358 log(" input en;\n");
2359 log(" input [7:0] i_data;\n");
2360 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2361 log(" endmodule\n");
2362 log("\n");
2363 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2364 log("\n");
2365 log(" struct bb_p_debug : public module {\n");
2366 log(" value<1> p_clk;\n");
2367 log(" bool posedge_p_clk() const { /* ... */ }\n");
2368 log(" value<1> p_en;\n");
2369 log(" value<8> p_i_data;\n");
2370 log(" wire<8> p_o_data;\n");
2371 log("\n");
2372 log(" bool eval() override;\n");
2373 log(" bool commit() override;\n");
2374 log("\n");
2375 log(" static std::unique_ptr<bb_p_debug>\n");
2376 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2377 log(" };\n");
2378 log("\n");
2379 log("The `create' function must be implemented by the driver. For example, it could\n");
2380 log("always provide an implementation logging the values to standard error stream:\n");
2381 log("\n");
2382 log(" namespace cxxrtl_design {\n");
2383 log("\n");
2384 log(" struct stderr_debug : public bb_p_debug {\n");
2385 log(" bool eval() override {\n");
2386 log(" if (posedge_p_clk() && p_en)\n");
2387 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2388 log(" p_o_data.next = p_i_data;\n");
2389 log(" return bb_p_debug::eval();\n");
2390 log(" }\n");
2391 log(" };\n");
2392 log("\n");
2393 log(" std::unique_ptr<bb_p_debug>\n");
2394 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2395 log(" cxxrtl::metadata_map attributes) {\n");
2396 log(" return std::make_unique<stderr_debug>();\n");
2397 log(" }\n");
2398 log("\n");
2399 log(" }\n");
2400 log("\n");
2401 log("For complex applications of black boxes, it is possible to parameterize their\n");
2402 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2403 log("interface for a configurable width debug sink:\n");
2404 log("\n");
2405 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2406 log(" module debug(...);\n");
2407 log(" parameter WIDTH = 8;\n");
2408 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2409 log(" input en;\n");
2410 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2411 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2412 log(" endmodule\n");
2413 log("\n");
2414 log("For this parametric HDL interface, this backend will generate the following C++\n");
2415 log("interface (only the differences are shown):\n");
2416 log("\n");
2417 log(" template<size_t WIDTH>\n");
2418 log(" struct bb_p_debug : public module {\n");
2419 log(" // ...\n");
2420 log(" value<WIDTH> p_i_data;\n");
2421 log(" wire<WIDTH> p_o_data;\n");
2422 log(" // ...\n");
2423 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2424 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2425 log(" };\n");
2426 log("\n");
2427 log("The `create' function must be implemented by the driver, specialized for every\n");
2428 log("possible combination of template parameters. (Specialization is necessary to\n");
2429 log("enable separate compilation of generated code and black box implementations.)\n");
2430 log("\n");
2431 log(" template<size_t SIZE>\n");
2432 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2433 log(" // ...\n");
2434 log(" };\n");
2435 log("\n");
2436 log(" template<>\n");
2437 log(" std::unique_ptr<bb_p_debug<8>>\n");
2438 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2439 log(" cxxrtl::metadata_map attributes) {\n");
2440 log(" return std::make_unique<stderr_debug<8>>();\n");
2441 log(" }\n");
2442 log("\n");
2443 log("The following attributes are recognized by this backend:\n");
2444 log("\n");
2445 log(" cxxrtl_blackbox\n");
2446 log(" only valid on modules. if specified, the module contents are ignored,\n");
2447 log(" and the generated code includes only the module interface and a factory\n");
2448 log(" function, which will be called to instantiate the module.\n");
2449 log("\n");
2450 log(" cxxrtl_edge\n");
2451 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2452 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2453 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2454 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2455 log("\n");
2456 log(" cxxrtl_template\n");
2457 log(" only valid on black boxes. must contain a space separated sequence of\n");
2458 log(" identifiers that have a corresponding black box parameters. for each\n");
2459 log(" of them, the generated code includes a `size_t` template parameter.\n");
2460 log("\n");
2461 log(" cxxrtl_width\n");
2462 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2463 log(" is directly inserted into generated code.\n");
2464 log("\n");
2465 log(" cxxrtl_comb, cxxrtl_sync\n");
2466 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2467 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2468 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2469 log(" if neither is specified, the output will be pessimistically treated as\n");
2470 log(" driven by both combinatorial and synchronous logic.\n");
2471 log("\n");
2472 log("The following options are supported by this backend:\n");
2473 log("\n");
2474 log(" -header\n");
2475 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2476 log(" if specified, the backend must be called with a filename, and filename\n");
2477 log(" of the interface is derived from filename of the implementation.\n");
2478 log(" otherwise, interface and implementation are generated together.\n");
2479 log("\n");
2480 log(" -namespace <ns-name>\n");
2481 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2482 log(" \"cxxrtl_design\" is used.\n");
2483 log("\n");
2484 log(" -noflatten\n");
2485 log(" don't flatten the design. fully flattened designs can evaluate within\n");
2486 log(" one delta cycle if they have no combinatorial feedback.\n");
2487 log(" note that the debug interface and waveform dumps use full hierarchical\n");
2488 log(" names for all wires even in flattened designs.\n");
2489 log("\n");
2490 log(" -noproc\n");
2491 log(" don't convert processes to netlists. in most designs, converting\n");
2492 log(" processes significantly improves evaluation performance at the cost of\n");
2493 log(" slight increase in compilation time.\n");
2494 log("\n");
2495 log(" -O <level>\n");
2496 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2497 log(" levels dramatically decrease compile and run time, and highest level\n");
2498 log(" possible for a design should be used.\n");
2499 log("\n");
2500 log(" -O0\n");
2501 log(" no optimization.\n");
2502 log("\n");
2503 log(" -O1\n");
2504 log(" localize internal wires if possible.\n");
2505 log("\n");
2506 log(" -O2\n");
2507 log(" like -O1, and unbuffer internal wires if possible.\n");
2508 log("\n");
2509 log(" -O3\n");
2510 log(" like -O2, and elide internal wires if possible.\n");
2511 log("\n");
2512 log(" -O4\n");
2513 log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
2514 log("\n");
2515 log(" -O5\n");
2516 log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
2517 log("\n");
2518 log(" -O6\n");
2519 log(" like -O5, and elide public wires not marked (*keep*) if possible.\n");
2520 log("\n");
2521 log(" -Og\n");
2522 log(" highest optimization level that provides debug information for all\n");
2523 log(" public wires. currently, alias for -O%d.\n", OPT_LEVEL_DEBUG);
2524 log("\n");
2525 log(" -g <level>\n");
2526 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2527 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2528 log("\n");
2529 log(" -g0\n");
2530 log(" no debug information.\n");
2531 log("\n");
2532 log(" -g1\n");
2533 log(" debug information for non-optimized public wires. this also makes it\n");
2534 log(" possible to use the C API.\n");
2535 log("\n");
2536 }
2537
2538 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
2539 {
2540 bool noflatten = false;
2541 bool noproc = false;
2542 int opt_level = DEFAULT_OPT_LEVEL;
2543 int debug_level = DEFAULT_DEBUG_LEVEL;
2544 CxxrtlWorker worker;
2545
2546 log_header(design, "Executing CXXRTL backend.\n");
2547
2548 size_t argidx;
2549 for (argidx = 1; argidx < args.size(); argidx++)
2550 {
2551 if (args[argidx] == "-noflatten") {
2552 noflatten = true;
2553 continue;
2554 }
2555 if (args[argidx] == "-noproc") {
2556 noproc = true;
2557 continue;
2558 }
2559 if (args[argidx] == "-Og") {
2560 opt_level = OPT_LEVEL_DEBUG;
2561 continue;
2562 }
2563 if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
2564 argidx++;
2565 opt_level = OPT_LEVEL_DEBUG;
2566 continue;
2567 }
2568 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2569 opt_level = std::stoi(args[++argidx]);
2570 continue;
2571 }
2572 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2573 opt_level = std::stoi(args[argidx].substr(2));
2574 continue;
2575 }
2576 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2577 debug_level = std::stoi(args[++argidx]);
2578 continue;
2579 }
2580 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2581 debug_level = std::stoi(args[argidx].substr(2));
2582 continue;
2583 }
2584 if (args[argidx] == "-header") {
2585 worker.split_intf = true;
2586 continue;
2587 }
2588 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2589 worker.design_ns = args[++argidx];
2590 continue;
2591 }
2592 break;
2593 }
2594 extra_args(f, filename, args, argidx);
2595
2596 worker.run_flatten = !noflatten;
2597 worker.run_proc = !noproc;
2598 switch (opt_level) {
2599 // the highest level here must match DEFAULT_OPT_LEVEL
2600 case 6:
2601 worker.elide_public = true;
2602 YS_FALLTHROUGH
2603 case 5:
2604 worker.localize_public = true;
2605 YS_FALLTHROUGH
2606 case 4:
2607 worker.unbuffer_public = true;
2608 YS_FALLTHROUGH
2609 case 3:
2610 worker.elide_internal = true;
2611 YS_FALLTHROUGH
2612 case 2:
2613 worker.localize_internal = true;
2614 YS_FALLTHROUGH
2615 case 1:
2616 worker.unbuffer_internal = true;
2617 YS_FALLTHROUGH
2618 case 0:
2619 break;
2620 default:
2621 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2622 }
2623 switch (debug_level) {
2624 // the highest level here must match DEFAULT_DEBUG_LEVEL
2625 case 1:
2626 worker.debug_info = true;
2627 YS_FALLTHROUGH
2628 case 0:
2629 break;
2630 default:
2631 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2632 }
2633
2634 std::ofstream intf_f;
2635 if (worker.split_intf) {
2636 if (filename == "<stdout>")
2637 log_cmd_error("Option -header must be used with a filename.\n");
2638
2639 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2640 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2641 if (intf_f.fail())
2642 log_cmd_error("Can't open file `%s' for writing: %s\n",
2643 worker.intf_filename.c_str(), strerror(errno));
2644
2645 worker.intf_f = &intf_f;
2646 }
2647 worker.impl_f = f;
2648
2649 worker.prepare_design(design);
2650 worker.dump_design(design);
2651 }
2652 } CxxrtlBackend;
2653
2654 PRIVATE_NAMESPACE_END