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Merge pull request #2128 from whitequark/flatten-processes
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/log.h"
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 // [[CITE]]
31 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
32 // Information Processing Letters, Vol. 47, pp 319-323, 1993
33 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
34
35 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
36 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
37 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
38 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
39 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
40 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
41 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
42 template<class T>
43 struct Scheduler {
44 struct Vertex {
45 T *data;
46 Vertex *prev, *next;
47 pool<Vertex*, hash_ptr_ops> preds, succs;
48
49 Vertex() : data(NULL), prev(this), next(this) {}
50 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
51
52 bool empty() const
53 {
54 log_assert(data == NULL);
55 if (next == this) {
56 log_assert(prev == next);
57 return true;
58 }
59 return false;
60 }
61
62 void link(Vertex *list)
63 {
64 log_assert(prev == NULL && next == NULL);
65 next = list;
66 prev = list->prev;
67 list->prev->next = this;
68 list->prev = this;
69 }
70
71 void unlink()
72 {
73 log_assert(prev->next == this && next->prev == this);
74 prev->next = next;
75 next->prev = prev;
76 next = prev = NULL;
77 }
78
79 int delta() const
80 {
81 return succs.size() - preds.size();
82 }
83 };
84
85 std::vector<Vertex*> vertices;
86 Vertex *sources = new Vertex;
87 Vertex *sinks = new Vertex;
88 dict<int, Vertex*> bins;
89
90 ~Scheduler()
91 {
92 delete sources;
93 delete sinks;
94 for (auto bin : bins)
95 delete bin.second;
96 for (auto vertex : vertices)
97 delete vertex;
98 }
99
100 Vertex *add(T *data)
101 {
102 Vertex *vertex = new Vertex(data);
103 vertices.push_back(vertex);
104 return vertex;
105 }
106
107 void relink(Vertex *vertex)
108 {
109 if (vertex->succs.empty())
110 vertex->link(sinks);
111 else if (vertex->preds.empty())
112 vertex->link(sources);
113 else {
114 int delta = vertex->delta();
115 if (!bins.count(delta))
116 bins[delta] = new Vertex;
117 vertex->link(bins[delta]);
118 }
119 }
120
121 Vertex *remove(Vertex *vertex)
122 {
123 vertex->unlink();
124 for (auto pred : vertex->preds) {
125 if (pred == vertex)
126 continue;
127 log_assert(pred->succs[vertex]);
128 pred->unlink();
129 pred->succs.erase(vertex);
130 relink(pred);
131 }
132 for (auto succ : vertex->succs) {
133 if (succ == vertex)
134 continue;
135 log_assert(succ->preds[vertex]);
136 succ->unlink();
137 succ->preds.erase(vertex);
138 relink(succ);
139 }
140 vertex->preds.clear();
141 vertex->succs.clear();
142 return vertex;
143 }
144
145 std::vector<Vertex*> schedule()
146 {
147 std::vector<Vertex*> s1, s2r;
148 for (auto vertex : vertices)
149 relink(vertex);
150 bool bins_empty = false;
151 while (!(sinks->empty() && sources->empty() && bins_empty)) {
152 while (!sinks->empty())
153 s2r.push_back(remove(sinks->next));
154 while (!sources->empty())
155 s1.push_back(remove(sources->next));
156 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
157 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
158 // naive implementation of find-max-key.
159 bins_empty = true;
160 bins.template sort<std::greater<int>>();
161 for (auto bin : bins) {
162 if (!bin.second->empty()) {
163 bins_empty = false;
164 s1.push_back(remove(bin.second->next));
165 break;
166 }
167 }
168 }
169 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
170 return s1;
171 }
172 };
173
174 bool is_input_wire(const RTLIL::Wire *wire)
175 {
176 return wire->port_input && !wire->port_output;
177 }
178
179 bool is_unary_cell(RTLIL::IdString type)
180 {
181 return type.in(
182 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
183 ID($pos), ID($neg));
184 }
185
186 bool is_binary_cell(RTLIL::IdString type)
187 {
188 return type.in(
189 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
190 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
191 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
192 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
193 }
194
195 bool is_extending_cell(RTLIL::IdString type)
196 {
197 return !type.in(
198 ID($logic_not), ID($logic_and), ID($logic_or),
199 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
200 }
201
202 bool is_elidable_cell(RTLIL::IdString type)
203 {
204 return is_unary_cell(type) || is_binary_cell(type) || type.in(
205 ID($mux), ID($concat), ID($slice));
206 }
207
208 bool is_sync_ff_cell(RTLIL::IdString type)
209 {
210 return type.in(
211 ID($dff), ID($dffe));
212 }
213
214 bool is_ff_cell(RTLIL::IdString type)
215 {
216 return is_sync_ff_cell(type) || type.in(
217 ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
218 }
219
220 bool is_internal_cell(RTLIL::IdString type)
221 {
222 return type[0] == '$' && !type.begins_with("$paramod");
223 }
224
225 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
226 {
227 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
228 log_assert(cell_module != nullptr);
229 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
230 }
231
232 enum class CxxrtlPortType {
233 UNKNOWN = 0, // or mixed comb/sync
234 COMB = 1,
235 SYNC = 2,
236 };
237
238 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
239 {
240 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
241 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
242 return CxxrtlPortType::UNKNOWN;
243 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
244 log_assert(cell_output_wire != nullptr);
245 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
246 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
247 if (is_comb && is_sync)
248 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
249 log_id(cell_module), log_signal(cell_output_wire));
250 else if (is_comb)
251 return CxxrtlPortType::COMB;
252 else if (is_sync)
253 return CxxrtlPortType::SYNC;
254 return CxxrtlPortType::UNKNOWN;
255 }
256
257 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
258 {
259 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
260 }
261
262 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
263 {
264 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
265 }
266
267 struct FlowGraph {
268 struct Node {
269 enum class Type {
270 CONNECT,
271 CELL_SYNC,
272 CELL_EVAL,
273 PROCESS
274 };
275
276 Type type;
277 RTLIL::SigSig connect = {};
278 const RTLIL::Cell *cell = NULL;
279 const RTLIL::Process *process = NULL;
280 };
281
282 std::vector<Node*> nodes;
283 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
284 dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
285
286 ~FlowGraph()
287 {
288 for (auto node : nodes)
289 delete node;
290 }
291
292 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool fully_sync, bool elidable)
293 {
294 for (auto chunk : sig.chunks())
295 if (chunk.wire) {
296 if (fully_sync)
297 wire_sync_defs[chunk.wire].insert(node);
298 else
299 wire_comb_defs[chunk.wire].insert(node);
300 }
301 // Only comb defs of an entire wire in the right order can be elided.
302 if (!fully_sync && sig.is_wire())
303 wire_def_elidable[sig.as_wire()] = elidable;
304 }
305
306 void add_uses(Node *node, const RTLIL::SigSpec &sig)
307 {
308 for (auto chunk : sig.chunks())
309 if (chunk.wire) {
310 wire_uses[chunk.wire].insert(node);
311 // Only a single use of an entire wire in the right order can be elided.
312 // (But the use can include other chunks.)
313 if (!wire_use_elidable.count(chunk.wire))
314 wire_use_elidable[chunk.wire] = true;
315 else
316 wire_use_elidable[chunk.wire] = false;
317 }
318 }
319
320 bool is_elidable(const RTLIL::Wire *wire) const
321 {
322 if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire))
323 return wire_def_elidable.at(wire) && wire_use_elidable.at(wire);
324 return false;
325 }
326
327 // Connections
328 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
329 {
330 add_defs(node, conn.first, /*fully_sync=*/false, /*elidable=*/true);
331 add_uses(node, conn.second);
332 }
333
334 Node *add_node(const RTLIL::SigSig &conn)
335 {
336 Node *node = new Node;
337 node->type = Node::Type::CONNECT;
338 node->connect = conn;
339 nodes.push_back(node);
340 add_connect_defs_uses(node, conn);
341 return node;
342 }
343
344 // Cells
345 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
346 {
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
352 //
353 // wire<1> i_tmp;
354 // cell->p_i = i_tmp.curr;
355 // cell->eval();
356 // i_tmp.next = cell->p_o.curr;
357 //
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
361 //
362 // value<1> i_tmp;
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
365 // cell->eval();
366 //
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn : cell->connections())
374 if (cell->output(conn.first))
375 if (is_cxxrtl_sync_port(cell, conn.first)) {
376 // See note regarding elidability below.
377 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
378 }
379 }
380
381 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
382 {
383 for (auto conn : cell->connections()) {
384 if (cell->output(conn.first)) {
385 if (is_elidable_cell(cell->type))
386 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/true);
387 else if (is_sync_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
388 add_defs(node, conn.second, /*fully_sync=*/true, /*elidable=*/false);
389 else if (is_internal_cell(cell->type))
390 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
391 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
392 // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
396 // the infrastructure required to elide outputs of cells with many of them.
397 add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
398 }
399 }
400 if (cell->input(conn.first))
401 add_uses(node, conn.second);
402 }
403 }
404
405 Node *add_node(const RTLIL::Cell *cell)
406 {
407 log_assert(cell->known());
408
409 bool has_fully_sync_outputs = false;
410 for (auto conn : cell->connections())
411 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
412 has_fully_sync_outputs = true;
413 break;
414 }
415 if (has_fully_sync_outputs) {
416 Node *node = new Node;
417 node->type = Node::Type::CELL_SYNC;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_sync_defs(node, cell);
421 }
422
423 Node *node = new Node;
424 node->type = Node::Type::CELL_EVAL;
425 node->cell = cell;
426 nodes.push_back(node);
427 add_cell_eval_defs_uses(node, cell);
428 return node;
429 }
430
431 // Processes
432 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
433 {
434 for (auto &action : case_->actions) {
435 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
436 add_uses(node, action.second);
437 }
438 for (auto sub_switch : case_->switches) {
439 add_uses(node, sub_switch->signal);
440 for (auto sub_case : sub_switch->cases) {
441 for (auto &compare : sub_case->compare)
442 add_uses(node, compare);
443 add_case_defs_uses(node, sub_case);
444 }
445 }
446 }
447
448 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
449 {
450 add_case_defs_uses(node, &process->root_case);
451 for (auto sync : process->syncs)
452 for (auto action : sync->actions) {
453 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
454 add_defs(node, action.first, /*is_sync=*/true, /*elidable=*/false);
455 else
456 add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
457 add_uses(node, action.second);
458 }
459 }
460
461 Node *add_node(const RTLIL::Process *process)
462 {
463 Node *node = new Node;
464 node->type = Node::Type::PROCESS;
465 node->process = process;
466 nodes.push_back(node);
467 add_process_defs_uses(node, process);
468 return node;
469 }
470 };
471
472 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
473 {
474 std::vector<std::string> result;
475 size_t prev = 0;
476 while (true) {
477 size_t curr = str.find_first_of(sep, prev);
478 if (curr == std::string::npos) {
479 std::string part = str.substr(prev);
480 if (!part.empty()) result.push_back(part);
481 break;
482 } else {
483 std::string part = str.substr(prev, curr - prev);
484 if (!part.empty()) result.push_back(part);
485 prev = curr + 1;
486 }
487 }
488 return result;
489 }
490
491 std::string escape_cxx_string(const std::string &input)
492 {
493 std::string output = "\"";
494 for (auto c : input) {
495 if (::isprint(c)) {
496 if (c == '\\')
497 output.push_back('\\');
498 output.push_back(c);
499 } else {
500 char l = c & 0xf, h = (c >> 4) & 0xf;
501 output.append("\\x");
502 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
503 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
504 }
505 }
506 output.push_back('"');
507 if (output.find('\0') != std::string::npos) {
508 output.insert(0, "std::string {");
509 output.append(stringf(", %zu}", input.size()));
510 }
511 return output;
512 }
513
514 template<class T>
515 std::string get_hdl_name(T *object)
516 {
517 if (object->has_attribute(ID::hdlname))
518 return object->get_string_attribute(ID::hdlname);
519 else
520 return object->name.str().substr(1);
521 }
522
523 struct CxxrtlWorker {
524 bool split_intf = false;
525 std::string intf_filename;
526 std::string design_ns = "cxxrtl_design";
527 std::ostream *impl_f = nullptr;
528 std::ostream *intf_f = nullptr;
529
530 bool elide_internal = false;
531 bool elide_public = false;
532 bool localize_internal = false;
533 bool localize_public = false;
534 bool run_proc_flatten = false;
535 bool max_opt_level = false;
536
537 bool debug_info = false;
538
539 std::ostringstream f;
540 std::string indent;
541 int temporary = 0;
542
543 dict<const RTLIL::Module*, SigMap> sigmaps;
544 pool<const RTLIL::Wire*> edge_wires;
545 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
546 pool<const RTLIL::Memory*> writable_memories;
547 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
548 dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
549 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
550 pool<const RTLIL::Wire*> localized_wires;
551 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
552 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
553 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
554 dict<const RTLIL::Module*, bool> eval_converges;
555
556 void inc_indent() {
557 indent += "\t";
558 }
559 void dec_indent() {
560 indent.resize(indent.size() - 1);
561 }
562
563 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
564 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
565 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
566 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
567 // 1. All generated identifiers start with `_`.
568 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
569 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
570 // 2. An underscore is escaped with another underscore, i.e. `__`.
571 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
572 std::string mangle_name(const RTLIL::IdString &name)
573 {
574 std::string mangled;
575 bool first = true;
576 for (char c : name.str()) {
577 if (first) {
578 first = false;
579 if (c == '\\')
580 mangled += "p_";
581 else if (c == '$')
582 mangled += "i_";
583 else
584 log_assert(false);
585 } else {
586 if (isalnum(c)) {
587 mangled += c;
588 } else if (c == '_') {
589 mangled += "__";
590 } else {
591 char l = c & 0xf, h = (c >> 4) & 0xf;
592 mangled += '_';
593 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
594 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
595 mangled += '_';
596 }
597 }
598 }
599 return mangled;
600 }
601
602 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
603 {
604 // Class namespace.
605 if (is_blackbox)
606 return "bb_" + mangle_name(name);
607 return mangle_name(name);
608 }
609
610 std::string mangle_memory_name(const RTLIL::IdString &name)
611 {
612 // Class member namespace.
613 return "memory_" + mangle_name(name);
614 }
615
616 std::string mangle_cell_name(const RTLIL::IdString &name)
617 {
618 // Class member namespace.
619 return "cell_" + mangle_name(name);
620 }
621
622 std::string mangle_wire_name(const RTLIL::IdString &name)
623 {
624 // Class member namespace.
625 return mangle_name(name);
626 }
627
628 std::string mangle(const RTLIL::Module *module)
629 {
630 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
631 }
632
633 std::string mangle(const RTLIL::Memory *memory)
634 {
635 return mangle_memory_name(memory->name);
636 }
637
638 std::string mangle(const RTLIL::Cell *cell)
639 {
640 return mangle_cell_name(cell->name);
641 }
642
643 std::string mangle(const RTLIL::Wire *wire)
644 {
645 return mangle_wire_name(wire->name);
646 }
647
648 std::string mangle(RTLIL::SigBit sigbit)
649 {
650 log_assert(sigbit.wire != NULL);
651 if (sigbit.wire->width == 1)
652 return mangle(sigbit.wire);
653 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
654 }
655
656 std::vector<std::string> template_param_names(const RTLIL::Module *module)
657 {
658 if (!module->has_attribute(ID(cxxrtl_template)))
659 return {};
660
661 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
662 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
663
664 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
665 for (const auto &param_name : param_names) {
666 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
667 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
668 // in both Verilog and C++, anyway.)
669 if (!isupper(param_name[0]))
670 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
671 "which does not start with an uppercase letter.\n",
672 log_id(module), param_name.c_str());
673 }
674 return param_names;
675 }
676
677 std::string template_params(const RTLIL::Module *module, bool is_decl)
678 {
679 std::vector<std::string> param_names = template_param_names(module);
680 if (param_names.empty())
681 return "";
682
683 std::string params = "<";
684 bool first = true;
685 for (const auto &param_name : param_names) {
686 if (!first)
687 params += ", ";
688 first = false;
689 if (is_decl)
690 params += "size_t ";
691 params += param_name;
692 }
693 params += ">";
694 return params;
695 }
696
697 std::string template_args(const RTLIL::Cell *cell)
698 {
699 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
700 log_assert(cell_module != nullptr);
701 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
702 return "";
703
704 std::vector<std::string> param_names = template_param_names(cell_module);
705 if (param_names.empty())
706 return "";
707
708 std::string params = "<";
709 bool first = true;
710 for (const auto &param_name : param_names) {
711 if (!first)
712 params += ", ";
713 first = false;
714 params += "/*" + param_name + "=*/";
715 RTLIL::IdString id_param_name = '\\' + param_name;
716 if (!cell->hasParam(id_param_name))
717 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
718 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
719 RTLIL::Const param_value = cell->getParam(id_param_name);
720 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
721 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
722 "is not a positive integer.\n",
723 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
724 params += std::to_string(cell->getParam(id_param_name).as_int());
725 }
726 params += ">";
727 return params;
728 }
729
730 std::string fresh_temporary()
731 {
732 return stringf("tmp_%d", temporary++);
733 }
734
735 void dump_attrs(const RTLIL::AttrObject *object)
736 {
737 for (auto attr : object->attributes) {
738 f << indent << "// " << attr.first.str() << ": ";
739 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
740 f << attr.second.decode_string();
741 } else {
742 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
743 }
744 f << "\n";
745 }
746 }
747
748 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
749 {
750 const int CHUNK_SIZE = 32;
751 f << "{";
752 while (width > 0) {
753 int chunk_width = min(width, CHUNK_SIZE);
754 uint32_t chunk = data.extract(offset, chunk_width).as_int();
755 if (fixed_width)
756 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
757 else
758 f << stringf("%#xu", chunk);
759 if (width > CHUNK_SIZE)
760 f << ',';
761 offset += CHUNK_SIZE;
762 width -= CHUNK_SIZE;
763 }
764 f << "}";
765 }
766
767 void dump_const_init(const RTLIL::Const &data)
768 {
769 dump_const_init(data, data.size());
770 }
771
772 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
773 {
774 f << "value<" << width << ">";
775 dump_const_init(data, width, offset, fixed_width);
776 }
777
778 void dump_const(const RTLIL::Const &data)
779 {
780 dump_const(data, data.size());
781 }
782
783 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs)
784 {
785 if (chunk.wire == NULL) {
786 dump_const(chunk.data, chunk.width, chunk.offset);
787 return false;
788 } else {
789 if (!is_lhs && elided_wires.count(chunk.wire)) {
790 const FlowGraph::Node &node = elided_wires[chunk.wire];
791 switch (node.type) {
792 case FlowGraph::Node::Type::CONNECT:
793 dump_connect_elided(node.connect);
794 break;
795 case FlowGraph::Node::Type::CELL_EVAL:
796 log_assert(is_elidable_cell(node.cell->type));
797 dump_cell_elided(node.cell);
798 break;
799 default:
800 log_assert(false);
801 }
802 } else if (localized_wires[chunk.wire] || is_input_wire(chunk.wire)) {
803 f << mangle(chunk.wire);
804 } else {
805 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
806 }
807 if (chunk.width == chunk.wire->width && chunk.offset == 0)
808 return false;
809 else if (chunk.width == 1)
810 f << ".slice<" << chunk.offset << ">()";
811 else
812 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
813 return true;
814 }
815 }
816
817 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs)
818 {
819 if (sig.empty()) {
820 f << "value<0>()";
821 return false;
822 } else if (sig.is_chunk()) {
823 return dump_sigchunk(sig.as_chunk(), is_lhs);
824 } else {
825 dump_sigchunk(*sig.chunks().rbegin(), is_lhs);
826 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
827 f << ".concat(";
828 dump_sigchunk(*it, is_lhs);
829 f << ")";
830 }
831 return true;
832 }
833 }
834
835 void dump_sigspec_lhs(const RTLIL::SigSpec &sig)
836 {
837 dump_sigspec(sig, /*is_lhs=*/true);
838 }
839
840 void dump_sigspec_rhs(const RTLIL::SigSpec &sig)
841 {
842 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
843 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
844 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
845 // type conversion, but only if the expression needs it.
846 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false);
847 if (is_complex)
848 f << ".val()";
849 }
850
851 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
852 {
853 for (auto chunk : sig.chunks()) {
854 if (!chunk.wire || !elided_wires.count(chunk.wire))
855 continue;
856
857 const FlowGraph::Node &node = elided_wires[chunk.wire];
858 switch (node.type) {
859 case FlowGraph::Node::Type::CONNECT:
860 collect_connect(node.connect, cells);
861 break;
862 case FlowGraph::Node::Type::CELL_EVAL:
863 collect_cell_eval(node.cell, cells);
864 break;
865 default:
866 log_assert(false);
867 }
868 }
869 }
870
871 void dump_connect_elided(const RTLIL::SigSig &conn)
872 {
873 dump_sigspec_rhs(conn.second);
874 }
875
876 bool is_connect_elided(const RTLIL::SigSig &conn)
877 {
878 return conn.first.is_wire() && elided_wires.count(conn.first.as_wire());
879 }
880
881 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
882 {
883 if (!is_connect_elided(conn))
884 return;
885
886 collect_sigspec_rhs(conn.second, cells);
887 }
888
889 void dump_connect(const RTLIL::SigSig &conn)
890 {
891 if (is_connect_elided(conn))
892 return;
893
894 f << indent << "// connection\n";
895 f << indent;
896 dump_sigspec_lhs(conn.first);
897 f << " = ";
898 dump_connect_elided(conn);
899 f << ";\n";
900 }
901
902 void dump_cell_sync(const RTLIL::Cell *cell)
903 {
904 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
905 f << indent << "// cell " << cell->name.str() << " syncs\n";
906 for (auto conn : cell->connections())
907 if (cell->output(conn.first))
908 if (is_cxxrtl_sync_port(cell, conn.first)) {
909 f << indent;
910 dump_sigspec_lhs(conn.second);
911 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
912 }
913 }
914
915 void dump_cell_elided(const RTLIL::Cell *cell)
916 {
917 // Unary cells
918 if (is_unary_cell(cell->type)) {
919 f << cell->type.substr(1);
920 if (is_extending_cell(cell->type))
921 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
922 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
923 dump_sigspec_rhs(cell->getPort(ID::A));
924 f << ")";
925 // Binary cells
926 } else if (is_binary_cell(cell->type)) {
927 f << cell->type.substr(1);
928 if (is_extending_cell(cell->type))
929 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
930 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
931 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
932 dump_sigspec_rhs(cell->getPort(ID::A));
933 f << ", ";
934 dump_sigspec_rhs(cell->getPort(ID::B));
935 f << ")";
936 // Muxes
937 } else if (cell->type == ID($mux)) {
938 f << "(";
939 dump_sigspec_rhs(cell->getPort(ID::S));
940 f << " ? ";
941 dump_sigspec_rhs(cell->getPort(ID::B));
942 f << " : ";
943 dump_sigspec_rhs(cell->getPort(ID::A));
944 f << ")";
945 // Concats
946 } else if (cell->type == ID($concat)) {
947 dump_sigspec_rhs(cell->getPort(ID::B));
948 f << ".concat(";
949 dump_sigspec_rhs(cell->getPort(ID::A));
950 f << ").val()";
951 // Slices
952 } else if (cell->type == ID($slice)) {
953 dump_sigspec_rhs(cell->getPort(ID::A));
954 f << ".slice<";
955 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
956 f << ",";
957 f << cell->getParam(ID::OFFSET).as_int();
958 f << ">().val()";
959 } else {
960 log_assert(false);
961 }
962 }
963
964 bool is_cell_elided(const RTLIL::Cell *cell)
965 {
966 return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
967 elided_wires.count(cell->getPort(ID::Y).as_wire());
968 }
969
970 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
971 {
972 if (!is_cell_elided(cell))
973 return;
974
975 cells.push_back(cell->name);
976 for (auto port : cell->connections())
977 if (port.first != ID::Y)
978 collect_sigspec_rhs(port.second, cells);
979 }
980
981 void dump_cell_eval(const RTLIL::Cell *cell)
982 {
983 if (is_cell_elided(cell))
984 return;
985 if (cell->type == ID($meminit))
986 return; // Handled elsewhere.
987
988 std::vector<RTLIL::IdString> elided_cells;
989 if (is_elidable_cell(cell->type)) {
990 for (auto port : cell->connections())
991 if (port.first != ID::Y)
992 collect_sigspec_rhs(port.second, elided_cells);
993 }
994 if (elided_cells.empty()) {
995 dump_attrs(cell);
996 f << indent << "// cell " << cell->name.str() << "\n";
997 } else {
998 f << indent << "// cells";
999 for (auto elided_cell : elided_cells)
1000 f << " " << elided_cell.str();
1001 f << "\n";
1002 }
1003
1004 // Elidable cells
1005 if (is_elidable_cell(cell->type)) {
1006 f << indent;
1007 dump_sigspec_lhs(cell->getPort(ID::Y));
1008 f << " = ";
1009 dump_cell_elided(cell);
1010 f << ";\n";
1011 // Parallel (one-hot) muxes
1012 } else if (cell->type == ID($pmux)) {
1013 int width = cell->getParam(ID::WIDTH).as_int();
1014 int s_width = cell->getParam(ID::S_WIDTH).as_int();
1015 bool first = true;
1016 for (int part = 0; part < s_width; part++) {
1017 f << (first ? indent : " else ");
1018 first = false;
1019 f << "if (";
1020 dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
1021 f << ") {\n";
1022 inc_indent();
1023 f << indent;
1024 dump_sigspec_lhs(cell->getPort(ID::Y));
1025 f << " = ";
1026 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
1027 f << ";\n";
1028 dec_indent();
1029 f << indent << "}";
1030 }
1031 f << " else {\n";
1032 inc_indent();
1033 f << indent;
1034 dump_sigspec_lhs(cell->getPort(ID::Y));
1035 f << " = ";
1036 dump_sigspec_rhs(cell->getPort(ID::A));
1037 f << ";\n";
1038 dec_indent();
1039 f << indent << "}\n";
1040 // Flip-flops
1041 } else if (is_ff_cell(cell->type)) {
1042 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1043 // Edge-sensitive logic
1044 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1045 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1046 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1047 << mangle(clk_bit) << ") {\n";
1048 inc_indent();
1049 if (cell->type == ID($dffe)) {
1050 f << indent << "if (";
1051 dump_sigspec_rhs(cell->getPort(ID::EN));
1052 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1053 inc_indent();
1054 }
1055 f << indent;
1056 dump_sigspec_lhs(cell->getPort(ID::Q));
1057 f << " = ";
1058 dump_sigspec_rhs(cell->getPort(ID::D));
1059 f << ";\n";
1060 if (cell->type == ID($dffe)) {
1061 dec_indent();
1062 f << indent << "}\n";
1063 }
1064 dec_indent();
1065 f << indent << "}\n";
1066 } else if (cell->hasPort(ID::EN)) {
1067 // Level-sensitive logic
1068 f << indent << "if (";
1069 dump_sigspec_rhs(cell->getPort(ID::EN));
1070 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1071 inc_indent();
1072 f << indent;
1073 dump_sigspec_lhs(cell->getPort(ID::Q));
1074 f << " = ";
1075 dump_sigspec_rhs(cell->getPort(ID::D));
1076 f << ";\n";
1077 dec_indent();
1078 f << indent << "}\n";
1079 }
1080 if (cell->hasPort(ID::ARST)) {
1081 // Asynchronous reset (entire coarse cell at once)
1082 f << indent << "if (";
1083 dump_sigspec_rhs(cell->getPort(ID::ARST));
1084 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1085 inc_indent();
1086 f << indent;
1087 dump_sigspec_lhs(cell->getPort(ID::Q));
1088 f << " = ";
1089 dump_const(cell->getParam(ID::ARST_VALUE));
1090 f << ";\n";
1091 dec_indent();
1092 f << indent << "}\n";
1093 }
1094 if (cell->hasPort(ID::SET)) {
1095 // Asynchronous set (for individual bits)
1096 f << indent;
1097 dump_sigspec_lhs(cell->getPort(ID::Q));
1098 f << " = ";
1099 dump_sigspec_lhs(cell->getPort(ID::Q));
1100 f << ".update(";
1101 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1102 f << ", ";
1103 dump_sigspec_rhs(cell->getPort(ID::SET));
1104 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1105 }
1106 if (cell->hasPort(ID::CLR)) {
1107 // Asynchronous clear (for individual bits; priority over set)
1108 f << indent;
1109 dump_sigspec_lhs(cell->getPort(ID::Q));
1110 f << " = ";
1111 dump_sigspec_lhs(cell->getPort(ID::Q));
1112 f << ".update(";
1113 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1114 f << ", ";
1115 dump_sigspec_rhs(cell->getPort(ID::CLR));
1116 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1117 }
1118 // Memory ports
1119 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1120 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1121 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1122 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1123 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1124 << mangle(clk_bit) << ") {\n";
1125 inc_indent();
1126 }
1127 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1128 std::string valid_index_temp = fresh_temporary();
1129 f << indent << "auto " << valid_index_temp << " = memory_index(";
1130 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1131 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1132 if (cell->type == ID($memrd)) {
1133 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1134 if (has_enable) {
1135 f << indent << "if (";
1136 dump_sigspec_rhs(cell->getPort(ID::EN));
1137 f << ") {\n";
1138 inc_indent();
1139 }
1140 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1141 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1142 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -NDEBUG not
1143 // just for release builds, but also to make sure the simulator (which is presumably embedded in some
1144 // larger program) will never crash the code that calls into it.
1145 //
1146 // If assertions are disabled, out of bounds reads are defined to return zero.
1147 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1148 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1149 inc_indent();
1150 if (writable_memories[memory]) {
1151 std::string addr_temp = fresh_temporary();
1152 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1153 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1154 f << ";\n";
1155 std::string lhs_temp = fresh_temporary();
1156 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1157 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1158 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1159 std::sort(memwr_cells.begin(), memwr_cells.end(),
1160 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1161 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1162 });
1163 for (auto memwr_cell : memwr_cells) {
1164 f << indent << "if (" << addr_temp << " == ";
1165 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1166 f << ") {\n";
1167 inc_indent();
1168 f << indent << lhs_temp << " = " << lhs_temp;
1169 f << ".update(";
1170 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1171 f << ", ";
1172 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1173 f << ");\n";
1174 dec_indent();
1175 f << indent << "}\n";
1176 }
1177 f << indent;
1178 dump_sigspec_lhs(cell->getPort(ID::DATA));
1179 f << " = " << lhs_temp << ";\n";
1180 } else {
1181 f << indent;
1182 dump_sigspec_lhs(cell->getPort(ID::DATA));
1183 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1184 }
1185 dec_indent();
1186 f << indent << "} else {\n";
1187 inc_indent();
1188 f << indent;
1189 dump_sigspec_lhs(cell->getPort(ID::DATA));
1190 f << " = value<" << memory->width << "> {};\n";
1191 dec_indent();
1192 f << indent << "}\n";
1193 if (has_enable) {
1194 dec_indent();
1195 f << indent << "}\n";
1196 }
1197 } else /*if (cell->type == ID($memwr))*/ {
1198 log_assert(writable_memories[memory]);
1199 // See above for rationale of having both the assert and the condition.
1200 //
1201 // If assertions are disabled, out of bounds writes are defined to do nothing.
1202 f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1203 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1204 inc_indent();
1205 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1206 dump_sigspec_rhs(cell->getPort(ID::DATA));
1207 f << ", ";
1208 dump_sigspec_rhs(cell->getPort(ID::EN));
1209 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1210 dec_indent();
1211 f << indent << "}\n";
1212 }
1213 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1214 dec_indent();
1215 f << indent << "}\n";
1216 }
1217 // Internal cells
1218 } else if (is_internal_cell(cell->type)) {
1219 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1220 // User cells
1221 } else {
1222 log_assert(cell->known());
1223 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1224 for (auto conn : cell->connections())
1225 if (cell->input(conn.first) && !cell->output(conn.first)) {
1226 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = ";
1227 dump_sigspec_rhs(conn.second);
1228 f << ";\n";
1229 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1230 // Until we have proper clock tree detection, this really awful hack that opportunistically
1231 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1232 // be if only one clock edge was simulated by replacing:
1233 // top.p_clk = value<1>{0u}; top.step();
1234 // top.p_clk = value<1>{1u}; top.step();
1235 // with:
1236 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1237 // Don't rely on this; it will be removed without warning.
1238 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1239 if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) {
1240 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1241 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1242 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1243 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1244 }
1245 }
1246 }
1247 } else if (cell->input(conn.first)) {
1248 f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = ";
1249 dump_sigspec_rhs(conn.second);
1250 f << ";\n";
1251 }
1252 auto assign_from_outputs = [&](bool cell_converged) {
1253 for (auto conn : cell->connections()) {
1254 if (cell->output(conn.first)) {
1255 if (conn.second.empty())
1256 continue; // ignore disconnected ports
1257 if (is_cxxrtl_sync_port(cell, conn.first))
1258 continue; // fully sync ports are handled in CELL_SYNC nodes
1259 f << indent;
1260 dump_sigspec_lhs(conn.second);
1261 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1262 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1263 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1264 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1265 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1266 // and consider the fate of the localized wires that used to be output ports.)
1267 //
1268 // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell
1269 // (which may be late bound) will converge immediately. Because of this, the choice between using .curr
1270 // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime.
1271 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1272 f << ".next;\n";
1273 else
1274 f << ".curr;\n";
1275 }
1276 }
1277 };
1278 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1279 inc_indent();
1280 assign_from_outputs(/*cell_converged=*/true);
1281 dec_indent();
1282 f << indent << "} else {\n";
1283 inc_indent();
1284 f << indent << "converged = false;\n";
1285 assign_from_outputs(/*cell_converged=*/false);
1286 dec_indent();
1287 f << indent << "}\n";
1288 }
1289 }
1290
1291 void dump_assign(const RTLIL::SigSig &sigsig)
1292 {
1293 f << indent;
1294 dump_sigspec_lhs(sigsig.first);
1295 f << " = ";
1296 dump_sigspec_rhs(sigsig.second);
1297 f << ";\n";
1298 }
1299
1300 void dump_case_rule(const RTLIL::CaseRule *rule)
1301 {
1302 for (auto action : rule->actions)
1303 dump_assign(action);
1304 for (auto switch_ : rule->switches)
1305 dump_switch_rule(switch_);
1306 }
1307
1308 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1309 {
1310 // The switch attributes are printed before the switch condition is captured.
1311 dump_attrs(rule);
1312 std::string signal_temp = fresh_temporary();
1313 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1314 dump_sigspec(rule->signal, /*is_lhs=*/false);
1315 f << ";\n";
1316
1317 bool first = true;
1318 for (auto case_ : rule->cases) {
1319 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1320 dump_attrs(rule);
1321 f << indent;
1322 if (!first)
1323 f << "} else ";
1324 first = false;
1325 if (!case_->compare.empty()) {
1326 f << "if (";
1327 bool first = true;
1328 for (auto &compare : case_->compare) {
1329 if (!first)
1330 f << " || ";
1331 first = false;
1332 if (compare.is_fully_def()) {
1333 f << signal_temp << " == ";
1334 dump_sigspec(compare, /*is_lhs=*/false);
1335 } else if (compare.is_fully_const()) {
1336 RTLIL::Const compare_mask, compare_value;
1337 for (auto bit : compare.as_const()) {
1338 switch (bit) {
1339 case RTLIL::S0:
1340 case RTLIL::S1:
1341 compare_mask.bits.push_back(RTLIL::S1);
1342 compare_value.bits.push_back(bit);
1343 break;
1344
1345 case RTLIL::Sx:
1346 case RTLIL::Sz:
1347 case RTLIL::Sa:
1348 compare_mask.bits.push_back(RTLIL::S0);
1349 compare_value.bits.push_back(RTLIL::S0);
1350 break;
1351
1352 default:
1353 log_assert(false);
1354 }
1355 }
1356 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1357 dump_const(compare_mask);
1358 f << ") == ";
1359 dump_const(compare_value);
1360 } else {
1361 log_assert(false);
1362 }
1363 }
1364 f << ") ";
1365 }
1366 f << "{\n";
1367 inc_indent();
1368 dump_case_rule(case_);
1369 dec_indent();
1370 }
1371 f << indent << "}\n";
1372 }
1373
1374 void dump_process(const RTLIL::Process *proc)
1375 {
1376 dump_attrs(proc);
1377 f << indent << "// process " << proc->name.str() << "\n";
1378 // The case attributes (for root case) are always empty.
1379 log_assert(proc->root_case.attributes.empty());
1380 dump_case_rule(&proc->root_case);
1381 for (auto sync : proc->syncs) {
1382 RTLIL::SigBit sync_bit;
1383 if (!sync->signal.empty()) {
1384 sync_bit = sync->signal[0];
1385 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1386 }
1387
1388 pool<std::string> events;
1389 switch (sync->type) {
1390 case RTLIL::STp:
1391 log_assert(sync_bit.wire != nullptr);
1392 events.insert("posedge_" + mangle(sync_bit));
1393 break;
1394 case RTLIL::STn:
1395 log_assert(sync_bit.wire != nullptr);
1396 events.insert("negedge_" + mangle(sync_bit));
1397 break;
1398 case RTLIL::STe:
1399 log_assert(sync_bit.wire != nullptr);
1400 events.insert("posedge_" + mangle(sync_bit));
1401 events.insert("negedge_" + mangle(sync_bit));
1402 break;
1403
1404 case RTLIL::STa:
1405 events.insert("true");
1406 break;
1407
1408 case RTLIL::ST0:
1409 case RTLIL::ST1:
1410 case RTLIL::STg:
1411 case RTLIL::STi:
1412 log_assert(false);
1413 }
1414 if (!events.empty()) {
1415 f << indent << "if (";
1416 bool first = true;
1417 for (auto &event : events) {
1418 if (!first)
1419 f << " || ";
1420 first = false;
1421 f << event;
1422 }
1423 f << ") {\n";
1424 inc_indent();
1425 for (auto action : sync->actions)
1426 dump_assign(action);
1427 dec_indent();
1428 f << indent << "}\n";
1429 }
1430 }
1431 }
1432
1433 void dump_wire(const RTLIL::Wire *wire, bool is_local_context)
1434 {
1435 if (elided_wires.count(wire))
1436 return;
1437 if (localized_wires.count(wire) != is_local_context)
1438 return;
1439
1440 if (is_local_context) {
1441 dump_attrs(wire);
1442 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1443 } else {
1444 std::string width;
1445 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1446 width = wire->get_string_attribute(ID(cxxrtl_width));
1447 } else {
1448 width = std::to_string(wire->width);
1449 }
1450
1451 dump_attrs(wire);
1452 f << indent << (is_input_wire(wire) ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1453 if (wire->has_attribute(ID::init)) {
1454 f << " ";
1455 dump_const_init(wire->attributes.at(ID::init));
1456 }
1457 f << ";\n";
1458 if (edge_wires[wire]) {
1459 if (is_input_wire(wire)) {
1460 f << indent << "value<" << width << "> prev_" << mangle(wire);
1461 if (wire->has_attribute(ID::init)) {
1462 f << " ";
1463 dump_const_init(wire->attributes.at(ID::init));
1464 }
1465 f << ";\n";
1466 }
1467 for (auto edge_type : edge_types) {
1468 if (edge_type.first.wire == wire) {
1469 std::string prev, next;
1470 if (is_input_wire(wire)) {
1471 prev = "prev_" + mangle(edge_type.first.wire);
1472 next = mangle(edge_type.first.wire);
1473 } else {
1474 prev = mangle(edge_type.first.wire) + ".curr";
1475 next = mangle(edge_type.first.wire) + ".next";
1476 }
1477 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1478 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1479 if (edge_type.second != RTLIL::STn) {
1480 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1481 inc_indent();
1482 f << indent << "return !" << prev << " && " << next << ";\n";
1483 dec_indent();
1484 f << indent << "}\n";
1485 }
1486 if (edge_type.second != RTLIL::STp) {
1487 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1488 inc_indent();
1489 f << indent << "return " << prev << " && !" << next << ";\n";
1490 dec_indent();
1491 f << indent << "}\n";
1492 }
1493 }
1494 }
1495 }
1496 }
1497 }
1498
1499 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1500 {
1501 vector<const RTLIL::Cell*> init_cells;
1502 for (auto cell : module->cells())
1503 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1504 init_cells.push_back(cell);
1505
1506 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1507 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1508 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1509 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1510 });
1511
1512 dump_attrs(memory);
1513 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1514 << " { " << memory->size << "u";
1515 if (init_cells.empty()) {
1516 f << " };\n";
1517 } else {
1518 f << ",\n";
1519 inc_indent();
1520 for (auto cell : init_cells) {
1521 dump_attrs(cell);
1522 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1523 size_t width = cell->getParam(ID::WIDTH).as_int();
1524 size_t words = cell->getParam(ID::WORDS).as_int();
1525 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1526 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1527 inc_indent();
1528 for (size_t n = 0; n < words; n++) {
1529 if (n % 4 == 0)
1530 f << "\n" << indent;
1531 else
1532 f << " ";
1533 dump_const(data, width, n * width, /*fixed_width=*/true);
1534 f << ",";
1535 }
1536 dec_indent();
1537 f << "\n" << indent << "}},\n";
1538 }
1539 dec_indent();
1540 f << indent << "};\n";
1541 }
1542 }
1543
1544 void dump_eval_method(RTLIL::Module *module)
1545 {
1546 inc_indent();
1547 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1548 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1549 for (auto wire : module->wires()) {
1550 if (edge_wires[wire]) {
1551 for (auto edge_type : edge_types) {
1552 if (edge_type.first.wire == wire) {
1553 if (edge_type.second != RTLIL::STn) {
1554 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1555 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1556 }
1557 if (edge_type.second != RTLIL::STp) {
1558 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1559 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1560 }
1561 }
1562 }
1563 }
1564 }
1565 for (auto wire : module->wires())
1566 dump_wire(wire, /*is_local_context=*/true);
1567 for (auto node : schedule[module]) {
1568 switch (node.type) {
1569 case FlowGraph::Node::Type::CONNECT:
1570 dump_connect(node.connect);
1571 break;
1572 case FlowGraph::Node::Type::CELL_SYNC:
1573 dump_cell_sync(node.cell);
1574 break;
1575 case FlowGraph::Node::Type::CELL_EVAL:
1576 dump_cell_eval(node.cell);
1577 break;
1578 case FlowGraph::Node::Type::PROCESS:
1579 dump_process(node.process);
1580 break;
1581 }
1582 }
1583 }
1584 f << indent << "return converged;\n";
1585 dec_indent();
1586 }
1587
1588 void dump_commit_method(RTLIL::Module *module)
1589 {
1590 inc_indent();
1591 f << indent << "bool changed = false;\n";
1592 for (auto wire : module->wires()) {
1593 if (elided_wires.count(wire) || localized_wires.count(wire))
1594 continue;
1595 if (is_input_wire(wire)) {
1596 if (edge_wires[wire])
1597 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1598 continue;
1599 }
1600 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1601 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1602 }
1603 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1604 for (auto memory : module->memories) {
1605 if (!writable_memories[memory.second])
1606 continue;
1607 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1608 }
1609 for (auto cell : module->cells()) {
1610 if (is_internal_cell(cell->type))
1611 continue;
1612 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1613 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1614 }
1615 }
1616 f << indent << "return changed;\n";
1617 dec_indent();
1618 }
1619
1620 void dump_debug_info_method(RTLIL::Module *module)
1621 {
1622 size_t count_const_wires = 0;
1623 size_t count_alias_wires = 0;
1624 size_t count_member_wires = 0;
1625 size_t count_skipped_wires = 0;
1626 inc_indent();
1627 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1628 for (auto wire : module->wires()) {
1629 if (wire->name[0] != '\\')
1630 continue;
1631 if (debug_const_wires.count(wire)) {
1632 // Wire tied to a constant
1633 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1634 dump_const(debug_const_wires[wire]);
1635 f << ";\n";
1636 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1637 f << ", debug_item(const_" << mangle(wire) << "));\n";
1638 count_const_wires++;
1639 } else if (debug_alias_wires.count(wire)) {
1640 // Alias of a member wire
1641 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1642 f << ", debug_item(" << mangle(debug_alias_wires[wire]) << "));\n";
1643 count_alias_wires++;
1644 } else if (!localized_wires.count(wire)) {
1645 // Member wire
1646 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
1647 f << ", debug_item(" << mangle(wire) << "));\n";
1648 count_member_wires++;
1649 } else {
1650 count_skipped_wires++;
1651 }
1652 }
1653 for (auto &memory_it : module->memories) {
1654 if (memory_it.first[0] != '\\')
1655 continue;
1656 f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1657 f << ", debug_item(" << mangle(memory_it.second) << "));\n";
1658 }
1659 for (auto cell : module->cells()) {
1660 if (is_internal_cell(cell->type))
1661 continue;
1662 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1663 f << indent << mangle(cell) << access << "debug_info(items, ";
1664 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1665 }
1666 dec_indent();
1667
1668 log_debug("Debug information statistics for module %s:\n", log_id(module));
1669 log_debug(" Const wires: %zu\n", count_const_wires);
1670 log_debug(" Alias wires: %zu\n", count_alias_wires);
1671 log_debug(" Member wires: %zu\n", count_member_wires);
1672 log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
1673 }
1674
1675 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1676 {
1677 if (metadata_map.empty()) {
1678 f << "metadata_map()";
1679 return;
1680 }
1681 f << "metadata_map({\n";
1682 inc_indent();
1683 for (auto metadata_item : metadata_map) {
1684 if (!metadata_item.first.begins_with("\\"))
1685 continue;
1686 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1687 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1688 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1689 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1690 f << escape_cxx_string(metadata_item.second.decode_string());
1691 } else {
1692 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1693 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1694 f << "u";
1695 }
1696 f << " },\n";
1697 }
1698 dec_indent();
1699 f << indent << "})";
1700 }
1701
1702 void dump_module_intf(RTLIL::Module *module)
1703 {
1704 dump_attrs(module);
1705 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1706 if (module->has_attribute(ID(cxxrtl_template)))
1707 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1708 f << indent << "struct " << mangle(module) << " : public module {\n";
1709 inc_indent();
1710 for (auto wire : module->wires()) {
1711 if (wire->port_id != 0)
1712 dump_wire(wire, /*is_local_context=*/false);
1713 }
1714 f << "\n";
1715 f << indent << "bool eval() override {\n";
1716 dump_eval_method(module);
1717 f << indent << "}\n";
1718 f << "\n";
1719 f << indent << "bool commit() override {\n";
1720 dump_commit_method(module);
1721 f << indent << "}\n";
1722 f << "\n";
1723 if (debug_info) {
1724 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1725 dump_debug_info_method(module);
1726 f << indent << "}\n";
1727 f << "\n";
1728 }
1729 f << indent << "static std::unique_ptr<" << mangle(module);
1730 f << template_params(module, /*is_decl=*/false) << "> ";
1731 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1732 dec_indent();
1733 f << indent << "}; // struct " << mangle(module) << "\n";
1734 f << "\n";
1735 if (blackbox_specializations.count(module)) {
1736 // If templated black boxes are used, the constructor of any module which includes the black box cell
1737 // (which calls the declared but not defined in the generated code `create` function) may only be used
1738 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1739 // a forward-declared explicit specialization.
1740 //
1741 // Option (b) makes it possible to have the generated code and the black box implementation in different
1742 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1743 // a specialization for every combination of parameters the generated code may use; but since the main
1744 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1745 // be very few such combinations anyway.
1746 for (auto specialization : blackbox_specializations[module]) {
1747 f << indent << "template<>\n";
1748 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1749 f << mangle(module) << specialization << "::";
1750 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1751 f << "\n";
1752 }
1753 }
1754 } else {
1755 f << indent << "struct " << mangle(module) << " : public module {\n";
1756 inc_indent();
1757 for (auto wire : module->wires())
1758 dump_wire(wire, /*is_local_context=*/false);
1759 f << "\n";
1760 bool has_memories = false;
1761 for (auto memory : module->memories) {
1762 dump_memory(module, memory.second);
1763 has_memories = true;
1764 }
1765 if (has_memories)
1766 f << "\n";
1767 bool has_cells = false;
1768 for (auto cell : module->cells()) {
1769 if (is_internal_cell(cell->type))
1770 continue;
1771 dump_attrs(cell);
1772 RTLIL::Module *cell_module = module->design->module(cell->type);
1773 log_assert(cell_module != nullptr);
1774 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1775 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1776 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1777 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1778 dump_metadata_map(cell->parameters);
1779 f << ", ";
1780 dump_metadata_map(cell->attributes);
1781 f << ");\n";
1782 } else {
1783 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1784 }
1785 has_cells = true;
1786 }
1787 if (has_cells)
1788 f << "\n";
1789 f << indent << "bool eval() override;\n";
1790 f << indent << "bool commit() override;\n";
1791 if (debug_info)
1792 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
1793 dec_indent();
1794 f << indent << "}; // struct " << mangle(module) << "\n";
1795 f << "\n";
1796 }
1797 }
1798
1799 void dump_module_impl(RTLIL::Module *module)
1800 {
1801 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1802 return;
1803 f << indent << "bool " << mangle(module) << "::eval() {\n";
1804 dump_eval_method(module);
1805 f << indent << "}\n";
1806 f << "\n";
1807 f << indent << "bool " << mangle(module) << "::commit() {\n";
1808 dump_commit_method(module);
1809 f << indent << "}\n";
1810 f << "\n";
1811 if (debug_info) {
1812 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
1813 dump_debug_info_method(module);
1814 f << indent << "}\n";
1815 f << "\n";
1816 }
1817 }
1818
1819 void dump_design(RTLIL::Design *design)
1820 {
1821 RTLIL::Module *top_module = nullptr;
1822 std::vector<RTLIL::Module*> modules;
1823 TopoSort<RTLIL::Module*> topo_design;
1824 for (auto module : design->modules()) {
1825 if (!design->selected_module(module))
1826 continue;
1827 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
1828 modules.push_back(module); // cxxrtl blackboxes first
1829 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
1830 continue;
1831 if (module->get_bool_attribute(ID::top))
1832 top_module = module;
1833
1834 topo_design.node(module);
1835 for (auto cell : module->cells()) {
1836 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
1837 continue;
1838 RTLIL::Module *cell_module = design->module(cell->type);
1839 log_assert(cell_module != nullptr);
1840 topo_design.edge(cell_module, module);
1841 }
1842 }
1843 log_assert(topo_design.sort());
1844 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
1845
1846 if (split_intf) {
1847 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
1848 std::string include_guard = design_ns + "_header";
1849 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
1850
1851 f << "#ifndef " << include_guard << "\n";
1852 f << "#define " << include_guard << "\n";
1853 f << "\n";
1854 if (top_module != nullptr && debug_info) {
1855 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
1856 f << "\n";
1857 f << "#ifdef __cplusplus\n";
1858 f << "extern \"C\" {\n";
1859 f << "#endif\n";
1860 f << "\n";
1861 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
1862 f << "\n";
1863 f << "#ifdef __cplusplus\n";
1864 f << "}\n";
1865 f << "#endif\n";
1866 f << "\n";
1867 } else {
1868 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
1869 f << "\n";
1870 }
1871 f << "#ifdef __cplusplus\n";
1872 f << "\n";
1873 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1874 f << "\n";
1875 f << "using namespace cxxrtl;\n";
1876 f << "\n";
1877 f << "namespace " << design_ns << " {\n";
1878 f << "\n";
1879 for (auto module : modules)
1880 dump_module_intf(module);
1881 f << "} // namespace " << design_ns << "\n";
1882 f << "\n";
1883 f << "#endif // __cplusplus\n";
1884 f << "\n";
1885 f << "#endif\n";
1886 *intf_f << f.str(); f.str("");
1887 }
1888
1889 if (split_intf)
1890 f << "#include \"" << intf_filename << "\"\n";
1891 else
1892 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
1893 f << "\n";
1894 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
1895 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1896 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
1897 f << "#endif\n";
1898 f << "\n";
1899 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
1900 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
1901 f << "#endif\n";
1902 f << "\n";
1903 f << "using namespace cxxrtl_yosys;\n";
1904 f << "\n";
1905 f << "namespace " << design_ns << " {\n";
1906 f << "\n";
1907 for (auto module : modules) {
1908 if (!split_intf)
1909 dump_module_intf(module);
1910 dump_module_impl(module);
1911 }
1912 f << "} // namespace " << design_ns << "\n";
1913 f << "\n";
1914 if (top_module != nullptr && debug_info) {
1915 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
1916 inc_indent();
1917 f << indent << "return new _cxxrtl_toplevel { ";
1918 f << "std::make_unique<" << design_ns << "::" << mangle(top_module) << ">()";
1919 f << " };\n";
1920 dec_indent();
1921 f << "}\n";
1922 }
1923
1924 *impl_f << f.str(); f.str("");
1925 }
1926
1927 // Edge-type sync rules require us to emit edge detectors, which require coordination between
1928 // eval and commit phases. To do this we need to collect them upfront.
1929 //
1930 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
1931 // operate at wire bit granularity; it is possible to have code similar to:
1932 // wire [3:0] clocks;
1933 // always @(posedge clocks[0]) ...
1934 // To handle this we track edge sensitivity both for wires and wire bits.
1935 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
1936 {
1937 signal = sigmap(signal);
1938 log_assert(signal.is_wire() && signal.is_bit());
1939 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
1940
1941 RTLIL::SigBit sigbit = signal[0];
1942 if (!edge_types.count(sigbit))
1943 edge_types[sigbit] = type;
1944 else if (edge_types[sigbit] != type)
1945 edge_types[sigbit] = RTLIL::STe;
1946 edge_wires.insert(signal.as_wire());
1947 }
1948
1949 void analyze_design(RTLIL::Design *design)
1950 {
1951 bool has_feedback_arcs = false;
1952 bool has_buffered_wires = false;
1953
1954 for (auto module : design->modules()) {
1955 if (!design->selected_module(module))
1956 continue;
1957
1958 SigMap &sigmap = sigmaps[module];
1959 sigmap.set(module);
1960
1961 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1962 for (auto port : module->ports) {
1963 RTLIL::Wire *wire = module->wire(port);
1964 if (wire->has_attribute(ID(cxxrtl_edge))) {
1965 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
1966 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
1967 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
1968 log_id(module), log_signal(wire));
1969
1970 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
1971 for (int i = 0; i < GetSize(wire); i++) {
1972 RTLIL::SigSpec wire_sig = wire;
1973 switch (edges[i]) {
1974 case '-': break;
1975 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
1976 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
1977 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
1978 default:
1979 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
1980 "other than '-', 'p', 'n', or 'a'.\n",
1981 log_id(module), log_signal(wire));
1982 }
1983 }
1984 }
1985 }
1986
1987 // Black boxes converge by default, since their implementations are quite unlikely to require
1988 // internal propagation of comb signals.
1989 eval_converges[module] = true;
1990 continue;
1991 }
1992
1993 FlowGraph flow;
1994
1995 for (auto conn : module->connections())
1996 flow.add_node(conn);
1997
1998 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
1999 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
2000 pool<const RTLIL::Cell*>> memwr_per_domain;
2001 for (auto cell : module->cells()) {
2002 if (!cell->known())
2003 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2004
2005 RTLIL::Module *cell_module = design->module(cell->type);
2006 if (cell_module &&
2007 cell_module->get_blackbox_attribute() &&
2008 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2009 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2010
2011 if (cell_module &&
2012 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2013 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2014 blackbox_specializations[cell_module].insert(template_args(cell));
2015
2016 FlowGraph::Node *node = flow.add_node(cell);
2017
2018 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2019 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
2020 if (cell->getPort(ID::CLK).is_wire())
2021 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2022 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2023 }
2024 // Similar for memory port cells.
2025 if (cell->type.in(ID($memrd), ID($memwr))) {
2026 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2027 if (cell->getPort(ID::CLK).is_wire())
2028 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2029 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2030 }
2031 memrw_cell_nodes[cell] = node;
2032 }
2033 // Optimize access to read-only memories.
2034 if (cell->type == ID($memwr))
2035 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2036 // Collect groups of memory write ports in the same domain.
2037 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2038 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2039 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2040 memwr_per_domain[{clk_bit, memory}].insert(cell);
2041 }
2042 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2043 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2044 if (cell->type.in(ID($mem)))
2045 log_assert(false);
2046 }
2047 for (auto cell : module->cells()) {
2048 // Collect groups of memory write ports read by every transparent read port.
2049 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2050 cell->getParam(ID::TRANSPARENT).as_bool()) {
2051 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2052 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2053 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2054 transparent_for[cell].insert(memwr_cell);
2055 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2056 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2057 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2058 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2059 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2060 }
2061 }
2062 }
2063
2064 for (auto proc : module->processes) {
2065 flow.add_node(proc.second);
2066
2067 for (auto sync : proc.second->syncs)
2068 switch (sync->type) {
2069 // Edge-type sync rules require pre-registration.
2070 case RTLIL::STp:
2071 case RTLIL::STn:
2072 case RTLIL::STe:
2073 register_edge_signal(sigmap, sync->signal, sync->type);
2074 break;
2075
2076 // Level-type sync rules require no special handling.
2077 case RTLIL::ST0:
2078 case RTLIL::ST1:
2079 case RTLIL::STa:
2080 break;
2081
2082 case RTLIL::STg:
2083 log_cmd_error("Global clock is not supported.\n");
2084
2085 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2086 // attribute regardless of input.
2087 case RTLIL::STi:
2088 log_assert(false);
2089 }
2090 }
2091
2092 for (auto wire : module->wires()) {
2093 if (!flow.is_elidable(wire)) continue;
2094 if (wire->port_id != 0) continue;
2095 if (wire->get_bool_attribute(ID::keep)) continue;
2096 if (wire->name.begins_with("$") && !elide_internal) continue;
2097 if (wire->name.begins_with("\\") && !elide_public) continue;
2098 if (edge_wires[wire]) continue;
2099 log_assert(flow.wire_comb_defs[wire].size() == 1);
2100 elided_wires[wire] = **flow.wire_comb_defs[wire].begin();
2101 }
2102
2103 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2104 for (auto wire_comb_def : flow.wire_comb_defs)
2105 for (auto node : wire_comb_def.second)
2106 node_defs[node].insert(wire_comb_def.first);
2107
2108 Scheduler<FlowGraph::Node> scheduler;
2109 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2110 for (auto node : flow.nodes)
2111 node_map[node] = scheduler.add(node);
2112 for (auto node_def : node_defs) {
2113 auto vertex = node_map[node_def.first];
2114 for (auto wire : node_def.second)
2115 for (auto succ_node : flow.wire_uses[wire]) {
2116 auto succ_vertex = node_map[succ_node];
2117 vertex->succs.insert(succ_vertex);
2118 succ_vertex->preds.insert(vertex);
2119 }
2120 }
2121
2122 auto eval_order = scheduler.schedule();
2123 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2124 pool<const RTLIL::Wire*> feedback_wires;
2125 for (auto vertex : eval_order) {
2126 auto node = vertex->data;
2127 schedule[module].push_back(*node);
2128 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2129 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2130 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2131 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2132 evaluated.insert(node);
2133 for (auto wire : node_defs[node])
2134 for (auto succ_node : flow.wire_uses[wire])
2135 if (evaluated[succ_node]) {
2136 feedback_wires.insert(wire);
2137 // Feedback wires may never be elided because feedback requires state, but the point of elision
2138 // (and localization) is to eliminate state.
2139 elided_wires.erase(wire);
2140 }
2141 }
2142
2143 if (!feedback_wires.empty()) {
2144 has_feedback_arcs = true;
2145 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2146 for (auto wire : feedback_wires)
2147 log(" %s\n", log_id(wire));
2148 log("\n");
2149 }
2150
2151 for (auto wire : module->wires()) {
2152 if (feedback_wires[wire]) continue;
2153 if (wire->port_id != 0) continue;
2154 if (wire->get_bool_attribute(ID::keep)) continue;
2155 if (wire->name.begins_with("$") && !localize_internal) continue;
2156 if (wire->name.begins_with("\\") && !localize_public) continue;
2157 if (edge_wires[wire]) continue;
2158 if (flow.wire_sync_defs.count(wire) > 0) continue;
2159 localized_wires.insert(wire);
2160 }
2161
2162 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2163 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2164 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2165 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2166 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2167 // also require more than one delta cycle to converge.
2168 pool<const RTLIL::Wire*> buffered_wires;
2169 for (auto wire : module->wires()) {
2170 if (flow.wire_comb_defs[wire].size() > 0 && !elided_wires.count(wire) && !localized_wires[wire]) {
2171 if (!feedback_wires[wire])
2172 buffered_wires.insert(wire);
2173 }
2174 }
2175 if (!buffered_wires.empty()) {
2176 has_buffered_wires = true;
2177 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2178 for (auto wire : buffered_wires)
2179 log(" %s\n", log_id(wire));
2180 log("\n");
2181 }
2182
2183 eval_converges[module] = feedback_wires.empty() && buffered_wires.empty();
2184
2185 if (debug_info) {
2186 // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
2187 // at essentially zero additional cost.
2188 //
2189 // Note that the information collected here can't be used for optimizing the netlist: debug information queries
2190 // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
2191 for (auto wire : module->wires()) {
2192 if (wire->name[0] != '\\')
2193 continue;
2194 if (!localized_wires[wire])
2195 continue;
2196 const RTLIL::Wire *wire_it = wire;
2197 while (1) {
2198 if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it]))
2199 break; // not an alias: complex def
2200 log_assert(flow.wire_comb_defs[wire_it].size() == 1);
2201 FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin();
2202 if (node->type != FlowGraph::Node::Type::CONNECT)
2203 break; // not an alias: def by cell
2204 RTLIL::SigSpec rhs_sig = node->connect.second;
2205 if (rhs_sig.is_wire()) {
2206 RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
2207 if (localized_wires[rhs_wire]) {
2208 wire_it = rhs_wire; // maybe an alias
2209 } else {
2210 debug_alias_wires[wire] = rhs_wire; // is an alias
2211 break;
2212 }
2213 } else if (rhs_sig.is_fully_const()) {
2214 debug_const_wires[wire] = rhs_sig.as_const(); // is a const
2215 break;
2216 } else {
2217 break; // not an alias: complex rhs
2218 }
2219 }
2220 }
2221 }
2222 }
2223 if (has_feedback_arcs || has_buffered_wires) {
2224 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2225 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2226 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2227 const char *why_pessimistic = nullptr;
2228 if (has_feedback_arcs)
2229 why_pessimistic = "feedback wires";
2230 else if (has_buffered_wires)
2231 why_pessimistic = "buffered combinatorial wires";
2232 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2233 if (!max_opt_level)
2234 log("Increasing the optimization level may eliminate %s from the design.\n", why_pessimistic);
2235 }
2236 }
2237
2238 void check_design(RTLIL::Design *design, bool &has_sync_init, bool &has_packed_mem)
2239 {
2240 has_sync_init = has_packed_mem = false;
2241
2242 for (auto module : design->modules()) {
2243 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2244 continue;
2245
2246 if (!design->selected_whole_module(module))
2247 if (design->selected_module(module))
2248 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2249 if (!design->selected_module(module))
2250 continue;
2251
2252 for (auto proc : module->processes)
2253 for (auto sync : proc.second->syncs)
2254 if (sync->type == RTLIL::STi)
2255 has_sync_init = true;
2256
2257 for (auto cell : module->cells())
2258 if (cell->type == ID($mem))
2259 has_packed_mem = true;
2260 }
2261 }
2262
2263 void prepare_design(RTLIL::Design *design)
2264 {
2265 bool did_anything = false;
2266 bool has_sync_init, has_packed_mem;
2267 log_push();
2268 check_design(design, has_sync_init, has_packed_mem);
2269 if (run_proc_flatten) {
2270 Pass::call(design, "proc");
2271 Pass::call(design, "flatten");
2272 did_anything = true;
2273 } else if (has_sync_init) {
2274 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2275 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2276 Pass::call(design, "proc_prune");
2277 Pass::call(design, "proc_clean");
2278 Pass::call(design, "proc_init");
2279 did_anything = true;
2280 }
2281 if (has_packed_mem) {
2282 Pass::call(design, "memory_unpack");
2283 did_anything = true;
2284 }
2285 // Recheck the design if it was modified.
2286 if (has_sync_init || has_packed_mem)
2287 check_design(design, has_sync_init, has_packed_mem);
2288 log_assert(!(has_sync_init || has_packed_mem));
2289 log_pop();
2290 if (did_anything)
2291 log_spacer();
2292 analyze_design(design);
2293 }
2294 };
2295
2296 struct CxxrtlBackend : public Backend {
2297 static const int DEFAULT_OPT_LEVEL = 5;
2298 static const int DEFAULT_DEBUG_LEVEL = 1;
2299
2300 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2301 void help() YS_OVERRIDE
2302 {
2303 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2304 log("\n");
2305 log(" write_cxxrtl [options] [filename]\n");
2306 log("\n");
2307 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2308 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2309 log("\n");
2310 log("The following driver may be used as an example for a design with a single clock\n");
2311 log("driving rising edge triggered flip-flops:\n");
2312 log("\n");
2313 log(" #include \"top.cc\"\n");
2314 log("\n");
2315 log(" int main() {\n");
2316 log(" cxxrtl_design::p_top top;\n");
2317 log(" top.step();\n");
2318 log(" while (1) {\n");
2319 log(" /* user logic */\n");
2320 log(" top.p_clk = value<1> {0u};\n");
2321 log(" top.step();\n");
2322 log(" top.p_clk = value<1> {1u};\n");
2323 log(" top.step();\n");
2324 log(" }\n");
2325 log(" }\n");
2326 log("\n");
2327 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2328 log("subject to race conditions. If, in the example above, the user logic would run\n");
2329 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2330 log("\n");
2331 log("This backend supports replacing parts of the design with black boxes implemented\n");
2332 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2333 log("and the generated code consists only of an interface and a factory function.\n");
2334 log("The driver must implement the factory function that creates an implementation of\n");
2335 log("the black box, taking into account the parameters it is instantiated with.\n");
2336 log("\n");
2337 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2338 log("a synchronous debug sink:\n");
2339 log("\n");
2340 log(" (* cxxrtl_blackbox *)\n");
2341 log(" module debug(...);\n");
2342 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2343 log(" input en;\n");
2344 log(" input [7:0] i_data;\n");
2345 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2346 log(" endmodule\n");
2347 log("\n");
2348 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2349 log("\n");
2350 log(" struct bb_p_debug : public module {\n");
2351 log(" value<1> p_clk;\n");
2352 log(" bool posedge_p_clk() const { /* ... */ }\n");
2353 log(" value<1> p_en;\n");
2354 log(" value<8> p_i_data;\n");
2355 log(" wire<8> p_o_data;\n");
2356 log("\n");
2357 log(" bool eval() override;\n");
2358 log(" bool commit() override;\n");
2359 log("\n");
2360 log(" static std::unique_ptr<bb_p_debug>\n");
2361 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2362 log(" };\n");
2363 log("\n");
2364 log("The `create' function must be implemented by the driver. For example, it could\n");
2365 log("always provide an implementation logging the values to standard error stream:\n");
2366 log("\n");
2367 log(" namespace cxxrtl_design {\n");
2368 log("\n");
2369 log(" struct stderr_debug : public bb_p_debug {\n");
2370 log(" bool eval() override {\n");
2371 log(" if (posedge_p_clk() && p_en)\n");
2372 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2373 log(" p_o_data.next = p_i_data;\n");
2374 log(" return bb_p_debug::eval();\n");
2375 log(" }\n");
2376 log(" };\n");
2377 log("\n");
2378 log(" std::unique_ptr<bb_p_debug>\n");
2379 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2380 log(" cxxrtl::metadata_map attributes) {\n");
2381 log(" return std::make_unique<stderr_debug>();\n");
2382 log(" }\n");
2383 log("\n");
2384 log(" }\n");
2385 log("\n");
2386 log("For complex applications of black boxes, it is possible to parameterize their\n");
2387 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2388 log("interface for a configurable width debug sink:\n");
2389 log("\n");
2390 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2391 log(" module debug(...);\n");
2392 log(" parameter WIDTH = 8;\n");
2393 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2394 log(" input en;\n");
2395 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2396 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2397 log(" endmodule\n");
2398 log("\n");
2399 log("For this parametric HDL interface, this backend will generate the following C++\n");
2400 log("interface (only the differences are shown):\n");
2401 log("\n");
2402 log(" template<size_t WIDTH>\n");
2403 log(" struct bb_p_debug : public module {\n");
2404 log(" // ...\n");
2405 log(" value<WIDTH> p_i_data;\n");
2406 log(" wire<WIDTH> p_o_data;\n");
2407 log(" // ...\n");
2408 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2409 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2410 log(" };\n");
2411 log("\n");
2412 log("The `create' function must be implemented by the driver, specialized for every\n");
2413 log("possible combination of template parameters. (Specialization is necessary to\n");
2414 log("enable separate compilation of generated code and black box implementations.)\n");
2415 log("\n");
2416 log(" template<size_t SIZE>\n");
2417 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2418 log(" // ...\n");
2419 log(" };\n");
2420 log("\n");
2421 log(" template<>\n");
2422 log(" std::unique_ptr<bb_p_debug<8>>\n");
2423 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2424 log(" cxxrtl::metadata_map attributes) {\n");
2425 log(" return std::make_unique<stderr_debug<8>>();\n");
2426 log(" }\n");
2427 log("\n");
2428 log("The following attributes are recognized by this backend:\n");
2429 log("\n");
2430 log(" cxxrtl_blackbox\n");
2431 log(" only valid on modules. if specified, the module contents are ignored,\n");
2432 log(" and the generated code includes only the module interface and a factory\n");
2433 log(" function, which will be called to instantiate the module.\n");
2434 log("\n");
2435 log(" cxxrtl_edge\n");
2436 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2437 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2438 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2439 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2440 log("\n");
2441 log(" cxxrtl_template\n");
2442 log(" only valid on black boxes. must contain a space separated sequence of\n");
2443 log(" identifiers that have a corresponding black box parameters. for each\n");
2444 log(" of them, the generated code includes a `size_t` template parameter.\n");
2445 log("\n");
2446 log(" cxxrtl_width\n");
2447 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2448 log(" is directly inserted into generated code.\n");
2449 log("\n");
2450 log(" cxxrtl_comb, cxxrtl_sync\n");
2451 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2452 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2453 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2454 log(" if neither is specified, the output will be pessimistically treated as\n");
2455 log(" driven by both combinatorial and synchronous logic.\n");
2456 log("\n");
2457 log("The following options are supported by this backend:\n");
2458 log("\n");
2459 log(" -header\n");
2460 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2461 log(" if specified, the backend must be called with a filename, and filename\n");
2462 log(" of the interface is derived from filename of the implementation.\n");
2463 log(" otherwise, interface and implementation are generated together.\n");
2464 log("\n");
2465 log(" -namespace <ns-name>\n");
2466 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2467 log(" \"cxxrtl_design\" is used.\n");
2468 log("\n");
2469 log(" -O <level>\n");
2470 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2471 log(" levels dramatically decrease compile and run time, and highest level\n");
2472 log(" possible for a design should be used.\n");
2473 log("\n");
2474 log(" -O0\n");
2475 log(" no optimization.\n");
2476 log("\n");
2477 log(" -O1\n");
2478 log(" elide internal wires if possible.\n");
2479 log("\n");
2480 log(" -O2\n");
2481 log(" like -O1, and localize internal wires if possible.\n");
2482 log("\n");
2483 log(" -O3\n");
2484 log(" like -O2, and elide public wires not marked (*keep*) if possible.\n");
2485 log("\n");
2486 log(" -O4\n");
2487 log(" like -O3, and localize public wires not marked (*keep*) if possible.\n");
2488 log("\n");
2489 log(" -O5\n");
2490 log(" like -O4, and run `proc; flatten` first.\n");
2491 log("\n");
2492 log(" -g <level>\n");
2493 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2494 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2495 log("\n");
2496 log(" -g0\n");
2497 log(" no debug information.\n");
2498 log("\n");
2499 log(" -g1\n");
2500 log(" debug information for non-optimized public wires. this also makes it\n");
2501 log(" possible to use the C API.\n");
2502 log("\n");
2503 }
2504
2505 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
2506 {
2507 int opt_level = DEFAULT_OPT_LEVEL;
2508 int debug_level = DEFAULT_DEBUG_LEVEL;
2509 CxxrtlWorker worker;
2510
2511 log_header(design, "Executing CXXRTL backend.\n");
2512
2513 size_t argidx;
2514 for (argidx = 1; argidx < args.size(); argidx++)
2515 {
2516 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2517 opt_level = std::stoi(args[++argidx]);
2518 continue;
2519 }
2520 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2521 opt_level = std::stoi(args[argidx].substr(2));
2522 continue;
2523 }
2524 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2525 debug_level = std::stoi(args[++argidx]);
2526 continue;
2527 }
2528 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2529 debug_level = std::stoi(args[argidx].substr(2));
2530 continue;
2531 }
2532 if (args[argidx] == "-header") {
2533 worker.split_intf = true;
2534 continue;
2535 }
2536 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2537 worker.design_ns = args[++argidx];
2538 continue;
2539 }
2540 break;
2541 }
2542 extra_args(f, filename, args, argidx);
2543
2544 switch (opt_level) {
2545 // the highest level here must match DEFAULT_OPT_LEVEL
2546 case 5:
2547 worker.max_opt_level = true;
2548 worker.run_proc_flatten = true;
2549 YS_FALLTHROUGH
2550 case 4:
2551 worker.localize_public = true;
2552 YS_FALLTHROUGH
2553 case 3:
2554 worker.elide_public = true;
2555 YS_FALLTHROUGH
2556 case 2:
2557 worker.localize_internal = true;
2558 YS_FALLTHROUGH
2559 case 1:
2560 worker.elide_internal = true;
2561 YS_FALLTHROUGH
2562 case 0:
2563 break;
2564 default:
2565 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2566 }
2567
2568 switch (debug_level) {
2569 // the highest level here must match DEFAULT_DEBUG_LEVEL
2570 case 1:
2571 worker.debug_info = true;
2572 YS_FALLTHROUGH
2573 case 0:
2574 break;
2575 default:
2576 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2577 }
2578
2579 std::ofstream intf_f;
2580 if (worker.split_intf) {
2581 if (filename == "<stdout>")
2582 log_cmd_error("Option -header must be used with a filename.\n");
2583
2584 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2585 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2586 if (intf_f.fail())
2587 log_cmd_error("Can't open file `%s' for writing: %s\n",
2588 worker.intf_filename.c_str(), strerror(errno));
2589
2590 worker.intf_f = &intf_f;
2591 }
2592 worker.impl_f = f;
2593
2594 worker.prepare_design(design);
2595 worker.dump_design(design);
2596 }
2597 } CxxrtlBackend;
2598
2599 PRIVATE_NAMESPACE_END