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Merge pull request #2487 from whitequark/cxxrtl-outlining
[yosys.git] / backends / cxxrtl / cxxrtl_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/mem.h"
26 #include "kernel/log.h"
27
28 USING_YOSYS_NAMESPACE
29 PRIVATE_NAMESPACE_BEGIN
30
31 // [[CITE]]
32 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
33 // Information Processing Letters, Vol. 47, pp 319-323, 1993
34 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
35
36 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
37 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
38 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
39 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
40 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
41 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
42 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
43 template<class T>
44 struct Scheduler {
45 struct Vertex {
46 T *data;
47 Vertex *prev, *next;
48 pool<Vertex*, hash_ptr_ops> preds, succs;
49
50 Vertex() : data(NULL), prev(this), next(this) {}
51 Vertex(T *data) : data(data), prev(NULL), next(NULL) {}
52
53 bool empty() const
54 {
55 log_assert(data == NULL);
56 if (next == this) {
57 log_assert(prev == next);
58 return true;
59 }
60 return false;
61 }
62
63 void link(Vertex *list)
64 {
65 log_assert(prev == NULL && next == NULL);
66 next = list;
67 prev = list->prev;
68 list->prev->next = this;
69 list->prev = this;
70 }
71
72 void unlink()
73 {
74 log_assert(prev->next == this && next->prev == this);
75 prev->next = next;
76 next->prev = prev;
77 next = prev = NULL;
78 }
79
80 int delta() const
81 {
82 return succs.size() - preds.size();
83 }
84 };
85
86 std::vector<Vertex*> vertices;
87 Vertex *sources = new Vertex;
88 Vertex *sinks = new Vertex;
89 dict<int, Vertex*> bins;
90
91 ~Scheduler()
92 {
93 delete sources;
94 delete sinks;
95 for (auto bin : bins)
96 delete bin.second;
97 for (auto vertex : vertices)
98 delete vertex;
99 }
100
101 Vertex *add(T *data)
102 {
103 Vertex *vertex = new Vertex(data);
104 vertices.push_back(vertex);
105 return vertex;
106 }
107
108 void relink(Vertex *vertex)
109 {
110 if (vertex->succs.empty())
111 vertex->link(sinks);
112 else if (vertex->preds.empty())
113 vertex->link(sources);
114 else {
115 int delta = vertex->delta();
116 if (!bins.count(delta))
117 bins[delta] = new Vertex;
118 vertex->link(bins[delta]);
119 }
120 }
121
122 Vertex *remove(Vertex *vertex)
123 {
124 vertex->unlink();
125 for (auto pred : vertex->preds) {
126 if (pred == vertex)
127 continue;
128 log_assert(pred->succs[vertex]);
129 pred->unlink();
130 pred->succs.erase(vertex);
131 relink(pred);
132 }
133 for (auto succ : vertex->succs) {
134 if (succ == vertex)
135 continue;
136 log_assert(succ->preds[vertex]);
137 succ->unlink();
138 succ->preds.erase(vertex);
139 relink(succ);
140 }
141 vertex->preds.clear();
142 vertex->succs.clear();
143 return vertex;
144 }
145
146 std::vector<Vertex*> schedule()
147 {
148 std::vector<Vertex*> s1, s2r;
149 for (auto vertex : vertices)
150 relink(vertex);
151 bool bins_empty = false;
152 while (!(sinks->empty() && sources->empty() && bins_empty)) {
153 while (!sinks->empty())
154 s2r.push_back(remove(sinks->next));
155 while (!sources->empty())
156 s1.push_back(remove(sources->next));
157 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
158 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
159 // naive implementation of find-max-key.
160 bins_empty = true;
161 bins.template sort<std::greater<int>>();
162 for (auto bin : bins) {
163 if (!bin.second->empty()) {
164 bins_empty = false;
165 s1.push_back(remove(bin.second->next));
166 break;
167 }
168 }
169 }
170 s1.insert(s1.end(), s2r.rbegin(), s2r.rend());
171 return s1;
172 }
173 };
174
175 bool is_unary_cell(RTLIL::IdString type)
176 {
177 return type.in(
178 ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
179 ID($pos), ID($neg));
180 }
181
182 bool is_binary_cell(RTLIL::IdString type)
183 {
184 return type.in(
185 ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
186 ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
187 ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
188 ID($add), ID($sub), ID($mul), ID($div), ID($mod));
189 }
190
191 bool is_extending_cell(RTLIL::IdString type)
192 {
193 return !type.in(
194 ID($logic_not), ID($logic_and), ID($logic_or),
195 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
196 }
197
198 bool is_inlinable_cell(RTLIL::IdString type)
199 {
200 return is_unary_cell(type) || is_binary_cell(type) || type.in(
201 ID($mux), ID($concat), ID($slice), ID($pmux));
202 }
203
204 bool is_ff_cell(RTLIL::IdString type)
205 {
206 return type.in(
207 ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
208 ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
209 ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
210 }
211
212 bool is_internal_cell(RTLIL::IdString type)
213 {
214 return !type.isPublic() && !type.begins_with("$paramod");
215 }
216
217 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
218 {
219 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
220 log_assert(cell_module != nullptr);
221 return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
222 }
223
224 enum class CxxrtlPortType {
225 UNKNOWN = 0, // or mixed comb/sync
226 COMB = 1,
227 SYNC = 2,
228 };
229
230 CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
231 {
232 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
233 if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
234 return CxxrtlPortType::UNKNOWN;
235 RTLIL::Wire *cell_output_wire = cell_module->wire(port);
236 log_assert(cell_output_wire != nullptr);
237 bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb));
238 bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync));
239 if (is_comb && is_sync)
240 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
241 log_id(cell_module), log_signal(cell_output_wire));
242 else if (is_comb)
243 return CxxrtlPortType::COMB;
244 else if (is_sync)
245 return CxxrtlPortType::SYNC;
246 return CxxrtlPortType::UNKNOWN;
247 }
248
249 bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
250 {
251 return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
252 }
253
254 bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
255 {
256 return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
257 }
258
259 struct FlowGraph {
260 struct Node {
261 enum class Type {
262 CONNECT,
263 CELL_SYNC,
264 CELL_EVAL,
265 PROCESS
266 };
267
268 Type type;
269 RTLIL::SigSig connect = {};
270 const RTLIL::Cell *cell = NULL;
271 const RTLIL::Process *process = NULL;
272 };
273
274 std::vector<Node*> nodes;
275 dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
276 dict<const RTLIL::Wire*, bool> wire_def_inlinable, wire_use_inlinable;
277 dict<RTLIL::SigBit, bool> bit_has_state;
278
279 ~FlowGraph()
280 {
281 for (auto node : nodes)
282 delete node;
283 }
284
285 void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool inlinable)
286 {
287 for (auto chunk : sig.chunks())
288 if (chunk.wire) {
289 if (is_ff) {
290 // A sync def means that a wire holds design state because it is driven directly by
291 // a flip-flop output. Such a wire can never be unbuffered.
292 wire_sync_defs[chunk.wire].insert(node);
293 } else {
294 // A comb def means that a wire doesn't hold design state. It might still be connected,
295 // indirectly, to a flip-flop output.
296 wire_comb_defs[chunk.wire].insert(node);
297 }
298 }
299 for (auto bit : sig.bits())
300 bit_has_state[bit] |= is_ff;
301 // Only comb defs of an entire wire in the right order can be inlined.
302 if (!is_ff && sig.is_wire())
303 wire_def_inlinable[sig.as_wire()] = inlinable;
304 }
305
306 void add_uses(Node *node, const RTLIL::SigSpec &sig)
307 {
308 for (auto chunk : sig.chunks())
309 if (chunk.wire) {
310 wire_uses[chunk.wire].insert(node);
311 // Only a single use of an entire wire in the right order can be inlined.
312 // (But the use can include other chunks.)
313 if (!wire_use_inlinable.count(chunk.wire))
314 wire_use_inlinable[chunk.wire] = true;
315 else
316 wire_use_inlinable[chunk.wire] = false;
317 }
318 }
319
320 bool is_inlinable(const RTLIL::Wire *wire) const
321 {
322 if (wire_def_inlinable.count(wire) && wire_use_inlinable.count(wire))
323 return wire_def_inlinable.at(wire) && wire_use_inlinable.at(wire);
324 return false;
325 }
326
327 // Connections
328 void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
329 {
330 add_defs(node, conn.first, /*is_ff=*/false, /*inlinable=*/true);
331 add_uses(node, conn.second);
332 }
333
334 Node *add_node(const RTLIL::SigSig &conn)
335 {
336 Node *node = new Node;
337 node->type = Node::Type::CONNECT;
338 node->connect = conn;
339 nodes.push_back(node);
340 add_connect_defs_uses(node, conn);
341 return node;
342 }
343
344 // Cells
345 void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
346 {
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
352 //
353 // wire<1> i_tmp;
354 // cell->p_i = i_tmp.curr;
355 // cell->eval();
356 // i_tmp.next = cell->p_o.curr;
357 //
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
361 //
362 // value<1> i_tmp;
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
365 // cell->eval();
366 //
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn : cell->connections())
374 if (cell->output(conn.first))
375 if (is_cxxrtl_sync_port(cell, conn.first)) {
376 // See note regarding inlinability below.
377 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
378 }
379 }
380
381 void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
382 {
383 for (auto conn : cell->connections()) {
384 if (cell->output(conn.first)) {
385 if (is_inlinable_cell(cell->type))
386 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/true);
387 else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
388 add_defs(node, conn.second, /*is_ff=*/true, /*inlinable=*/false);
389 else if (is_internal_cell(cell->type))
390 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
391 else if (!is_cxxrtl_sync_port(cell, conn.first)) {
392 // Although at first it looks like outputs of user-defined cells may always be inlined, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in inlining. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be inlined, but should be rare in practical designs and don't justify
396 // the infrastructure required to inline outputs of cells with many of them.
397 add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
398 }
399 }
400 if (cell->input(conn.first))
401 add_uses(node, conn.second);
402 }
403 }
404
405 Node *add_node(const RTLIL::Cell *cell)
406 {
407 log_assert(cell->known());
408
409 bool has_fully_sync_outputs = false;
410 for (auto conn : cell->connections())
411 if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
412 has_fully_sync_outputs = true;
413 break;
414 }
415 if (has_fully_sync_outputs) {
416 Node *node = new Node;
417 node->type = Node::Type::CELL_SYNC;
418 node->cell = cell;
419 nodes.push_back(node);
420 add_cell_sync_defs(node, cell);
421 }
422
423 Node *node = new Node;
424 node->type = Node::Type::CELL_EVAL;
425 node->cell = cell;
426 nodes.push_back(node);
427 add_cell_eval_defs_uses(node, cell);
428 return node;
429 }
430
431 // Processes
432 void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
433 {
434 for (auto &action : case_->actions) {
435 add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
436 add_uses(node, action.second);
437 }
438 for (auto sub_switch : case_->switches) {
439 add_uses(node, sub_switch->signal);
440 for (auto sub_case : sub_switch->cases) {
441 for (auto &compare : sub_case->compare)
442 add_uses(node, compare);
443 add_case_defs_uses(node, sub_case);
444 }
445 }
446 }
447
448 void add_process_defs_uses(Node *node, const RTLIL::Process *process)
449 {
450 add_case_defs_uses(node, &process->root_case);
451 for (auto sync : process->syncs)
452 for (auto action : sync->actions) {
453 if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
454 add_defs(node, action.first, /*is_ff=*/true, /*inlinable=*/false);
455 else
456 add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
457 add_uses(node, action.second);
458 }
459 }
460
461 Node *add_node(const RTLIL::Process *process)
462 {
463 Node *node = new Node;
464 node->type = Node::Type::PROCESS;
465 node->process = process;
466 nodes.push_back(node);
467 add_process_defs_uses(node, process);
468 return node;
469 }
470 };
471
472 std::vector<std::string> split_by(const std::string &str, const std::string &sep)
473 {
474 std::vector<std::string> result;
475 size_t prev = 0;
476 while (true) {
477 size_t curr = str.find_first_of(sep, prev);
478 if (curr == std::string::npos) {
479 std::string part = str.substr(prev);
480 if (!part.empty()) result.push_back(part);
481 break;
482 } else {
483 std::string part = str.substr(prev, curr - prev);
484 if (!part.empty()) result.push_back(part);
485 prev = curr + 1;
486 }
487 }
488 return result;
489 }
490
491 std::string escape_cxx_string(const std::string &input)
492 {
493 std::string output = "\"";
494 for (auto c : input) {
495 if (::isprint(c)) {
496 if (c == '\\')
497 output.push_back('\\');
498 output.push_back(c);
499 } else {
500 char l = c & 0xf, h = (c >> 4) & 0xf;
501 output.append("\\x");
502 output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
503 output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
504 }
505 }
506 output.push_back('"');
507 if (output.find('\0') != std::string::npos) {
508 output.insert(0, "std::string {");
509 output.append(stringf(", %zu}", input.size()));
510 }
511 return output;
512 }
513
514 template<class T>
515 std::string get_hdl_name(T *object)
516 {
517 if (object->has_attribute(ID::hdlname))
518 return object->get_string_attribute(ID::hdlname);
519 else
520 return object->name.str().substr(1);
521 }
522
523 struct CxxrtlWorker {
524 bool split_intf = false;
525 std::string intf_filename;
526 std::string design_ns = "cxxrtl_design";
527 std::ostream *impl_f = nullptr;
528 std::ostream *intf_f = nullptr;
529
530 bool run_hierarchy = false;
531 bool run_flatten = false;
532 bool run_proc = false;
533
534 bool unbuffer_internal = false;
535 bool unbuffer_public = false;
536 bool localize_internal = false;
537 bool localize_public = false;
538 bool inline_internal = false;
539 bool inline_public = false;
540
541 bool debug_info = false;
542 bool debug_alias = false;
543 bool debug_eval = false;
544
545 std::ostringstream f;
546 std::string indent;
547 int temporary = 0;
548
549 dict<const RTLIL::Module*, SigMap> sigmaps;
550 pool<const RTLIL::Wire*> edge_wires;
551 dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
552 pool<const RTLIL::Memory*> writable_memories;
553 dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
554 dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
555 pool<const RTLIL::Wire*> unbuffered_wires;
556 pool<const RTLIL::Wire*> localized_wires;
557 dict<const RTLIL::Wire*, FlowGraph::Node> inlined_wires;
558 dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
559 dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
560 pool<const RTLIL::Wire*> debug_outlined_wires;
561 dict<RTLIL::SigBit, bool> bit_has_state;
562 dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
563 dict<const RTLIL::Module*, bool> eval_converges;
564
565 void inc_indent() {
566 indent += "\t";
567 }
568 void dec_indent() {
569 indent.resize(indent.size() - 1);
570 }
571
572 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
573 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
574 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
575 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
576 // 1. All generated identifiers start with `_`.
577 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
578 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
579 // 2. An underscore is escaped with another underscore, i.e. `__`.
580 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
581 std::string mangle_name(const RTLIL::IdString &name)
582 {
583 std::string mangled;
584 bool first = true;
585 for (char c : name.str()) {
586 if (first) {
587 first = false;
588 if (c == '\\')
589 mangled += "p_";
590 else if (c == '$')
591 mangled += "i_";
592 else
593 log_assert(false);
594 } else {
595 if (isalnum(c)) {
596 mangled += c;
597 } else if (c == '_') {
598 mangled += "__";
599 } else {
600 char l = c & 0xf, h = (c >> 4) & 0xf;
601 mangled += '_';
602 mangled += (h < 10 ? '0' + h : 'a' + h - 10);
603 mangled += (l < 10 ? '0' + l : 'a' + l - 10);
604 mangled += '_';
605 }
606 }
607 }
608 return mangled;
609 }
610
611 std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
612 {
613 // Class namespace.
614 if (is_blackbox)
615 return "bb_" + mangle_name(name);
616 return mangle_name(name);
617 }
618
619 std::string mangle_memory_name(const RTLIL::IdString &name)
620 {
621 // Class member namespace.
622 return "memory_" + mangle_name(name);
623 }
624
625 std::string mangle_cell_name(const RTLIL::IdString &name)
626 {
627 // Class member namespace.
628 return "cell_" + mangle_name(name);
629 }
630
631 std::string mangle_wire_name(const RTLIL::IdString &name)
632 {
633 // Class member namespace.
634 return mangle_name(name);
635 }
636
637 std::string mangle(const RTLIL::Module *module)
638 {
639 return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
640 }
641
642 std::string mangle(const RTLIL::Memory *memory)
643 {
644 return mangle_memory_name(memory->name);
645 }
646
647 std::string mangle(const RTLIL::Cell *cell)
648 {
649 return mangle_cell_name(cell->name);
650 }
651
652 std::string mangle(const RTLIL::Wire *wire)
653 {
654 return mangle_wire_name(wire->name);
655 }
656
657 std::string mangle(RTLIL::SigBit sigbit)
658 {
659 log_assert(sigbit.wire != NULL);
660 if (sigbit.wire->width == 1)
661 return mangle(sigbit.wire);
662 return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
663 }
664
665 std::vector<std::string> template_param_names(const RTLIL::Module *module)
666 {
667 if (!module->has_attribute(ID(cxxrtl_template)))
668 return {};
669
670 if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
671 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
672
673 std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
674 for (const auto &param_name : param_names) {
675 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
676 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
677 // in both Verilog and C++, anyway.)
678 if (!isupper(param_name[0]))
679 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
680 "which does not start with an uppercase letter.\n",
681 log_id(module), param_name.c_str());
682 }
683 return param_names;
684 }
685
686 std::string template_params(const RTLIL::Module *module, bool is_decl)
687 {
688 std::vector<std::string> param_names = template_param_names(module);
689 if (param_names.empty())
690 return "";
691
692 std::string params = "<";
693 bool first = true;
694 for (const auto &param_name : param_names) {
695 if (!first)
696 params += ", ";
697 first = false;
698 if (is_decl)
699 params += "size_t ";
700 params += param_name;
701 }
702 params += ">";
703 return params;
704 }
705
706 std::string template_args(const RTLIL::Cell *cell)
707 {
708 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
709 log_assert(cell_module != nullptr);
710 if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
711 return "";
712
713 std::vector<std::string> param_names = template_param_names(cell_module);
714 if (param_names.empty())
715 return "";
716
717 std::string params = "<";
718 bool first = true;
719 for (const auto &param_name : param_names) {
720 if (!first)
721 params += ", ";
722 first = false;
723 params += "/*" + param_name + "=*/";
724 RTLIL::IdString id_param_name = '\\' + param_name;
725 if (!cell->hasParam(id_param_name))
726 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
727 log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
728 RTLIL::Const param_value = cell->getParam(id_param_name);
729 if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
730 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
731 "is not a positive integer.\n",
732 param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
733 params += std::to_string(cell->getParam(id_param_name).as_int());
734 }
735 params += ">";
736 return params;
737 }
738
739 std::string fresh_temporary()
740 {
741 return stringf("tmp_%d", temporary++);
742 }
743
744 void dump_attrs(const RTLIL::AttrObject *object)
745 {
746 for (auto attr : object->attributes) {
747 f << indent << "// " << attr.first.str() << ": ";
748 if (attr.second.flags & RTLIL::CONST_FLAG_STRING) {
749 f << attr.second.decode_string();
750 } else {
751 f << attr.second.as_int(/*is_signed=*/attr.second.flags & RTLIL::CONST_FLAG_SIGNED);
752 }
753 f << "\n";
754 }
755 }
756
757 void dump_const_init(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
758 {
759 const int CHUNK_SIZE = 32;
760 f << "{";
761 while (width > 0) {
762 int chunk_width = min(width, CHUNK_SIZE);
763 uint32_t chunk = data.extract(offset, chunk_width).as_int();
764 if (fixed_width)
765 f << stringf("0x%.*xu", (3 + chunk_width) / 4, chunk);
766 else
767 f << stringf("%#xu", chunk);
768 if (width > CHUNK_SIZE)
769 f << ',';
770 offset += CHUNK_SIZE;
771 width -= CHUNK_SIZE;
772 }
773 f << "}";
774 }
775
776 void dump_const_init(const RTLIL::Const &data)
777 {
778 dump_const_init(data, data.size());
779 }
780
781 void dump_const(const RTLIL::Const &data, int width, int offset = 0, bool fixed_width = false)
782 {
783 f << "value<" << width << ">";
784 dump_const_init(data, width, offset, fixed_width);
785 }
786
787 void dump_const(const RTLIL::Const &data)
788 {
789 dump_const(data, data.size());
790 }
791
792 bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs, bool for_debug = false)
793 {
794 if (chunk.wire == NULL) {
795 dump_const(chunk.data, chunk.width, chunk.offset);
796 return false;
797 } else {
798 if (inlined_wires.count(chunk.wire) && (!for_debug || !debug_outlined_wires[chunk.wire])) {
799 log_assert(!is_lhs);
800 const FlowGraph::Node &node = inlined_wires[chunk.wire];
801 switch (node.type) {
802 case FlowGraph::Node::Type::CONNECT:
803 dump_connect_expr(node.connect, for_debug);
804 break;
805 case FlowGraph::Node::Type::CELL_EVAL:
806 log_assert(is_inlinable_cell(node.cell->type));
807 dump_cell_expr(node.cell, for_debug);
808 break;
809 default:
810 log_assert(false);
811 }
812 } else if (unbuffered_wires[chunk.wire]) {
813 f << mangle(chunk.wire);
814 } else {
815 f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
816 }
817 if (chunk.width == chunk.wire->width && chunk.offset == 0)
818 return false;
819 else if (chunk.width == 1)
820 f << ".slice<" << chunk.offset << ">()";
821 else
822 f << ".slice<" << chunk.offset+chunk.width-1 << "," << chunk.offset << ">()";
823 return true;
824 }
825 }
826
827 bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs, bool for_debug = false)
828 {
829 if (sig.empty()) {
830 f << "value<0>()";
831 return false;
832 } else if (sig.is_chunk()) {
833 return dump_sigchunk(sig.as_chunk(), is_lhs, for_debug);
834 } else {
835 dump_sigchunk(*sig.chunks().rbegin(), is_lhs, for_debug);
836 for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
837 f << ".concat(";
838 dump_sigchunk(*it, is_lhs, for_debug);
839 f << ")";
840 }
841 return true;
842 }
843 }
844
845 void dump_sigspec_lhs(const RTLIL::SigSpec &sig, bool for_debug = false)
846 {
847 dump_sigspec(sig, /*is_lhs=*/true, for_debug);
848 }
849
850 void dump_sigspec_rhs(const RTLIL::SigSpec &sig, bool for_debug = false)
851 {
852 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
853 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
854 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
855 // type conversion, but only if the expression needs it.
856 bool is_complex = dump_sigspec(sig, /*is_lhs=*/false, for_debug);
857 if (is_complex)
858 f << ".val()";
859 }
860
861 void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
862 {
863 for (auto chunk : sig.chunks()) {
864 if (!chunk.wire || !inlined_wires.count(chunk.wire))
865 continue;
866
867 const FlowGraph::Node &node = inlined_wires[chunk.wire];
868 switch (node.type) {
869 case FlowGraph::Node::Type::CONNECT:
870 collect_connect(node.connect, cells);
871 break;
872 case FlowGraph::Node::Type::CELL_EVAL:
873 collect_cell_eval(node.cell, cells);
874 break;
875 default:
876 log_assert(false);
877 }
878 }
879 }
880
881 void dump_connect_expr(const RTLIL::SigSig &conn, bool for_debug = false)
882 {
883 dump_sigspec_rhs(conn.second, for_debug);
884 }
885
886 bool is_connect_inlined(const RTLIL::SigSig &conn)
887 {
888 return conn.first.is_wire() && inlined_wires.count(conn.first.as_wire());
889 }
890
891 bool is_connect_outlined(const RTLIL::SigSig &conn)
892 {
893 for (auto chunk : conn.first.chunks())
894 if (debug_outlined_wires.count(chunk.wire))
895 return true;
896 return false;
897 }
898
899 void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
900 {
901 if (!is_connect_inlined(conn))
902 return;
903
904 collect_sigspec_rhs(conn.second, cells);
905 }
906
907 void dump_connect(const RTLIL::SigSig &conn, bool for_debug = false)
908 {
909 if (!for_debug && is_connect_inlined(conn))
910 return;
911 if (for_debug && !is_connect_outlined(conn))
912 return;
913
914 std::vector<RTLIL::IdString> inlined_cells;
915 collect_sigspec_rhs(conn.second, inlined_cells);
916 if (for_debug || inlined_cells.empty()) {
917 f << indent << "// connection\n";
918 } else {
919 f << indent << "// cells";
920 for (auto inlined_cell : inlined_cells)
921 f << " " << inlined_cell.str();
922 f << "\n";
923 }
924 f << indent;
925 dump_sigspec_lhs(conn.first, for_debug);
926 f << " = ";
927 dump_connect_expr(conn, for_debug);
928 f << ";\n";
929 }
930
931 void dump_cell_sync(const RTLIL::Cell *cell)
932 {
933 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
934 f << indent << "// cell " << cell->name.str() << " syncs\n";
935 for (auto conn : cell->connections())
936 if (cell->output(conn.first))
937 if (is_cxxrtl_sync_port(cell, conn.first)) {
938 f << indent;
939 dump_sigspec_lhs(conn.second);
940 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
941 }
942 }
943
944 void dump_cell_expr(const RTLIL::Cell *cell, bool for_debug = false)
945 {
946 // Unary cells
947 if (is_unary_cell(cell->type)) {
948 f << cell->type.substr(1);
949 if (is_extending_cell(cell->type))
950 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
951 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
952 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
953 f << ")";
954 // Binary cells
955 } else if (is_binary_cell(cell->type)) {
956 f << cell->type.substr(1);
957 if (is_extending_cell(cell->type))
958 f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
959 (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
960 f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
961 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
962 f << ", ";
963 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
964 f << ")";
965 // Muxes
966 } else if (cell->type == ID($mux)) {
967 f << "(";
968 dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
969 f << " ? ";
970 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
971 f << " : ";
972 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
973 f << ")";
974 // Parallel (one-hot) muxes
975 } else if (cell->type == ID($pmux)) {
976 int width = cell->getParam(ID::WIDTH).as_int();
977 int s_width = cell->getParam(ID::S_WIDTH).as_int();
978 for (int part = 0; part < s_width; part++) {
979 f << "(";
980 dump_sigspec_rhs(cell->getPort(ID::S).extract(part), for_debug);
981 f << " ? ";
982 dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width), for_debug);
983 f << " : ";
984 }
985 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
986 for (int part = 0; part < s_width; part++) {
987 f << ")";
988 }
989 // Concats
990 } else if (cell->type == ID($concat)) {
991 dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
992 f << ".concat(";
993 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
994 f << ").val()";
995 // Slices
996 } else if (cell->type == ID($slice)) {
997 dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
998 f << ".slice<";
999 f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
1000 f << ",";
1001 f << cell->getParam(ID::OFFSET).as_int();
1002 f << ">().val()";
1003 } else {
1004 log_assert(false);
1005 }
1006 }
1007
1008 bool is_cell_inlined(const RTLIL::Cell *cell)
1009 {
1010 return is_inlinable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
1011 inlined_wires.count(cell->getPort(ID::Y).as_wire());
1012 }
1013
1014 bool is_cell_outlined(const RTLIL::Cell *cell)
1015 {
1016 if (is_internal_cell(cell->type))
1017 for (auto conn : cell->connections())
1018 if (cell->output(conn.first))
1019 for (auto chunk : conn.second.chunks())
1020 if (debug_outlined_wires.count(chunk.wire))
1021 return true;
1022 return false;
1023 }
1024
1025 void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
1026 {
1027 if (!is_cell_inlined(cell))
1028 return;
1029
1030 cells.push_back(cell->name);
1031 for (auto port : cell->connections())
1032 if (port.first != ID::Y)
1033 collect_sigspec_rhs(port.second, cells);
1034 }
1035
1036 void dump_cell_eval(const RTLIL::Cell *cell, bool for_debug = false)
1037 {
1038 if (!for_debug && is_cell_inlined(cell))
1039 return;
1040 if (for_debug && !is_cell_outlined(cell))
1041 return;
1042 if (cell->type == ID($meminit))
1043 return; // Handled elsewhere.
1044
1045 std::vector<RTLIL::IdString> inlined_cells;
1046 if (is_inlinable_cell(cell->type)) {
1047 for (auto port : cell->connections())
1048 if (port.first != ID::Y)
1049 collect_sigspec_rhs(port.second, inlined_cells);
1050 }
1051 if (inlined_cells.empty()) {
1052 dump_attrs(cell);
1053 f << indent << "// cell " << cell->name.str() << "\n";
1054 } else {
1055 f << indent << "// cells";
1056 for (auto inlined_cell : inlined_cells)
1057 f << " " << inlined_cell.str();
1058 f << "\n";
1059 }
1060
1061 // Elidable cells
1062 if (is_inlinable_cell(cell->type)) {
1063 f << indent;
1064 dump_sigspec_lhs(cell->getPort(ID::Y), for_debug);
1065 f << " = ";
1066 dump_cell_expr(cell, for_debug);
1067 f << ";\n";
1068 // Flip-flops
1069 } else if (is_ff_cell(cell->type)) {
1070 if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
1071 // Edge-sensitive logic
1072 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1073 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1074 if (clk_bit.wire) {
1075 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1076 << mangle(clk_bit) << ") {\n";
1077 } else {
1078 f << indent << "if (false) {\n";
1079 }
1080 inc_indent();
1081 if (cell->hasPort(ID::EN)) {
1082 f << indent << "if (";
1083 dump_sigspec_rhs(cell->getPort(ID::EN));
1084 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1085 inc_indent();
1086 }
1087 f << indent;
1088 dump_sigspec_lhs(cell->getPort(ID::Q));
1089 f << " = ";
1090 dump_sigspec_rhs(cell->getPort(ID::D));
1091 f << ";\n";
1092 if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
1093 dec_indent();
1094 f << indent << "}\n";
1095 }
1096 if (cell->hasPort(ID::SRST)) {
1097 f << indent << "if (";
1098 dump_sigspec_rhs(cell->getPort(ID::SRST));
1099 f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
1100 inc_indent();
1101 f << indent;
1102 dump_sigspec_lhs(cell->getPort(ID::Q));
1103 f << " = ";
1104 dump_const(cell->getParam(ID::SRST_VALUE));
1105 f << ";\n";
1106 dec_indent();
1107 f << indent << "}\n";
1108 }
1109 if (cell->hasPort(ID::EN) && cell->type == ID($sdffce)) {
1110 dec_indent();
1111 f << indent << "}\n";
1112 }
1113 dec_indent();
1114 f << indent << "}\n";
1115 } else if (cell->hasPort(ID::EN)) {
1116 // Level-sensitive logic
1117 f << indent << "if (";
1118 dump_sigspec_rhs(cell->getPort(ID::EN));
1119 f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
1120 inc_indent();
1121 f << indent;
1122 dump_sigspec_lhs(cell->getPort(ID::Q));
1123 f << " = ";
1124 dump_sigspec_rhs(cell->getPort(ID::D));
1125 f << ";\n";
1126 dec_indent();
1127 f << indent << "}\n";
1128 }
1129 if (cell->hasPort(ID::ARST)) {
1130 // Asynchronous reset (entire coarse cell at once)
1131 f << indent << "if (";
1132 dump_sigspec_rhs(cell->getPort(ID::ARST));
1133 f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
1134 inc_indent();
1135 f << indent;
1136 dump_sigspec_lhs(cell->getPort(ID::Q));
1137 f << " = ";
1138 dump_const(cell->getParam(ID::ARST_VALUE));
1139 f << ";\n";
1140 dec_indent();
1141 f << indent << "}\n";
1142 }
1143 if (cell->hasPort(ID::SET)) {
1144 // Asynchronous set (for individual bits)
1145 f << indent;
1146 dump_sigspec_lhs(cell->getPort(ID::Q));
1147 f << " = ";
1148 dump_sigspec_lhs(cell->getPort(ID::Q));
1149 f << ".update(";
1150 dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
1151 f << ", ";
1152 dump_sigspec_rhs(cell->getPort(ID::SET));
1153 f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1154 }
1155 if (cell->hasPort(ID::CLR)) {
1156 // Asynchronous clear (for individual bits; priority over set)
1157 f << indent;
1158 dump_sigspec_lhs(cell->getPort(ID::Q));
1159 f << " = ";
1160 dump_sigspec_lhs(cell->getPort(ID::Q));
1161 f << ".update(";
1162 dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
1163 f << ", ";
1164 dump_sigspec_rhs(cell->getPort(ID::CLR));
1165 f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
1166 }
1167 // Memory ports
1168 } else if (cell->type.in(ID($memrd), ID($memwr))) {
1169 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1170 RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
1171 clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
1172 if (clk_bit.wire) {
1173 f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
1174 << mangle(clk_bit) << ") {\n";
1175 } else {
1176 f << indent << "if (false) {\n";
1177 }
1178 inc_indent();
1179 }
1180 RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
1181 std::string valid_index_temp = fresh_temporary();
1182 f << indent << "auto " << valid_index_temp << " = memory_index(";
1183 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1184 f << ", " << memory->start_offset << ", " << memory->size << ");\n";
1185 if (cell->type == ID($memrd)) {
1186 bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
1187 if (has_enable) {
1188 f << indent << "if (";
1189 dump_sigspec_rhs(cell->getPort(ID::EN));
1190 f << ") {\n";
1191 inc_indent();
1192 }
1193 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1194 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1195 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DCXXRTL_NDEBUG
1196 // not only for release builds, but also to make sure the simulator (which is presumably embedded in some
1197 // larger program) will never crash the code that calls into it.
1198 //
1199 // If assertions are disabled, out of bounds reads are defined to return zero.
1200 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
1201 f << indent << "if(" << valid_index_temp << ".valid) {\n";
1202 inc_indent();
1203 if (writable_memories[memory]) {
1204 std::string lhs_temp = fresh_temporary();
1205 f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
1206 << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1207 std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
1208 if (!memwr_cells.empty()) {
1209 std::string addr_temp = fresh_temporary();
1210 f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
1211 dump_sigspec_rhs(cell->getPort(ID::ADDR));
1212 f << ";\n";
1213 std::sort(memwr_cells.begin(), memwr_cells.end(),
1214 [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1215 return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
1216 });
1217 for (auto memwr_cell : memwr_cells) {
1218 f << indent << "if (" << addr_temp << " == ";
1219 dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
1220 f << ") {\n";
1221 inc_indent();
1222 f << indent << lhs_temp << " = " << lhs_temp;
1223 f << ".update(";
1224 dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
1225 f << ", ";
1226 dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
1227 f << ");\n";
1228 dec_indent();
1229 f << indent << "}\n";
1230 }
1231 }
1232 f << indent;
1233 dump_sigspec_lhs(cell->getPort(ID::DATA));
1234 f << " = " << lhs_temp << ";\n";
1235 } else {
1236 f << indent;
1237 dump_sigspec_lhs(cell->getPort(ID::DATA));
1238 f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
1239 }
1240 dec_indent();
1241 f << indent << "} else {\n";
1242 inc_indent();
1243 f << indent;
1244 dump_sigspec_lhs(cell->getPort(ID::DATA));
1245 f << " = value<" << memory->width << "> {};\n";
1246 dec_indent();
1247 f << indent << "}\n";
1248 if (has_enable) {
1249 dec_indent();
1250 f << indent << "}\n";
1251 }
1252 } else /*if (cell->type == ID($memwr))*/ {
1253 log_assert(writable_memories[memory]);
1254 // See above for rationale of having both the assert and the condition.
1255 //
1256 // If assertions are disabled, out of bounds writes are defined to do nothing.
1257 f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
1258 f << indent << "if (" << valid_index_temp << ".valid) {\n";
1259 inc_indent();
1260 f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
1261 dump_sigspec_rhs(cell->getPort(ID::DATA));
1262 f << ", ";
1263 dump_sigspec_rhs(cell->getPort(ID::EN));
1264 f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
1265 dec_indent();
1266 f << indent << "}\n";
1267 }
1268 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
1269 dec_indent();
1270 f << indent << "}\n";
1271 }
1272 // Internal cells
1273 } else if (is_internal_cell(cell->type)) {
1274 log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
1275 // User cells
1276 } else {
1277 log_assert(cell->known());
1278 bool buffered_inputs = false;
1279 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1280 for (auto conn : cell->connections())
1281 if (cell->input(conn.first)) {
1282 RTLIL::Module *cell_module = cell->module->design->module(cell->type);
1283 log_assert(cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire());
1284 RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
1285 f << indent << mangle(cell) << access << mangle_wire_name(conn.first);
1286 if (!is_cxxrtl_blackbox_cell(cell) && !unbuffered_wires[cell_module_wire]) {
1287 buffered_inputs = true;
1288 f << ".next";
1289 }
1290 f << " = ";
1291 dump_sigspec_rhs(conn.second);
1292 f << ";\n";
1293 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1294 // Until we have proper clock tree detection, this really awful hack that opportunistically
1295 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1296 // be if only one clock edge was simulated by replacing:
1297 // top.p_clk = value<1>{0u}; top.step();
1298 // top.p_clk = value<1>{1u}; top.step();
1299 // with:
1300 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1301 // Don't rely on this; it will be removed without warning.
1302 if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
1303 f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
1304 f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
1305 }
1306 }
1307 }
1308 auto assign_from_outputs = [&](bool cell_converged) {
1309 for (auto conn : cell->connections()) {
1310 if (cell->output(conn.first)) {
1311 if (conn.second.empty())
1312 continue; // ignore disconnected ports
1313 if (is_cxxrtl_sync_port(cell, conn.first))
1314 continue; // fully sync ports are handled in CELL_SYNC nodes
1315 f << indent;
1316 dump_sigspec_lhs(conn.second);
1317 f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
1318 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1319 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1320 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1321 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1322 // and consider the fate of the localized wires that used to be output ports.)
1323 //
1324 // It is not possible to know apriori whether the cell (which may be late bound) will converge immediately.
1325 // Because of this, the choice between using .curr (appropriate for buffered outputs) and .next (appropriate
1326 // for unbuffered outputs) is made at runtime.
1327 if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
1328 f << ".next;\n";
1329 else
1330 f << ".curr;\n";
1331 }
1332 }
1333 };
1334 if (buffered_inputs) {
1335 // If we have any buffered inputs, there's no chance of converging immediately.
1336 f << indent << mangle(cell) << access << "eval();\n";
1337 f << indent << "converged = false;\n";
1338 assign_from_outputs(/*cell_converged=*/false);
1339 } else {
1340 f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
1341 inc_indent();
1342 assign_from_outputs(/*cell_converged=*/true);
1343 dec_indent();
1344 f << indent << "} else {\n";
1345 inc_indent();
1346 f << indent << "converged = false;\n";
1347 assign_from_outputs(/*cell_converged=*/false);
1348 dec_indent();
1349 f << indent << "}\n";
1350 }
1351 }
1352 }
1353
1354 void dump_assign(const RTLIL::SigSig &sigsig)
1355 {
1356 f << indent;
1357 dump_sigspec_lhs(sigsig.first);
1358 f << " = ";
1359 dump_sigspec_rhs(sigsig.second);
1360 f << ";\n";
1361 }
1362
1363 void dump_case_rule(const RTLIL::CaseRule *rule)
1364 {
1365 for (auto action : rule->actions)
1366 dump_assign(action);
1367 for (auto switch_ : rule->switches)
1368 dump_switch_rule(switch_);
1369 }
1370
1371 void dump_switch_rule(const RTLIL::SwitchRule *rule)
1372 {
1373 // The switch attributes are printed before the switch condition is captured.
1374 dump_attrs(rule);
1375 std::string signal_temp = fresh_temporary();
1376 f << indent << "const value<" << rule->signal.size() << "> &" << signal_temp << " = ";
1377 dump_sigspec(rule->signal, /*is_lhs=*/false);
1378 f << ";\n";
1379
1380 bool first = true;
1381 for (auto case_ : rule->cases) {
1382 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1383 dump_attrs(rule);
1384 f << indent;
1385 if (!first)
1386 f << "} else ";
1387 first = false;
1388 if (!case_->compare.empty()) {
1389 f << "if (";
1390 bool first = true;
1391 for (auto &compare : case_->compare) {
1392 if (!first)
1393 f << " || ";
1394 first = false;
1395 if (compare.is_fully_def()) {
1396 f << signal_temp << " == ";
1397 dump_sigspec(compare, /*is_lhs=*/false);
1398 } else if (compare.is_fully_const()) {
1399 RTLIL::Const compare_mask, compare_value;
1400 for (auto bit : compare.as_const()) {
1401 switch (bit) {
1402 case RTLIL::S0:
1403 case RTLIL::S1:
1404 compare_mask.bits.push_back(RTLIL::S1);
1405 compare_value.bits.push_back(bit);
1406 break;
1407
1408 case RTLIL::Sx:
1409 case RTLIL::Sz:
1410 case RTLIL::Sa:
1411 compare_mask.bits.push_back(RTLIL::S0);
1412 compare_value.bits.push_back(RTLIL::S0);
1413 break;
1414
1415 default:
1416 log_assert(false);
1417 }
1418 }
1419 f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
1420 dump_const(compare_mask);
1421 f << ") == ";
1422 dump_const(compare_value);
1423 } else {
1424 log_assert(false);
1425 }
1426 }
1427 f << ") ";
1428 }
1429 f << "{\n";
1430 inc_indent();
1431 dump_case_rule(case_);
1432 dec_indent();
1433 }
1434 f << indent << "}\n";
1435 }
1436
1437 void dump_process(const RTLIL::Process *proc)
1438 {
1439 dump_attrs(proc);
1440 f << indent << "// process " << proc->name.str() << "\n";
1441 // The case attributes (for root case) are always empty.
1442 log_assert(proc->root_case.attributes.empty());
1443 dump_case_rule(&proc->root_case);
1444 for (auto sync : proc->syncs) {
1445 RTLIL::SigBit sync_bit;
1446 if (!sync->signal.empty()) {
1447 sync_bit = sync->signal[0];
1448 sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
1449 }
1450
1451 pool<std::string> events;
1452 switch (sync->type) {
1453 case RTLIL::STp:
1454 log_assert(sync_bit.wire != nullptr);
1455 events.insert("posedge_" + mangle(sync_bit));
1456 break;
1457 case RTLIL::STn:
1458 log_assert(sync_bit.wire != nullptr);
1459 events.insert("negedge_" + mangle(sync_bit));
1460 break;
1461 case RTLIL::STe:
1462 log_assert(sync_bit.wire != nullptr);
1463 events.insert("posedge_" + mangle(sync_bit));
1464 events.insert("negedge_" + mangle(sync_bit));
1465 break;
1466
1467 case RTLIL::STa:
1468 events.insert("true");
1469 break;
1470
1471 case RTLIL::ST0:
1472 case RTLIL::ST1:
1473 case RTLIL::STg:
1474 case RTLIL::STi:
1475 log_assert(false);
1476 }
1477 if (!events.empty()) {
1478 f << indent << "if (";
1479 bool first = true;
1480 for (auto &event : events) {
1481 if (!first)
1482 f << " || ";
1483 first = false;
1484 f << event;
1485 }
1486 f << ") {\n";
1487 inc_indent();
1488 for (auto action : sync->actions)
1489 dump_assign(action);
1490 dec_indent();
1491 f << indent << "}\n";
1492 }
1493 }
1494 }
1495
1496 void dump_wire(const RTLIL::Wire *wire, bool is_local)
1497 {
1498 if (is_local && localized_wires[wire] && !inlined_wires.count(wire)) {
1499 dump_attrs(wire);
1500 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1501 }
1502 if (!is_local && !localized_wires[wire]) {
1503 std::string width;
1504 if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
1505 width = wire->get_string_attribute(ID(cxxrtl_width));
1506 } else {
1507 width = std::to_string(wire->width);
1508 }
1509
1510 dump_attrs(wire);
1511 f << indent;
1512 if (wire->port_input && wire->port_output)
1513 f << "/*inout*/ ";
1514 else if (wire->port_input)
1515 f << "/*input*/ ";
1516 else if (wire->port_output)
1517 f << "/*output*/ ";
1518 f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
1519 if (wire->has_attribute(ID::init)) {
1520 f << " ";
1521 dump_const_init(wire->attributes.at(ID::init));
1522 }
1523 f << ";\n";
1524 if (edge_wires[wire]) {
1525 if (unbuffered_wires[wire]) {
1526 f << indent << "value<" << width << "> prev_" << mangle(wire);
1527 if (wire->has_attribute(ID::init)) {
1528 f << " ";
1529 dump_const_init(wire->attributes.at(ID::init));
1530 }
1531 f << ";\n";
1532 }
1533 for (auto edge_type : edge_types) {
1534 if (edge_type.first.wire == wire) {
1535 std::string prev, next;
1536 if (unbuffered_wires[wire]) {
1537 prev = "prev_" + mangle(edge_type.first.wire);
1538 next = mangle(edge_type.first.wire);
1539 } else {
1540 prev = mangle(edge_type.first.wire) + ".curr";
1541 next = mangle(edge_type.first.wire) + ".next";
1542 }
1543 prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1544 next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
1545 if (edge_type.second != RTLIL::STn) {
1546 f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
1547 inc_indent();
1548 f << indent << "return !" << prev << " && " << next << ";\n";
1549 dec_indent();
1550 f << indent << "}\n";
1551 }
1552 if (edge_type.second != RTLIL::STp) {
1553 f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
1554 inc_indent();
1555 f << indent << "return " << prev << " && !" << next << ";\n";
1556 dec_indent();
1557 f << indent << "}\n";
1558 }
1559 }
1560 }
1561 }
1562 }
1563 }
1564
1565 void dump_debug_wire(const RTLIL::Wire *wire, bool is_local)
1566 {
1567 if (!debug_outlined_wires[wire])
1568 return;
1569
1570 bool is_outlined_member = wire->name.isPublic() &&
1571 !(debug_const_wires.count(wire) || debug_alias_wires.count(wire));
1572 if (is_local && !is_outlined_member) {
1573 dump_attrs(wire);
1574 f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
1575 }
1576 if (!is_local && is_outlined_member) {
1577 dump_attrs(wire);
1578 f << indent << "/*outline*/ value<" << wire->width << "> " << mangle(wire) << ";\n";
1579 }
1580 }
1581
1582 void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
1583 {
1584 vector<const RTLIL::Cell*> init_cells;
1585 for (auto cell : module->cells())
1586 if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
1587 init_cells.push_back(cell);
1588
1589 std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
1590 int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
1591 int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
1592 return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
1593 });
1594
1595 dump_attrs(memory);
1596 f << indent << "memory<" << memory->width << "> " << mangle(memory)
1597 << " { " << memory->size << "u";
1598 if (init_cells.empty()) {
1599 f << " };\n";
1600 } else {
1601 f << ",\n";
1602 inc_indent();
1603 for (auto cell : init_cells) {
1604 dump_attrs(cell);
1605 RTLIL::Const data = cell->getPort(ID::DATA).as_const();
1606 size_t width = cell->getParam(ID::WIDTH).as_int();
1607 size_t words = cell->getParam(ID::WORDS).as_int();
1608 f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
1609 << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
1610 inc_indent();
1611 for (size_t n = 0; n < words; n++) {
1612 if (n % 4 == 0)
1613 f << "\n" << indent;
1614 else
1615 f << " ";
1616 dump_const(data, width, n * width, /*fixed_width=*/true);
1617 f << ",";
1618 }
1619 dec_indent();
1620 f << "\n" << indent << "}},\n";
1621 }
1622 dec_indent();
1623 f << indent << "};\n";
1624 }
1625 }
1626
1627 void dump_eval_method(RTLIL::Module *module)
1628 {
1629 inc_indent();
1630 f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
1631 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1632 for (auto wire : module->wires()) {
1633 if (edge_wires[wire]) {
1634 for (auto edge_type : edge_types) {
1635 if (edge_type.first.wire == wire) {
1636 if (edge_type.second != RTLIL::STn) {
1637 f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
1638 f << "this->posedge_" << mangle(edge_type.first) << "();\n";
1639 }
1640 if (edge_type.second != RTLIL::STp) {
1641 f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
1642 f << "this->negedge_" << mangle(edge_type.first) << "();\n";
1643 }
1644 }
1645 }
1646 }
1647 }
1648 for (auto wire : module->wires())
1649 dump_wire(wire, /*is_local=*/true);
1650 for (auto node : schedule[module]) {
1651 switch (node.type) {
1652 case FlowGraph::Node::Type::CONNECT:
1653 dump_connect(node.connect);
1654 break;
1655 case FlowGraph::Node::Type::CELL_SYNC:
1656 dump_cell_sync(node.cell);
1657 break;
1658 case FlowGraph::Node::Type::CELL_EVAL:
1659 dump_cell_eval(node.cell);
1660 break;
1661 case FlowGraph::Node::Type::PROCESS:
1662 dump_process(node.process);
1663 break;
1664 }
1665 }
1666 }
1667 f << indent << "return converged;\n";
1668 dec_indent();
1669 }
1670
1671 void dump_debug_eval_method(RTLIL::Module *module)
1672 {
1673 inc_indent();
1674 for (auto wire : module->wires())
1675 dump_debug_wire(wire, /*is_local=*/true);
1676 for (auto node : schedule[module]) {
1677 switch (node.type) {
1678 case FlowGraph::Node::Type::CONNECT:
1679 dump_connect(node.connect, /*for_debug=*/true);
1680 break;
1681 case FlowGraph::Node::Type::CELL_EVAL:
1682 dump_cell_eval(node.cell, /*for_debug=*/true);
1683 break;
1684 case FlowGraph::Node::Type::CELL_SYNC:
1685 case FlowGraph::Node::Type::PROCESS:
1686 break;
1687 }
1688 }
1689 dec_indent();
1690 }
1691
1692 void dump_commit_method(RTLIL::Module *module)
1693 {
1694 inc_indent();
1695 f << indent << "bool changed = false;\n";
1696 for (auto wire : module->wires()) {
1697 if (inlined_wires.count(wire))
1698 continue;
1699 if (unbuffered_wires[wire]) {
1700 if (edge_wires[wire])
1701 f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
1702 continue;
1703 }
1704 if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0)
1705 f << indent << "changed |= " << mangle(wire) << ".commit();\n";
1706 }
1707 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1708 for (auto memory : module->memories) {
1709 if (!writable_memories[memory.second])
1710 continue;
1711 f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
1712 }
1713 for (auto cell : module->cells()) {
1714 if (is_internal_cell(cell->type))
1715 continue;
1716 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1717 f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
1718 }
1719 }
1720 f << indent << "return changed;\n";
1721 dec_indent();
1722 }
1723
1724 void dump_debug_info_method(RTLIL::Module *module)
1725 {
1726 size_t count_public_wires = 0;
1727 size_t count_const_wires = 0;
1728 size_t count_alias_wires = 0;
1729 size_t count_inline_wires = 0;
1730 size_t count_member_wires = 0;
1731 size_t count_skipped_wires = 0;
1732 size_t count_driven_sync = 0;
1733 size_t count_driven_comb = 0;
1734 size_t count_undriven = 0;
1735 size_t count_mixed_driver = 0;
1736 inc_indent();
1737 f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1738 for (auto wire : module->wires()) {
1739 if (!wire->name.isPublic())
1740 continue;
1741 if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
1742 continue;
1743 count_public_wires++;
1744 if (debug_const_wires.count(wire)) {
1745 // Wire tied to a constant
1746 f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
1747 dump_const(debug_const_wires[wire]);
1748 f << ";\n";
1749 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1750 f << ", debug_item(const_" << mangle(wire) << ", ";
1751 f << wire->start_offset << "));\n";
1752 count_const_wires++;
1753 } else if (debug_alias_wires.count(wire)) {
1754 // Alias of a member wire
1755 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1756 f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
1757 f << wire->start_offset << "));\n";
1758 count_alias_wires++;
1759 } else if (debug_outlined_wires.count(wire)) {
1760 // Inlined but rematerializable wire
1761 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1762 f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", ";
1763 f << wire->start_offset << "));\n";
1764 count_inline_wires++;
1765 } else if (!localized_wires.count(wire)) {
1766 // Member wire
1767 std::vector<std::string> flags;
1768
1769 if (wire->port_input && wire->port_output)
1770 flags.push_back("INOUT");
1771 else if (wire->port_input)
1772 flags.push_back("INPUT");
1773 else if (wire->port_output)
1774 flags.push_back("OUTPUT");
1775
1776 bool has_driven_sync = false;
1777 bool has_driven_comb = false;
1778 bool has_undriven = false;
1779 SigSpec sig(wire);
1780 for (auto bit : sig.bits())
1781 if (!bit_has_state.count(bit))
1782 has_undriven = true;
1783 else if (bit_has_state[bit])
1784 has_driven_sync = true;
1785 else
1786 has_driven_comb = true;
1787 if (has_driven_sync)
1788 flags.push_back("DRIVEN_SYNC");
1789 if (has_driven_sync && !has_driven_comb && !has_undriven)
1790 count_driven_sync++;
1791 if (has_driven_comb)
1792 flags.push_back("DRIVEN_COMB");
1793 if (!has_driven_sync && has_driven_comb && !has_undriven)
1794 count_driven_comb++;
1795 if (has_undriven)
1796 flags.push_back("UNDRIVEN");
1797 if (!has_driven_sync && !has_driven_comb && has_undriven)
1798 count_undriven++;
1799 if (has_driven_sync + has_driven_comb + has_undriven > 1)
1800 count_mixed_driver++;
1801
1802 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
1803 f << ", debug_item(" << mangle(wire) << ", ";
1804 f << wire->start_offset;
1805 bool first = true;
1806 for (auto flag : flags) {
1807 if (first) {
1808 first = false;
1809 f << ", ";
1810 } else {
1811 f << "|";
1812 }
1813 f << "debug_item::" << flag;
1814 }
1815 f << "));\n";
1816 count_member_wires++;
1817 } else {
1818 // Localized or inlined wire with no debug information
1819 count_skipped_wires++;
1820 }
1821 }
1822 if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1823 for (auto &memory_it : module->memories) {
1824 if (!memory_it.first.isPublic())
1825 continue;
1826 f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
1827 f << ", debug_item(" << mangle(memory_it.second) << ", ";
1828 f << memory_it.second->start_offset << "));\n";
1829 }
1830 for (auto cell : module->cells()) {
1831 if (is_internal_cell(cell->type))
1832 continue;
1833 const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
1834 f << indent << mangle(cell) << access << "debug_info(items, ";
1835 f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
1836 }
1837 }
1838 dec_indent();
1839
1840 log_debug("Debug information statistics for module `%s':\n", log_id(module));
1841 log_debug(" Public wires: %zu, of which:\n", count_public_wires);
1842 log_debug(" Member wires: %zu, of which:\n", count_member_wires);
1843 log_debug(" Driven sync: %zu\n", count_driven_sync);
1844 log_debug(" Driven comb: %zu\n", count_driven_comb);
1845 log_debug(" Mixed driver: %zu\n", count_mixed_driver);
1846 log_debug(" Undriven: %zu\n", count_undriven);
1847 log_debug(" Inline wires: %zu\n", count_inline_wires);
1848 log_debug(" Alias wires: %zu\n", count_alias_wires);
1849 log_debug(" Const wires: %zu\n", count_const_wires);
1850 log_debug(" Other wires: %zu%s\n", count_skipped_wires,
1851 count_skipped_wires > 0 ? " (debug information unavailable)" : "");
1852 }
1853
1854 void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
1855 {
1856 if (metadata_map.empty()) {
1857 f << "metadata_map()";
1858 return;
1859 }
1860 f << "metadata_map({\n";
1861 inc_indent();
1862 for (auto metadata_item : metadata_map) {
1863 if (!metadata_item.first.begins_with("\\"))
1864 continue;
1865 f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
1866 if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
1867 f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
1868 } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
1869 f << escape_cxx_string(metadata_item.second.decode_string());
1870 } else {
1871 f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
1872 if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
1873 f << "u";
1874 }
1875 f << " },\n";
1876 }
1877 dec_indent();
1878 f << indent << "})";
1879 }
1880
1881 void dump_module_intf(RTLIL::Module *module)
1882 {
1883 dump_attrs(module);
1884 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1885 if (module->has_attribute(ID(cxxrtl_template)))
1886 f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
1887 f << indent << "struct " << mangle(module) << " : public module {\n";
1888 inc_indent();
1889 for (auto wire : module->wires()) {
1890 if (wire->port_id != 0)
1891 dump_wire(wire, /*is_local=*/false);
1892 }
1893 f << "\n";
1894 f << indent << "bool eval() override {\n";
1895 dump_eval_method(module);
1896 f << indent << "}\n";
1897 f << "\n";
1898 f << indent << "bool commit() override {\n";
1899 dump_commit_method(module);
1900 f << indent << "}\n";
1901 f << "\n";
1902 if (debug_info) {
1903 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1904 dump_debug_info_method(module);
1905 f << indent << "}\n";
1906 f << "\n";
1907 }
1908 f << indent << "static std::unique_ptr<" << mangle(module);
1909 f << template_params(module, /*is_decl=*/false) << "> ";
1910 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1911 dec_indent();
1912 f << indent << "}; // struct " << mangle(module) << "\n";
1913 f << "\n";
1914 if (blackbox_specializations.count(module)) {
1915 // If templated black boxes are used, the constructor of any module which includes the black box cell
1916 // (which calls the declared but not defined in the generated code `create` function) may only be used
1917 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1918 // a forward-declared explicit specialization.
1919 //
1920 // Option (b) makes it possible to have the generated code and the black box implementation in different
1921 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1922 // a specialization for every combination of parameters the generated code may use; but since the main
1923 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1924 // be very few such combinations anyway.
1925 for (auto specialization : blackbox_specializations[module]) {
1926 f << indent << "template<>\n";
1927 f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
1928 f << mangle(module) << specialization << "::";
1929 f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1930 f << "\n";
1931 }
1932 }
1933 } else {
1934 f << indent << "struct " << mangle(module) << " : public module {\n";
1935 inc_indent();
1936 for (auto wire : module->wires())
1937 dump_wire(wire, /*is_local=*/false);
1938 for (auto wire : module->wires())
1939 dump_debug_wire(wire, /*is_local=*/false);
1940 bool has_memories = false;
1941 for (auto memory : module->memories) {
1942 dump_memory(module, memory.second);
1943 has_memories = true;
1944 }
1945 if (has_memories)
1946 f << "\n";
1947 bool has_cells = false;
1948 for (auto cell : module->cells()) {
1949 if (is_internal_cell(cell->type))
1950 continue;
1951 dump_attrs(cell);
1952 RTLIL::Module *cell_module = module->design->module(cell->type);
1953 log_assert(cell_module != nullptr);
1954 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1955 f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
1956 f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
1957 f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
1958 dump_metadata_map(cell->parameters);
1959 f << ", ";
1960 dump_metadata_map(cell->attributes);
1961 f << ");\n";
1962 } else {
1963 f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
1964 }
1965 has_cells = true;
1966 }
1967 if (has_cells)
1968 f << "\n";
1969 f << indent << mangle(module) << "() {}\n";
1970 if (has_cells) {
1971 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) :\n";
1972 bool first = true;
1973 for (auto cell : module->cells()) {
1974 if (is_internal_cell(cell->type))
1975 continue;
1976 if (first) {
1977 first = false;
1978 } else {
1979 f << ",\n";
1980 }
1981 RTLIL::Module *cell_module = module->design->module(cell->type);
1982 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
1983 f << indent << " " << mangle(cell) << "(std::move(other." << mangle(cell) << "))";
1984 } else {
1985 f << indent << " " << mangle(cell) << "(adopt {}, std::move(other." << mangle(cell) << "))";
1986 }
1987 }
1988 f << " {\n";
1989 inc_indent();
1990 for (auto cell : module->cells()) {
1991 if (is_internal_cell(cell->type))
1992 continue;
1993 RTLIL::Module *cell_module = module->design->module(cell->type);
1994 if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
1995 f << indent << mangle(cell) << "->reset();\n";
1996 }
1997 dec_indent();
1998 f << indent << "}\n";
1999 } else {
2000 f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) {}\n";
2001 }
2002 f << "\n";
2003 f << indent << "void reset() override {\n";
2004 inc_indent();
2005 f << indent << "*this = " << mangle(module) << "(adopt {}, std::move(*this));\n";
2006 dec_indent();
2007 f << indent << "}\n";
2008 f << "\n";
2009 f << indent << "bool eval() override;\n";
2010 f << indent << "bool commit() override;\n";
2011 if (debug_info) {
2012 if (debug_eval) {
2013 f << "\n";
2014 f << indent << "void debug_eval();\n";
2015 for (auto wire : module->wires())
2016 if (debug_outlined_wires.count(wire)) {
2017 f << indent << "debug_outline debug_eval_outline { std::bind(&"
2018 << mangle(module) << "::debug_eval, this) };\n";
2019 break;
2020 }
2021 }
2022 f << "\n";
2023 f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
2024 }
2025 dec_indent();
2026 f << indent << "}; // struct " << mangle(module) << "\n";
2027 f << "\n";
2028 }
2029 }
2030
2031 void dump_module_impl(RTLIL::Module *module)
2032 {
2033 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
2034 return;
2035 f << indent << "bool " << mangle(module) << "::eval() {\n";
2036 dump_eval_method(module);
2037 f << indent << "}\n";
2038 f << "\n";
2039 f << indent << "bool " << mangle(module) << "::commit() {\n";
2040 dump_commit_method(module);
2041 f << indent << "}\n";
2042 f << "\n";
2043 if (debug_info) {
2044 if (debug_eval) {
2045 f << indent << "void " << mangle(module) << "::debug_eval() {\n";
2046 dump_debug_eval_method(module);
2047 f << indent << "}\n";
2048 f << "\n";
2049 }
2050 f << indent << "CXXRTL_EXTREMELY_COLD\n";
2051 f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
2052 dump_debug_info_method(module);
2053 f << indent << "}\n";
2054 f << "\n";
2055 }
2056 }
2057
2058 void dump_design(RTLIL::Design *design)
2059 {
2060 RTLIL::Module *top_module = nullptr;
2061 std::vector<RTLIL::Module*> modules;
2062 TopoSort<RTLIL::Module*> topo_design;
2063 for (auto module : design->modules()) {
2064 if (!design->selected_module(module))
2065 continue;
2066 if (module->get_bool_attribute(ID(cxxrtl_blackbox)))
2067 modules.push_back(module); // cxxrtl blackboxes first
2068 if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
2069 continue;
2070 if (module->get_bool_attribute(ID::top))
2071 top_module = module;
2072
2073 topo_design.node(module);
2074 for (auto cell : module->cells()) {
2075 if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
2076 continue;
2077 RTLIL::Module *cell_module = design->module(cell->type);
2078 log_assert(cell_module != nullptr);
2079 topo_design.edge(cell_module, module);
2080 }
2081 }
2082 bool no_loops = topo_design.sort();
2083 log_assert(no_loops);
2084 modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
2085
2086 if (split_intf) {
2087 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
2088 std::string include_guard = design_ns + "_header";
2089 std::transform(include_guard.begin(), include_guard.end(), include_guard.begin(), ::toupper);
2090
2091 f << "#ifndef " << include_guard << "\n";
2092 f << "#define " << include_guard << "\n";
2093 f << "\n";
2094 if (top_module != nullptr && debug_info) {
2095 f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
2096 f << "\n";
2097 f << "#ifdef __cplusplus\n";
2098 f << "extern \"C\" {\n";
2099 f << "#endif\n";
2100 f << "\n";
2101 f << "cxxrtl_toplevel " << design_ns << "_create();\n";
2102 f << "\n";
2103 f << "#ifdef __cplusplus\n";
2104 f << "}\n";
2105 f << "#endif\n";
2106 f << "\n";
2107 } else {
2108 f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
2109 f << "\n";
2110 }
2111 f << "#ifdef __cplusplus\n";
2112 f << "\n";
2113 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2114 f << "\n";
2115 f << "using namespace cxxrtl;\n";
2116 f << "\n";
2117 f << "namespace " << design_ns << " {\n";
2118 f << "\n";
2119 for (auto module : modules)
2120 dump_module_intf(module);
2121 f << "} // namespace " << design_ns << "\n";
2122 f << "\n";
2123 f << "#endif // __cplusplus\n";
2124 f << "\n";
2125 f << "#endif\n";
2126 *intf_f << f.str(); f.str("");
2127 }
2128
2129 if (split_intf)
2130 f << "#include \"" << intf_filename << "\"\n";
2131 else
2132 f << "#include <backends/cxxrtl/cxxrtl.h>\n";
2133 f << "\n";
2134 f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
2135 f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2136 f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
2137 f << "#endif\n";
2138 f << "\n";
2139 f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2140 f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
2141 f << "#endif\n";
2142 f << "\n";
2143 f << "using namespace cxxrtl_yosys;\n";
2144 f << "\n";
2145 f << "namespace " << design_ns << " {\n";
2146 f << "\n";
2147 for (auto module : modules) {
2148 if (!split_intf)
2149 dump_module_intf(module);
2150 dump_module_impl(module);
2151 }
2152 f << "} // namespace " << design_ns << "\n";
2153 f << "\n";
2154 if (top_module != nullptr && debug_info) {
2155 f << "extern \"C\"\n";
2156 f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
2157 inc_indent();
2158 std::string top_type = design_ns + "::" + mangle(top_module);
2159 f << indent << "return new _cxxrtl_toplevel { ";
2160 f << "std::unique_ptr<" << top_type << ">(new " + top_type + ")";
2161 f << " };\n";
2162 dec_indent();
2163 f << "}\n";
2164 }
2165
2166 *impl_f << f.str(); f.str("");
2167 }
2168
2169 // Edge-type sync rules require us to emit edge detectors, which require coordination between
2170 // eval and commit phases. To do this we need to collect them upfront.
2171 //
2172 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
2173 // operate at wire bit granularity; it is possible to have code similar to:
2174 // wire [3:0] clocks;
2175 // always @(posedge clocks[0]) ...
2176 // To handle this we track edge sensitivity both for wires and wire bits.
2177 void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
2178 {
2179 signal = sigmap(signal);
2180 log_assert(signal.is_wire() && signal.is_bit());
2181 log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
2182
2183 RTLIL::SigBit sigbit = signal[0];
2184 if (!edge_types.count(sigbit))
2185 edge_types[sigbit] = type;
2186 else if (edge_types[sigbit] != type)
2187 edge_types[sigbit] = RTLIL::STe;
2188 edge_wires.insert(signal.as_wire());
2189 }
2190
2191 void analyze_design(RTLIL::Design *design)
2192 {
2193 bool has_feedback_arcs = false;
2194 bool has_buffered_comb_wires = false;
2195
2196 for (auto module : design->modules()) {
2197 if (!design->selected_module(module))
2198 continue;
2199
2200 SigMap &sigmap = sigmaps[module];
2201 sigmap.set(module);
2202
2203 if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
2204 for (auto port : module->ports) {
2205 RTLIL::Wire *wire = module->wire(port);
2206 if (wire->port_input && !wire->port_output)
2207 unbuffered_wires.insert(wire);
2208 if (wire->has_attribute(ID(cxxrtl_edge))) {
2209 RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
2210 if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
2211 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
2212 log_id(module), log_signal(wire));
2213
2214 std::string edges = wire->get_string_attribute(ID(cxxrtl_edge));
2215 for (int i = 0; i < GetSize(wire); i++) {
2216 RTLIL::SigSpec wire_sig = wire;
2217 switch (edges[i]) {
2218 case '-': break;
2219 case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
2220 case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
2221 case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
2222 default:
2223 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
2224 "other than '-', 'p', 'n', or 'a'.\n",
2225 log_id(module), log_signal(wire));
2226 }
2227 }
2228 }
2229 }
2230
2231 // Black boxes converge by default, since their implementations are quite unlikely to require
2232 // internal propagation of comb signals.
2233 eval_converges[module] = true;
2234 continue;
2235 }
2236
2237 FlowGraph flow;
2238
2239 for (auto conn : module->connections())
2240 flow.add_node(conn);
2241
2242 dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
2243 dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
2244 pool<const RTLIL::Cell*>> memwr_per_domain;
2245 for (auto cell : module->cells()) {
2246 if (!cell->known())
2247 log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
2248
2249 RTLIL::Module *cell_module = design->module(cell->type);
2250 if (cell_module &&
2251 cell_module->get_blackbox_attribute() &&
2252 !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
2253 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
2254
2255 if (cell_module &&
2256 cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
2257 cell_module->get_bool_attribute(ID(cxxrtl_template)))
2258 blackbox_specializations[cell_module].insert(template_args(cell));
2259
2260 FlowGraph::Node *node = flow.add_node(cell);
2261
2262 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2263 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
2264 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2265 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2266 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2267 }
2268 // Similar for memory port cells.
2269 if (cell->type.in(ID($memrd), ID($memwr))) {
2270 if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
2271 if (sigmap(cell->getPort(ID::CLK)).is_wire())
2272 register_edge_signal(sigmap, cell->getPort(ID::CLK),
2273 cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
2274 }
2275 memrw_cell_nodes[cell] = node;
2276 }
2277 // Optimize access to read-only memories.
2278 if (cell->type == ID($memwr))
2279 writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
2280 // Collect groups of memory write ports in the same domain.
2281 if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
2282 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2283 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2284 memwr_per_domain[{clk_bit, memory}].insert(cell);
2285 }
2286 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2287 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2288 if (cell->type.in(ID($mem)))
2289 log_assert(false);
2290 }
2291 for (auto cell : module->cells()) {
2292 // Collect groups of memory write ports read by every transparent read port.
2293 if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
2294 cell->getParam(ID::TRANSPARENT).as_bool()) {
2295 RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
2296 const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
2297 for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
2298 transparent_for[cell].insert(memwr_cell);
2299 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2300 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2301 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
2302 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
2303 flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
2304 }
2305 }
2306 }
2307
2308 for (auto proc : module->processes) {
2309 flow.add_node(proc.second);
2310
2311 for (auto sync : proc.second->syncs)
2312 switch (sync->type) {
2313 // Edge-type sync rules require pre-registration.
2314 case RTLIL::STp:
2315 case RTLIL::STn:
2316 case RTLIL::STe:
2317 register_edge_signal(sigmap, sync->signal, sync->type);
2318 break;
2319
2320 // Level-type sync rules require no special handling.
2321 case RTLIL::ST0:
2322 case RTLIL::ST1:
2323 case RTLIL::STa:
2324 break;
2325
2326 case RTLIL::STg:
2327 log_cmd_error("Global clock is not supported.\n");
2328
2329 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2330 // attribute regardless of input.
2331 case RTLIL::STi:
2332 log_assert(false);
2333 }
2334 }
2335
2336 for (auto wire : module->wires()) {
2337 if (!flow.is_inlinable(wire)) continue;
2338 if (wire->port_id != 0) continue;
2339 if (wire->get_bool_attribute(ID::keep)) continue;
2340 if (wire->name.begins_with("$") && !inline_internal) continue;
2341 if (wire->name.begins_with("\\") && !inline_public) continue;
2342 if (edge_wires[wire]) continue;
2343 if (flow.wire_comb_defs[wire].size() > 1)
2344 log_cmd_error("Wire %s.%s has multiple drivers.\n", log_id(module), log_id(wire));
2345 log_assert(flow.wire_comb_defs[wire].size() == 1);
2346 inlined_wires[wire] = **flow.wire_comb_defs[wire].begin();
2347 }
2348
2349 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
2350 for (auto wire_comb_def : flow.wire_comb_defs)
2351 for (auto node : wire_comb_def.second)
2352 node_defs[node].insert(wire_comb_def.first);
2353
2354 dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_uses;
2355 for (auto wire_use : flow.wire_uses)
2356 for (auto node : wire_use.second)
2357 node_uses[node].insert(wire_use.first);
2358
2359 Scheduler<FlowGraph::Node> scheduler;
2360 dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
2361 for (auto node : flow.nodes)
2362 node_map[node] = scheduler.add(node);
2363 for (auto node_def : node_defs) {
2364 auto vertex = node_map[node_def.first];
2365 for (auto wire : node_def.second)
2366 for (auto succ_node : flow.wire_uses[wire]) {
2367 auto succ_vertex = node_map[succ_node];
2368 vertex->succs.insert(succ_vertex);
2369 succ_vertex->preds.insert(vertex);
2370 }
2371 }
2372
2373 auto eval_order = scheduler.schedule();
2374 pool<FlowGraph::Node*, hash_ptr_ops> evaluated;
2375 pool<const RTLIL::Wire*> feedback_wires;
2376 for (auto vertex : eval_order) {
2377 auto node = vertex->data;
2378 schedule[module].push_back(*node);
2379 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2380 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2381 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2382 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2383 evaluated.insert(node);
2384 for (auto wire : node_defs[node])
2385 for (auto succ_node : flow.wire_uses[wire])
2386 if (evaluated[succ_node]) {
2387 feedback_wires.insert(wire);
2388 // Feedback wires may never be inlined because feedback requires state, but the point of
2389 // inlining (and localization) is to eliminate state.
2390 inlined_wires.erase(wire);
2391 }
2392 }
2393
2394 if (!feedback_wires.empty()) {
2395 has_feedback_arcs = true;
2396 log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
2397 for (auto wire : feedback_wires)
2398 log(" %s\n", log_id(wire));
2399 }
2400
2401 for (auto wire : module->wires()) {
2402 if (feedback_wires[wire]) continue;
2403 if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
2404 if (wire->name.begins_with("$") && !unbuffer_internal) continue;
2405 if (wire->name.begins_with("\\") && !unbuffer_public) continue;
2406 if (flow.wire_sync_defs.count(wire) > 0) continue;
2407 unbuffered_wires.insert(wire);
2408 if (edge_wires[wire]) continue;
2409 if (wire->get_bool_attribute(ID::keep)) continue;
2410 if (wire->port_input || wire->port_output) continue;
2411 if (wire->name.begins_with("$") && !localize_internal) continue;
2412 if (wire->name.begins_with("\\") && !localize_public) continue;
2413 localized_wires.insert(wire);
2414 }
2415
2416 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2417 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2418 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2419 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2420 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2421 // also require more than one delta cycle to converge.
2422 pool<const RTLIL::Wire*> buffered_comb_wires;
2423 for (auto wire : module->wires()) {
2424 if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
2425 buffered_comb_wires.insert(wire);
2426 }
2427 if (!buffered_comb_wires.empty()) {
2428 has_buffered_comb_wires = true;
2429 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
2430 for (auto wire : buffered_comb_wires)
2431 log(" %s\n", log_id(wire));
2432 }
2433
2434 eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
2435
2436 for (auto item : flow.bit_has_state)
2437 bit_has_state.insert(item);
2438
2439 if (debug_info && debug_eval) {
2440 // Find wires that can be be outlined, i.e. whose values can be always recovered from
2441 // the values of other wires. (This is the inverse of inlining--any wire that can be
2442 // inlined can also be outlined.) Although this may seem strictly less efficient, since
2443 // such values are computed at least twice, second-order effects make outlining useful.
2444 pool<const RTLIL::Wire*> worklist, visited;
2445 for (auto wire : module->wires()) {
2446 if (!wire->name.isPublic())
2447 continue;
2448 worklist.insert(wire);
2449 }
2450 while (!worklist.empty()) {
2451 const RTLIL::Wire *wire = worklist.pop();
2452 visited.insert(wire);
2453 if (!localized_wires.count(wire) && !inlined_wires.count(wire))
2454 continue; // member wire, doesn't need outlining
2455 if (wire->name.isPublic() || !inlined_wires.count(wire))
2456 debug_outlined_wires.insert(wire); // allow outlining of internal wires only
2457 for (auto node : flow.wire_comb_defs[wire])
2458 for (auto node_use : node_uses[node])
2459 if (!visited.count(node_use))
2460 worklist.insert(node_use);
2461 }
2462 }
2463 if (debug_info && debug_alias) {
2464 // Find wires that alias other wires or are tied to a constant. Both of these cases are
2465 // directly expressible in the debug information, improving coverage at zero cost.
2466 for (auto wire : module->wires()) {
2467 if (!wire->name.isPublic())
2468 continue;
2469 const RTLIL::Wire *cursor = wire;
2470 RTLIL::SigSpec alias_of;
2471 while (1) {
2472 if (!(flow.wire_def_inlinable.count(cursor) && flow.wire_def_inlinable[cursor]))
2473 break; // not an alias: complex def
2474 log_assert(flow.wire_comb_defs[cursor].size() == 1);
2475 FlowGraph::Node *node = *flow.wire_comb_defs[cursor].begin();
2476 if (node->type != FlowGraph::Node::Type::CONNECT)
2477 break; // not an alias: def by cell
2478 RTLIL::SigSpec rhs_sig = node->connect.second;
2479 if (rhs_sig.is_fully_const()) {
2480 alias_of = rhs_sig; // alias of const
2481 break;
2482 } else if (rhs_sig.is_wire()) {
2483 RTLIL::Wire *rhs_wire = rhs_sig.as_wire(); // possible alias of wire
2484 if (rhs_wire->port_input && !rhs_wire->port_output) {
2485 alias_of = rhs_wire; // alias of input
2486 break;
2487 } else if (!localized_wires.count(rhs_wire) && !inlined_wires.count(rhs_wire)) {
2488 alias_of = rhs_wire; // alias of member
2489 break;
2490 } else {
2491 if (rhs_wire->name.isPublic() && debug_outlined_wires.count(rhs_wire))
2492 alias_of = rhs_wire; // alias of either outline or another alias
2493 cursor = rhs_wire; // keep looking
2494 }
2495 } else {
2496 break; // not an alias: complex rhs
2497 }
2498 }
2499 if (alias_of.empty()) {
2500 continue;
2501 } else if (alias_of.is_fully_const()) {
2502 debug_const_wires[wire] = alias_of.as_const();
2503 } else if (alias_of.is_wire()) {
2504 debug_alias_wires[wire] = alias_of.as_wire();
2505 } else log_abort();
2506 if (inlined_wires.count(wire))
2507 debug_outlined_wires.erase(wire);
2508 }
2509 }
2510 }
2511 if (has_feedback_arcs || has_buffered_comb_wires) {
2512 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2513 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2514 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2515 const char *why_pessimistic = nullptr;
2516 if (has_feedback_arcs)
2517 why_pessimistic = "feedback wires";
2518 else if (has_buffered_comb_wires)
2519 why_pessimistic = "buffered combinatorial wires";
2520 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
2521 if (!run_flatten)
2522 log("Flattening may eliminate %s from the design.\n", why_pessimistic);
2523 if (!run_proc)
2524 log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic);
2525 }
2526 }
2527
2528 void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init, bool &has_packed_mem)
2529 {
2530 has_sync_init = has_packed_mem = has_top = false;
2531
2532 for (auto module : design->modules()) {
2533 if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
2534 continue;
2535
2536 if (!design->selected_whole_module(module))
2537 if (design->selected_module(module))
2538 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
2539 if (!design->selected_module(module))
2540 continue;
2541
2542 if (module->get_bool_attribute(ID::top))
2543 has_top = true;
2544
2545 for (auto proc : module->processes)
2546 for (auto sync : proc.second->syncs)
2547 if (sync->type == RTLIL::STi)
2548 has_sync_init = true;
2549
2550 // The Mem constructor also checks for well-formedness of $meminit cells, if any.
2551 for (auto &mem : Mem::get_all_memories(module))
2552 if (mem.packed)
2553 has_packed_mem = true;
2554 }
2555 }
2556
2557 void prepare_design(RTLIL::Design *design)
2558 {
2559 bool did_anything = false;
2560 bool has_top, has_sync_init, has_packed_mem;
2561 log_push();
2562 check_design(design, has_top, has_sync_init, has_packed_mem);
2563 if (run_hierarchy && !has_top) {
2564 Pass::call(design, "hierarchy -auto-top");
2565 did_anything = true;
2566 }
2567 if (run_flatten) {
2568 Pass::call(design, "flatten");
2569 did_anything = true;
2570 }
2571 if (run_proc) {
2572 Pass::call(design, "proc");
2573 did_anything = true;
2574 } else if (has_sync_init) {
2575 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2576 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2577 Pass::call(design, "proc_prune");
2578 Pass::call(design, "proc_clean");
2579 Pass::call(design, "proc_init");
2580 did_anything = true;
2581 }
2582 if (has_packed_mem) {
2583 Pass::call(design, "memory_unpack");
2584 did_anything = true;
2585 }
2586 // Recheck the design if it was modified.
2587 if (did_anything)
2588 check_design(design, has_top, has_sync_init, has_packed_mem);
2589 log_assert(has_top && !has_sync_init && !has_packed_mem);
2590 log_pop();
2591 if (did_anything)
2592 log_spacer();
2593 analyze_design(design);
2594 }
2595 };
2596
2597 struct CxxrtlBackend : public Backend {
2598 static const int DEFAULT_OPT_LEVEL = 6;
2599 static const int DEFAULT_DEBUG_LEVEL = 3;
2600
2601 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2602 void help() override
2603 {
2604 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2605 log("\n");
2606 log(" write_cxxrtl [options] [filename]\n");
2607 log("\n");
2608 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2609 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2610 log("\n");
2611 log("The following driver may be used as an example for a design with a single clock\n");
2612 log("driving rising edge triggered flip-flops:\n");
2613 log("\n");
2614 log(" #include \"top.cc\"\n");
2615 log("\n");
2616 log(" int main() {\n");
2617 log(" cxxrtl_design::p_top top;\n");
2618 log(" top.step();\n");
2619 log(" while (1) {\n");
2620 log(" /* user logic */\n");
2621 log(" top.p_clk.set(false);\n");
2622 log(" top.step();\n");
2623 log(" top.p_clk.set(true);\n");
2624 log(" top.step();\n");
2625 log(" }\n");
2626 log(" }\n");
2627 log("\n");
2628 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2629 log("subject to race conditions. If, in the example above, the user logic would run\n");
2630 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2631 log("\n");
2632 log("This backend supports replacing parts of the design with black boxes implemented\n");
2633 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2634 log("and the generated code consists only of an interface and a factory function.\n");
2635 log("The driver must implement the factory function that creates an implementation of\n");
2636 log("the black box, taking into account the parameters it is instantiated with.\n");
2637 log("\n");
2638 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2639 log("a synchronous debug sink:\n");
2640 log("\n");
2641 log(" (* cxxrtl_blackbox *)\n");
2642 log(" module debug(...);\n");
2643 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2644 log(" input en;\n");
2645 log(" input [7:0] i_data;\n");
2646 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2647 log(" endmodule\n");
2648 log("\n");
2649 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2650 log("\n");
2651 log(" struct bb_p_debug : public module {\n");
2652 log(" value<1> p_clk;\n");
2653 log(" bool posedge_p_clk() const { /* ... */ }\n");
2654 log(" value<1> p_en;\n");
2655 log(" value<8> p_i_data;\n");
2656 log(" wire<8> p_o_data;\n");
2657 log("\n");
2658 log(" bool eval() override;\n");
2659 log(" bool commit() override;\n");
2660 log("\n");
2661 log(" static std::unique_ptr<bb_p_debug>\n");
2662 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2663 log(" };\n");
2664 log("\n");
2665 log("The `create' function must be implemented by the driver. For example, it could\n");
2666 log("always provide an implementation logging the values to standard error stream:\n");
2667 log("\n");
2668 log(" namespace cxxrtl_design {\n");
2669 log("\n");
2670 log(" struct stderr_debug : public bb_p_debug {\n");
2671 log(" bool eval() override {\n");
2672 log(" if (posedge_p_clk() && p_en)\n");
2673 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2674 log(" p_o_data.next = p_i_data;\n");
2675 log(" return bb_p_debug::eval();\n");
2676 log(" }\n");
2677 log(" };\n");
2678 log("\n");
2679 log(" std::unique_ptr<bb_p_debug>\n");
2680 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2681 log(" cxxrtl::metadata_map attributes) {\n");
2682 log(" return std::make_unique<stderr_debug>();\n");
2683 log(" }\n");
2684 log("\n");
2685 log(" }\n");
2686 log("\n");
2687 log("For complex applications of black boxes, it is possible to parameterize their\n");
2688 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2689 log("interface for a configurable width debug sink:\n");
2690 log("\n");
2691 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2692 log(" module debug(...);\n");
2693 log(" parameter WIDTH = 8;\n");
2694 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2695 log(" input en;\n");
2696 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2697 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2698 log(" endmodule\n");
2699 log("\n");
2700 log("For this parametric HDL interface, this backend will generate the following C++\n");
2701 log("interface (only the differences are shown):\n");
2702 log("\n");
2703 log(" template<size_t WIDTH>\n");
2704 log(" struct bb_p_debug : public module {\n");
2705 log(" // ...\n");
2706 log(" value<WIDTH> p_i_data;\n");
2707 log(" wire<WIDTH> p_o_data;\n");
2708 log(" // ...\n");
2709 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2710 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2711 log(" };\n");
2712 log("\n");
2713 log("The `create' function must be implemented by the driver, specialized for every\n");
2714 log("possible combination of template parameters. (Specialization is necessary to\n");
2715 log("enable separate compilation of generated code and black box implementations.)\n");
2716 log("\n");
2717 log(" template<size_t SIZE>\n");
2718 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2719 log(" // ...\n");
2720 log(" };\n");
2721 log("\n");
2722 log(" template<>\n");
2723 log(" std::unique_ptr<bb_p_debug<8>>\n");
2724 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2725 log(" cxxrtl::metadata_map attributes) {\n");
2726 log(" return std::make_unique<stderr_debug<8>>();\n");
2727 log(" }\n");
2728 log("\n");
2729 log("The following attributes are recognized by this backend:\n");
2730 log("\n");
2731 log(" cxxrtl_blackbox\n");
2732 log(" only valid on modules. if specified, the module contents are ignored,\n");
2733 log(" and the generated code includes only the module interface and a factory\n");
2734 log(" function, which will be called to instantiate the module.\n");
2735 log("\n");
2736 log(" cxxrtl_edge\n");
2737 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2738 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2739 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2740 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2741 log("\n");
2742 log(" cxxrtl_template\n");
2743 log(" only valid on black boxes. must contain a space separated sequence of\n");
2744 log(" identifiers that have a corresponding black box parameters. for each\n");
2745 log(" of them, the generated code includes a `size_t` template parameter.\n");
2746 log("\n");
2747 log(" cxxrtl_width\n");
2748 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2749 log(" is directly inserted into generated code.\n");
2750 log("\n");
2751 log(" cxxrtl_comb, cxxrtl_sync\n");
2752 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2753 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2754 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2755 log(" if neither is specified, the output will be pessimistically treated as\n");
2756 log(" driven by both combinatorial and synchronous logic.\n");
2757 log("\n");
2758 log("The following options are supported by this backend:\n");
2759 log("\n");
2760 log(" -header\n");
2761 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2762 log(" if specified, the backend must be called with a filename, and filename\n");
2763 log(" of the interface is derived from filename of the implementation.\n");
2764 log(" otherwise, interface and implementation are generated together.\n");
2765 log("\n");
2766 log(" -namespace <ns-name>\n");
2767 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2768 log(" \"cxxrtl_design\" is used.\n");
2769 log("\n");
2770 log(" -nohierarchy\n");
2771 log(" use design hierarchy as-is. in most designs, a top module should be\n");
2772 log(" present as it is exposed through the C API and has unbuffered outputs\n");
2773 log(" for improved performance; it will be determined automatically if absent.\n");
2774 log("\n");
2775 log(" -noflatten\n");
2776 log(" don't flatten the design. fully flattened designs can evaluate within\n");
2777 log(" one delta cycle if they have no combinatorial feedback.\n");
2778 log(" note that the debug interface and waveform dumps use full hierarchical\n");
2779 log(" names for all wires even in flattened designs.\n");
2780 log("\n");
2781 log(" -noproc\n");
2782 log(" don't convert processes to netlists. in most designs, converting\n");
2783 log(" processes significantly improves evaluation performance at the cost of\n");
2784 log(" slight increase in compilation time.\n");
2785 log("\n");
2786 log(" -O <level>\n");
2787 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
2788 log(" levels dramatically decrease compile and run time, and highest level\n");
2789 log(" possible for a design should be used.\n");
2790 log("\n");
2791 log(" -O0\n");
2792 log(" no optimization.\n");
2793 log("\n");
2794 log(" -O1\n");
2795 log(" localize internal wires if possible.\n");
2796 log("\n");
2797 log(" -O2\n");
2798 log(" like -O1, and unbuffer internal wires if possible.\n");
2799 log("\n");
2800 log(" -O3\n");
2801 log(" like -O2, and inline internal wires if possible.\n");
2802 log("\n");
2803 log(" -O4\n");
2804 log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
2805 log("\n");
2806 log(" -O5\n");
2807 log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
2808 log("\n");
2809 log(" -O6\n");
2810 log(" like -O5, and inline public wires not marked (*keep*) if possible.\n");
2811 log("\n");
2812 log(" -g <level>\n");
2813 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
2814 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2815 log("\n");
2816 log(" -g0\n");
2817 log(" no debug information. the C API is unavailable.\n");
2818 log("\n");
2819 log(" -g1\n");
2820 log(" debug information for member public wires only. this is the bare minimum\n");
2821 log(" necessary to access all design state. enables the C API.\n");
2822 log("\n");
2823 log(" -g2\n");
2824 log(" like -g1, and include debug information for public wires that are tied\n");
2825 log(" to a constant or another public wire.\n");
2826 log("\n");
2827 log(" -g3\n");
2828 log(" like -g2, and compute debug information on demand for all public wires\n");
2829 log(" that were optimized out.\n");
2830 log("\n");
2831 }
2832
2833 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
2834 {
2835 bool nohierarchy = false;
2836 bool noflatten = false;
2837 bool noproc = false;
2838 int opt_level = DEFAULT_OPT_LEVEL;
2839 int debug_level = DEFAULT_DEBUG_LEVEL;
2840 CxxrtlWorker worker;
2841
2842 log_header(design, "Executing CXXRTL backend.\n");
2843
2844 size_t argidx;
2845 for (argidx = 1; argidx < args.size(); argidx++)
2846 {
2847 if (args[argidx] == "-nohierarchy") {
2848 nohierarchy = true;
2849 continue;
2850 }
2851 if (args[argidx] == "-noflatten") {
2852 noflatten = true;
2853 continue;
2854 }
2855 if (args[argidx] == "-noproc") {
2856 noproc = true;
2857 continue;
2858 }
2859 if (args[argidx] == "-Og") {
2860 log_warning("The `-Og` option has been removed. Use `-g3` instead for complete "
2861 "design coverage regardless of optimization level.\n");
2862 continue;
2863 }
2864 if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
2865 argidx++;
2866 log_warning("The `-Og` option has been removed. Use `-g3` instead for complete "
2867 "design coverage regardless of optimization level.\n");
2868 continue;
2869 }
2870 if (args[argidx] == "-O" && argidx+1 < args.size()) {
2871 opt_level = std::stoi(args[++argidx]);
2872 continue;
2873 }
2874 if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2875 opt_level = std::stoi(args[argidx].substr(2));
2876 continue;
2877 }
2878 if (args[argidx] == "-g" && argidx+1 < args.size()) {
2879 debug_level = std::stoi(args[++argidx]);
2880 continue;
2881 }
2882 if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
2883 debug_level = std::stoi(args[argidx].substr(2));
2884 continue;
2885 }
2886 if (args[argidx] == "-header") {
2887 worker.split_intf = true;
2888 continue;
2889 }
2890 if (args[argidx] == "-namespace" && argidx+1 < args.size()) {
2891 worker.design_ns = args[++argidx];
2892 continue;
2893 }
2894 break;
2895 }
2896 extra_args(f, filename, args, argidx);
2897
2898 worker.run_hierarchy = !nohierarchy;
2899 worker.run_flatten = !noflatten;
2900 worker.run_proc = !noproc;
2901 switch (opt_level) {
2902 // the highest level here must match DEFAULT_OPT_LEVEL
2903 case 6:
2904 worker.inline_public = true;
2905 YS_FALLTHROUGH
2906 case 5:
2907 worker.localize_public = true;
2908 YS_FALLTHROUGH
2909 case 4:
2910 worker.unbuffer_public = true;
2911 YS_FALLTHROUGH
2912 case 3:
2913 worker.inline_internal = true;
2914 YS_FALLTHROUGH
2915 case 2:
2916 worker.localize_internal = true;
2917 YS_FALLTHROUGH
2918 case 1:
2919 worker.unbuffer_internal = true;
2920 YS_FALLTHROUGH
2921 case 0:
2922 break;
2923 default:
2924 log_cmd_error("Invalid optimization level %d.\n", opt_level);
2925 }
2926 switch (debug_level) {
2927 // the highest level here must match DEFAULT_DEBUG_LEVEL
2928 case 3:
2929 worker.debug_eval = true;
2930 YS_FALLTHROUGH
2931 case 2:
2932 worker.debug_alias = true;
2933 YS_FALLTHROUGH
2934 case 1:
2935 worker.debug_info = true;
2936 YS_FALLTHROUGH
2937 case 0:
2938 break;
2939 default:
2940 log_cmd_error("Invalid debug information level %d.\n", debug_level);
2941 }
2942
2943 std::ofstream intf_f;
2944 if (worker.split_intf) {
2945 if (filename == "<stdout>")
2946 log_cmd_error("Option -header must be used with a filename.\n");
2947
2948 worker.intf_filename = filename.substr(0, filename.rfind('.')) + ".h";
2949 intf_f.open(worker.intf_filename, std::ofstream::trunc);
2950 if (intf_f.fail())
2951 log_cmd_error("Can't open file `%s' for writing: %s\n",
2952 worker.intf_filename.c_str(), strerror(errno));
2953
2954 worker.intf_f = &intf_f;
2955 }
2956 worker.impl_f = f;
2957
2958 worker.prepare_design(design);
2959 worker.dump_design(design);
2960 }
2961 } CxxrtlBackend;
2962
2963 PRIVATE_NAMESPACE_END