2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25 #include "kernel/mem.h"
26 #include "kernel/log.h"
29 PRIVATE_NAMESPACE_BEGIN
32 // Peter Eades; Xuemin Lin; W. F. Smyth, "A Fast Effective Heuristic For The Feedback Arc Set Problem"
33 // Information Processing Letters, Vol. 47, pp 319-323, 1993
34 // https://pdfs.semanticscholar.org/c7ed/d9acce96ca357876540e19664eb9d976637f.pdf
36 // A topological sort (on a cell/wire graph) is always possible in a fully flattened RTLIL design without
37 // processes or logic loops where every wire has a single driver. Logic loops are illegal in RTLIL and wires
38 // with multiple drivers can be split by the `splitnets` pass; however, interdependencies between processes
39 // or module instances can create strongly connected components without introducing evaluation nondeterminism.
40 // We wish to support designs with such benign SCCs (as well as designs with multiple drivers per wire), so
41 // we sort the graph in a way that minimizes feedback arcs. If there are no feedback arcs in the sorted graph,
42 // then a more efficient evaluation method is possible, since eval() will always immediately converge.
48 pool
<Vertex
*, hash_ptr_ops
> preds
, succs
;
50 Vertex() : data(NULL
), prev(this), next(this) {}
51 Vertex(T
*data
) : data(data
), prev(NULL
), next(NULL
) {}
55 log_assert(data
== NULL
);
57 log_assert(prev
== next
);
63 void link(Vertex
*list
)
65 log_assert(prev
== NULL
&& next
== NULL
);
68 list
->prev
->next
= this;
74 log_assert(prev
->next
== this && next
->prev
== this);
82 return succs
.size() - preds
.size();
86 std::vector
<Vertex
*> vertices
;
87 Vertex
*sources
= new Vertex
;
88 Vertex
*sinks
= new Vertex
;
89 dict
<int, Vertex
*> bins
;
97 for (auto vertex
: vertices
)
103 Vertex
*vertex
= new Vertex(data
);
104 vertices
.push_back(vertex
);
108 void relink(Vertex
*vertex
)
110 if (vertex
->succs
.empty())
112 else if (vertex
->preds
.empty())
113 vertex
->link(sources
);
115 int delta
= vertex
->delta();
116 if (!bins
.count(delta
))
117 bins
[delta
] = new Vertex
;
118 vertex
->link(bins
[delta
]);
122 Vertex
*remove(Vertex
*vertex
)
125 for (auto pred
: vertex
->preds
) {
128 log_assert(pred
->succs
[vertex
]);
130 pred
->succs
.erase(vertex
);
133 for (auto succ
: vertex
->succs
) {
136 log_assert(succ
->preds
[vertex
]);
138 succ
->preds
.erase(vertex
);
141 vertex
->preds
.clear();
142 vertex
->succs
.clear();
146 std::vector
<Vertex
*> schedule()
148 std::vector
<Vertex
*> s1
, s2r
;
149 for (auto vertex
: vertices
)
151 bool bins_empty
= false;
152 while (!(sinks
->empty() && sources
->empty() && bins_empty
)) {
153 while (!sinks
->empty())
154 s2r
.push_back(remove(sinks
->next
));
155 while (!sources
->empty())
156 s1
.push_back(remove(sources
->next
));
157 // Choosing u in this implementation isn't O(1), but the paper handwaves which data structure they suggest
158 // using to get O(1) relinking *and* find-max-key ("it is clear"... no it isn't), so this code uses a very
159 // naive implementation of find-max-key.
161 bins
.template sort
<std::greater
<int>>();
162 for (auto bin
: bins
) {
163 if (!bin
.second
->empty()) {
165 s1
.push_back(remove(bin
.second
->next
));
170 s1
.insert(s1
.end(), s2r
.rbegin(), s2r
.rend());
175 bool is_unary_cell(RTLIL::IdString type
)
178 ID($
not), ID($logic_not
), ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
),
182 bool is_binary_cell(RTLIL::IdString type
)
185 ID($
and), ID($
or), ID($
xor), ID($xnor
), ID($logic_and
), ID($logic_or
),
186 ID($shl
), ID($sshl
), ID($shr
), ID($sshr
), ID($shift
), ID($shiftx
),
187 ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($gt
), ID($ge
), ID($lt
), ID($le
),
188 ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
));
191 bool is_extending_cell(RTLIL::IdString type
)
194 ID($logic_not
), ID($logic_and
), ID($logic_or
),
195 ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
));
198 bool is_elidable_cell(RTLIL::IdString type
)
200 return is_unary_cell(type
) || is_binary_cell(type
) || type
.in(
201 ID($mux
), ID($concat
), ID($slice
), ID($pmux
));
204 bool is_ff_cell(RTLIL::IdString type
)
207 ID($dff
), ID($dffe
), ID($sdff
), ID($sdffe
), ID($sdffce
),
208 ID($adff
), ID($adffe
), ID($dffsr
), ID($dffsre
),
209 ID($dlatch
), ID($adlatch
), ID($dlatchsr
), ID($sr
));
212 bool is_internal_cell(RTLIL::IdString type
)
214 return !type
.isPublic() && !type
.begins_with("$paramod");
217 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell
*cell
)
219 RTLIL::Module
*cell_module
= cell
->module
->design
->module(cell
->type
);
220 log_assert(cell_module
!= nullptr);
221 return cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
));
224 enum class CxxrtlPortType
{
225 UNKNOWN
= 0, // or mixed comb/sync
230 CxxrtlPortType
cxxrtl_port_type(const RTLIL::Cell
*cell
, RTLIL::IdString port
)
232 RTLIL::Module
*cell_module
= cell
->module
->design
->module(cell
->type
);
233 if (cell_module
== nullptr || !cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
)))
234 return CxxrtlPortType::UNKNOWN
;
235 RTLIL::Wire
*cell_output_wire
= cell_module
->wire(port
);
236 log_assert(cell_output_wire
!= nullptr);
237 bool is_comb
= cell_output_wire
->get_bool_attribute(ID(cxxrtl_comb
));
238 bool is_sync
= cell_output_wire
->get_bool_attribute(ID(cxxrtl_sync
));
239 if (is_comb
&& is_sync
)
240 log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n",
241 log_id(cell_module
), log_signal(cell_output_wire
));
243 return CxxrtlPortType::COMB
;
245 return CxxrtlPortType::SYNC
;
246 return CxxrtlPortType::UNKNOWN
;
249 bool is_cxxrtl_comb_port(const RTLIL::Cell
*cell
, RTLIL::IdString port
)
251 return cxxrtl_port_type(cell
, port
) == CxxrtlPortType::COMB
;
254 bool is_cxxrtl_sync_port(const RTLIL::Cell
*cell
, RTLIL::IdString port
)
256 return cxxrtl_port_type(cell
, port
) == CxxrtlPortType::SYNC
;
269 RTLIL::SigSig connect
= {};
270 const RTLIL::Cell
*cell
= NULL
;
271 const RTLIL::Process
*process
= NULL
;
274 std::vector
<Node
*> nodes
;
275 dict
<const RTLIL::Wire
*, pool
<Node
*, hash_ptr_ops
>> wire_comb_defs
, wire_sync_defs
, wire_uses
;
276 dict
<const RTLIL::Wire
*, bool> wire_def_elidable
, wire_use_elidable
;
277 dict
<RTLIL::SigBit
, bool> bit_has_state
;
281 for (auto node
: nodes
)
285 void add_defs(Node
*node
, const RTLIL::SigSpec
&sig
, bool is_ff
, bool elidable
)
287 for (auto chunk
: sig
.chunks())
290 // A sync def means that a wire holds design state because it is driven directly by
291 // a flip-flop output. Such a wire can never be unbuffered.
292 wire_sync_defs
[chunk
.wire
].insert(node
);
294 // A comb def means that a wire doesn't hold design state. It might still be connected,
295 // indirectly, to a flip-flop output.
296 wire_comb_defs
[chunk
.wire
].insert(node
);
299 for (auto bit
: sig
.bits())
300 bit_has_state
[bit
] |= is_ff
;
301 // Only comb defs of an entire wire in the right order can be elided.
302 if (!is_ff
&& sig
.is_wire())
303 wire_def_elidable
[sig
.as_wire()] = elidable
;
306 void add_uses(Node
*node
, const RTLIL::SigSpec
&sig
)
308 for (auto chunk
: sig
.chunks())
310 wire_uses
[chunk
.wire
].insert(node
);
311 // Only a single use of an entire wire in the right order can be elided.
312 // (But the use can include other chunks.)
313 if (!wire_use_elidable
.count(chunk
.wire
))
314 wire_use_elidable
[chunk
.wire
] = true;
316 wire_use_elidable
[chunk
.wire
] = false;
320 bool is_elidable(const RTLIL::Wire
*wire
) const
322 if (wire_def_elidable
.count(wire
) && wire_use_elidable
.count(wire
))
323 return wire_def_elidable
.at(wire
) && wire_use_elidable
.at(wire
);
328 void add_connect_defs_uses(Node
*node
, const RTLIL::SigSig
&conn
)
330 add_defs(node
, conn
.first
, /*is_ff=*/false, /*elidable=*/true);
331 add_uses(node
, conn
.second
);
334 Node
*add_node(const RTLIL::SigSig
&conn
)
336 Node
*node
= new Node
;
337 node
->type
= Node::Type::CONNECT
;
338 node
->connect
= conn
;
339 nodes
.push_back(node
);
340 add_connect_defs_uses(node
, conn
);
345 void add_cell_sync_defs(Node
*node
, const RTLIL::Cell
*cell
)
347 // To understand why this node type is necessary and why it produces comb defs, consider a cell
348 // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
349 // not result in a feedback arc because the output is synchronous. However, a naive implementation
350 // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
351 // would not be able to immediately converge...
354 // cell->p_i = i_tmp.curr;
356 // i_tmp.next = cell->p_o.curr;
358 // ... since the wire connecting the input and output ports would not be localizable. To solve
359 // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
360 // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
363 // i_tmp = cell->p_o.curr;
364 // cell->p_i = i_tmp;
367 // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
368 // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
369 // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
370 // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
371 // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
372 // and the left-hand side has a comb def.
373 for (auto conn
: cell
->connections())
374 if (cell
->output(conn
.first
))
375 if (is_cxxrtl_sync_port(cell
, conn
.first
)) {
376 // See note regarding elidability below.
377 add_defs(node
, conn
.second
, /*is_ff=*/false, /*elidable=*/false);
381 void add_cell_eval_defs_uses(Node
*node
, const RTLIL::Cell
*cell
)
383 for (auto conn
: cell
->connections()) {
384 if (cell
->output(conn
.first
)) {
385 if (is_elidable_cell(cell
->type
))
386 add_defs(node
, conn
.second
, /*is_ff=*/false, /*elidable=*/true);
387 else if (is_ff_cell(cell
->type
) || (cell
->type
== ID($memrd
) && cell
->getParam(ID::CLK_ENABLE
).as_bool()))
388 add_defs(node
, conn
.second
, /*is_ff=*/true, /*elidable=*/false);
389 else if (is_internal_cell(cell
->type
))
390 add_defs(node
, conn
.second
, /*is_ff=*/false, /*elidable=*/false);
391 else if (!is_cxxrtl_sync_port(cell
, conn
.first
)) {
392 // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
393 // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
394 // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
395 // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
396 // the infrastructure required to elide outputs of cells with many of them.
397 add_defs(node
, conn
.second
, /*is_ff=*/false, /*elidable=*/false);
400 if (cell
->input(conn
.first
))
401 add_uses(node
, conn
.second
);
405 Node
*add_node(const RTLIL::Cell
*cell
)
407 log_assert(cell
->known());
409 bool has_fully_sync_outputs
= false;
410 for (auto conn
: cell
->connections())
411 if (cell
->output(conn
.first
) && is_cxxrtl_sync_port(cell
, conn
.first
)) {
412 has_fully_sync_outputs
= true;
415 if (has_fully_sync_outputs
) {
416 Node
*node
= new Node
;
417 node
->type
= Node::Type::CELL_SYNC
;
419 nodes
.push_back(node
);
420 add_cell_sync_defs(node
, cell
);
423 Node
*node
= new Node
;
424 node
->type
= Node::Type::CELL_EVAL
;
426 nodes
.push_back(node
);
427 add_cell_eval_defs_uses(node
, cell
);
432 void add_case_defs_uses(Node
*node
, const RTLIL::CaseRule
*case_
)
434 for (auto &action
: case_
->actions
) {
435 add_defs(node
, action
.first
, /*is_ff=*/false, /*elidable=*/false);
436 add_uses(node
, action
.second
);
438 for (auto sub_switch
: case_
->switches
) {
439 add_uses(node
, sub_switch
->signal
);
440 for (auto sub_case
: sub_switch
->cases
) {
441 for (auto &compare
: sub_case
->compare
)
442 add_uses(node
, compare
);
443 add_case_defs_uses(node
, sub_case
);
448 void add_process_defs_uses(Node
*node
, const RTLIL::Process
*process
)
450 add_case_defs_uses(node
, &process
->root_case
);
451 for (auto sync
: process
->syncs
)
452 for (auto action
: sync
->actions
) {
453 if (sync
->type
== RTLIL::STp
|| sync
->type
== RTLIL::STn
|| sync
->type
== RTLIL::STe
)
454 add_defs(node
, action
.first
, /*is_ff=*/true, /*elidable=*/false);
456 add_defs(node
, action
.first
, /*is_ff=*/false, /*elidable=*/false);
457 add_uses(node
, action
.second
);
461 Node
*add_node(const RTLIL::Process
*process
)
463 Node
*node
= new Node
;
464 node
->type
= Node::Type::PROCESS
;
465 node
->process
= process
;
466 nodes
.push_back(node
);
467 add_process_defs_uses(node
, process
);
472 std::vector
<std::string
> split_by(const std::string
&str
, const std::string
&sep
)
474 std::vector
<std::string
> result
;
477 size_t curr
= str
.find_first_of(sep
, prev
);
478 if (curr
== std::string::npos
) {
479 std::string part
= str
.substr(prev
);
480 if (!part
.empty()) result
.push_back(part
);
483 std::string part
= str
.substr(prev
, curr
- prev
);
484 if (!part
.empty()) result
.push_back(part
);
491 std::string
escape_cxx_string(const std::string
&input
)
493 std::string output
= "\"";
494 for (auto c
: input
) {
497 output
.push_back('\\');
500 char l
= c
& 0xf, h
= (c
>> 4) & 0xf;
501 output
.append("\\x");
502 output
.push_back((h
< 10 ? '0' + h
: 'a' + h
- 10));
503 output
.push_back((l
< 10 ? '0' + l
: 'a' + l
- 10));
506 output
.push_back('"');
507 if (output
.find('\0') != std::string::npos
) {
508 output
.insert(0, "std::string {");
509 output
.append(stringf(", %zu}", input
.size()));
515 std::string
get_hdl_name(T
*object
)
517 if (object
->has_attribute(ID::hdlname
))
518 return object
->get_string_attribute(ID::hdlname
);
520 return object
->name
.str().substr(1);
523 struct CxxrtlWorker
{
524 bool split_intf
= false;
525 std::string intf_filename
;
526 std::string design_ns
= "cxxrtl_design";
527 std::ostream
*impl_f
= nullptr;
528 std::ostream
*intf_f
= nullptr;
530 bool run_hierarchy
= false;
531 bool run_flatten
= false;
532 bool run_proc
= false;
534 bool unbuffer_internal
= false;
535 bool unbuffer_public
= false;
536 bool localize_internal
= false;
537 bool localize_public
= false;
538 bool elide_internal
= false;
539 bool elide_public
= false;
541 bool debug_info
= false;
543 std::ostringstream f
;
547 dict
<const RTLIL::Module
*, SigMap
> sigmaps
;
548 pool
<const RTLIL::Wire
*> edge_wires
;
549 dict
<RTLIL::SigBit
, RTLIL::SyncType
> edge_types
;
550 pool
<const RTLIL::Memory
*> writable_memories
;
551 dict
<const RTLIL::Cell
*, pool
<const RTLIL::Cell
*>> transparent_for
;
552 dict
<const RTLIL::Wire
*, FlowGraph::Node
> elided_wires
;
553 dict
<const RTLIL::Module
*, std::vector
<FlowGraph::Node
>> schedule
;
554 pool
<const RTLIL::Wire
*> unbuffered_wires
;
555 pool
<const RTLIL::Wire
*> localized_wires
;
556 dict
<const RTLIL::Wire
*, const RTLIL::Wire
*> debug_alias_wires
;
557 dict
<const RTLIL::Wire
*, RTLIL::Const
> debug_const_wires
;
558 dict
<RTLIL::SigBit
, bool> bit_has_state
;
559 dict
<const RTLIL::Module
*, pool
<std::string
>> blackbox_specializations
;
560 dict
<const RTLIL::Module
*, bool> eval_converges
;
566 indent
.resize(indent
.size() - 1);
569 // RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
570 // because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
571 // identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
572 // in readable identifiers, does not depend on an up-to-date list of C++ keywords, and is easy to apply. Its rules:
573 // 1. All generated identifiers start with `_`.
574 // 1a. Generated identifiers for public names (beginning with `\`) start with `p_`.
575 // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
576 // 2. An underscore is escaped with another underscore, i.e. `__`.
577 // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
578 std::string
mangle_name(const RTLIL::IdString
&name
)
582 for (char c
: name
.str()) {
594 } else if (c
== '_') {
597 char l
= c
& 0xf, h
= (c
>> 4) & 0xf;
599 mangled
+= (h
< 10 ? '0' + h
: 'a' + h
- 10);
600 mangled
+= (l
< 10 ? '0' + l
: 'a' + l
- 10);
608 std::string
mangle_module_name(const RTLIL::IdString
&name
, bool is_blackbox
= false)
612 return "bb_" + mangle_name(name
);
613 return mangle_name(name
);
616 std::string
mangle_memory_name(const RTLIL::IdString
&name
)
618 // Class member namespace.
619 return "memory_" + mangle_name(name
);
622 std::string
mangle_cell_name(const RTLIL::IdString
&name
)
624 // Class member namespace.
625 return "cell_" + mangle_name(name
);
628 std::string
mangle_wire_name(const RTLIL::IdString
&name
)
630 // Class member namespace.
631 return mangle_name(name
);
634 std::string
mangle(const RTLIL::Module
*module
)
636 return mangle_module_name(module
->name
, /*is_blackbox=*/module
->get_bool_attribute(ID(cxxrtl_blackbox
)));
639 std::string
mangle(const RTLIL::Memory
*memory
)
641 return mangle_memory_name(memory
->name
);
644 std::string
mangle(const RTLIL::Cell
*cell
)
646 return mangle_cell_name(cell
->name
);
649 std::string
mangle(const RTLIL::Wire
*wire
)
651 return mangle_wire_name(wire
->name
);
654 std::string
mangle(RTLIL::SigBit sigbit
)
656 log_assert(sigbit
.wire
!= NULL
);
657 if (sigbit
.wire
->width
== 1)
658 return mangle(sigbit
.wire
);
659 return mangle(sigbit
.wire
) + "_" + std::to_string(sigbit
.offset
);
662 std::vector
<std::string
> template_param_names(const RTLIL::Module
*module
)
664 if (!module
->has_attribute(ID(cxxrtl_template
)))
667 if (module
->attributes
.at(ID(cxxrtl_template
)).flags
!= RTLIL::CONST_FLAG_STRING
)
668 log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module
));
670 std::vector
<std::string
> param_names
= split_by(module
->get_string_attribute(ID(cxxrtl_template
)), " \t");
671 for (const auto ¶m_name
: param_names
) {
672 // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
673 // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
674 // in both Verilog and C++, anyway.)
675 if (!isupper(param_name
[0]))
676 log_cmd_error("Attribute `cxxrtl_template' of module `%s' includes a parameter `%s', "
677 "which does not start with an uppercase letter.\n",
678 log_id(module
), param_name
.c_str());
683 std::string
template_params(const RTLIL::Module
*module
, bool is_decl
)
685 std::vector
<std::string
> param_names
= template_param_names(module
);
686 if (param_names
.empty())
689 std::string params
= "<";
691 for (const auto ¶m_name
: param_names
) {
697 params
+= param_name
;
703 std::string
template_args(const RTLIL::Cell
*cell
)
705 RTLIL::Module
*cell_module
= cell
->module
->design
->module(cell
->type
);
706 log_assert(cell_module
!= nullptr);
707 if (!cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
)))
710 std::vector
<std::string
> param_names
= template_param_names(cell_module
);
711 if (param_names
.empty())
714 std::string params
= "<";
716 for (const auto ¶m_name
: param_names
) {
720 params
+= "/*" + param_name
+ "=*/";
721 RTLIL::IdString id_param_name
= '\\' + param_name
;
722 if (!cell
->hasParam(id_param_name
))
723 log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
724 log_id(cell
->module
), log_id(cell
), param_name
.c_str(), log_id(cell_module
));
725 RTLIL::Const param_value
= cell
->getParam(id_param_name
);
726 if (((param_value
.flags
& ~RTLIL::CONST_FLAG_SIGNED
) != 0) || param_value
.as_int() < 0)
727 log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
728 "is not a positive integer.\n",
729 param_name
.c_str(), log_id(cell
->module
), log_id(cell
), log_id(cell_module
));
730 params
+= std::to_string(cell
->getParam(id_param_name
).as_int());
736 std::string
fresh_temporary()
738 return stringf("tmp_%d", temporary
++);
741 void dump_attrs(const RTLIL::AttrObject
*object
)
743 for (auto attr
: object
->attributes
) {
744 f
<< indent
<< "// " << attr
.first
.str() << ": ";
745 if (attr
.second
.flags
& RTLIL::CONST_FLAG_STRING
) {
746 f
<< attr
.second
.decode_string();
748 f
<< attr
.second
.as_int(/*is_signed=*/attr
.second
.flags
& RTLIL::CONST_FLAG_SIGNED
);
754 void dump_const_init(const RTLIL::Const
&data
, int width
, int offset
= 0, bool fixed_width
= false)
756 const int CHUNK_SIZE
= 32;
759 int chunk_width
= min(width
, CHUNK_SIZE
);
760 uint32_t chunk
= data
.extract(offset
, chunk_width
).as_int();
762 f
<< stringf("0x%.*xu", (3 + chunk_width
) / 4, chunk
);
764 f
<< stringf("%#xu", chunk
);
765 if (width
> CHUNK_SIZE
)
767 offset
+= CHUNK_SIZE
;
773 void dump_const_init(const RTLIL::Const
&data
)
775 dump_const_init(data
, data
.size());
778 void dump_const(const RTLIL::Const
&data
, int width
, int offset
= 0, bool fixed_width
= false)
780 f
<< "value<" << width
<< ">";
781 dump_const_init(data
, width
, offset
, fixed_width
);
784 void dump_const(const RTLIL::Const
&data
)
786 dump_const(data
, data
.size());
789 bool dump_sigchunk(const RTLIL::SigChunk
&chunk
, bool is_lhs
)
791 if (chunk
.wire
== NULL
) {
792 dump_const(chunk
.data
, chunk
.width
, chunk
.offset
);
795 if (elided_wires
.count(chunk
.wire
)) {
797 const FlowGraph::Node
&node
= elided_wires
[chunk
.wire
];
799 case FlowGraph::Node::Type::CONNECT
:
800 dump_connect_elided(node
.connect
);
802 case FlowGraph::Node::Type::CELL_EVAL
:
803 log_assert(is_elidable_cell(node
.cell
->type
));
804 dump_cell_elided(node
.cell
);
809 } else if (unbuffered_wires
[chunk
.wire
]) {
810 f
<< mangle(chunk
.wire
);
812 f
<< mangle(chunk
.wire
) << (is_lhs
? ".next" : ".curr");
814 if (chunk
.width
== chunk
.wire
->width
&& chunk
.offset
== 0)
816 else if (chunk
.width
== 1)
817 f
<< ".slice<" << chunk
.offset
<< ">()";
819 f
<< ".slice<" << chunk
.offset
+chunk
.width
-1 << "," << chunk
.offset
<< ">()";
824 bool dump_sigspec(const RTLIL::SigSpec
&sig
, bool is_lhs
)
829 } else if (sig
.is_chunk()) {
830 return dump_sigchunk(sig
.as_chunk(), is_lhs
);
832 dump_sigchunk(*sig
.chunks().rbegin(), is_lhs
);
833 for (auto it
= sig
.chunks().rbegin() + 1; it
!= sig
.chunks().rend(); ++it
) {
835 dump_sigchunk(*it
, is_lhs
);
842 void dump_sigspec_lhs(const RTLIL::SigSpec
&sig
)
844 dump_sigspec(sig
, /*is_lhs=*/true);
847 void dump_sigspec_rhs(const RTLIL::SigSpec
&sig
)
849 // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`,
850 // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit
851 // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit
852 // type conversion, but only if the expression needs it.
853 bool is_complex
= dump_sigspec(sig
, /*is_lhs=*/false);
858 void collect_sigspec_rhs(const RTLIL::SigSpec
&sig
, std::vector
<RTLIL::IdString
> &cells
)
860 for (auto chunk
: sig
.chunks()) {
861 if (!chunk
.wire
|| !elided_wires
.count(chunk
.wire
))
864 const FlowGraph::Node
&node
= elided_wires
[chunk
.wire
];
866 case FlowGraph::Node::Type::CONNECT
:
867 collect_connect(node
.connect
, cells
);
869 case FlowGraph::Node::Type::CELL_EVAL
:
870 collect_cell_eval(node
.cell
, cells
);
878 void dump_connect_elided(const RTLIL::SigSig
&conn
)
880 dump_sigspec_rhs(conn
.second
);
883 bool is_connect_elided(const RTLIL::SigSig
&conn
)
885 return conn
.first
.is_wire() && elided_wires
.count(conn
.first
.as_wire());
888 void collect_connect(const RTLIL::SigSig
&conn
, std::vector
<RTLIL::IdString
> &cells
)
890 if (!is_connect_elided(conn
))
893 collect_sigspec_rhs(conn
.second
, cells
);
896 void dump_connect(const RTLIL::SigSig
&conn
)
898 if (is_connect_elided(conn
))
901 f
<< indent
<< "// connection\n";
903 dump_sigspec_lhs(conn
.first
);
905 dump_connect_elided(conn
);
909 void dump_cell_sync(const RTLIL::Cell
*cell
)
911 const char *access
= is_cxxrtl_blackbox_cell(cell
) ? "->" : ".";
912 f
<< indent
<< "// cell " << cell
->name
.str() << " syncs\n";
913 for (auto conn
: cell
->connections())
914 if (cell
->output(conn
.first
))
915 if (is_cxxrtl_sync_port(cell
, conn
.first
)) {
917 dump_sigspec_lhs(conn
.second
);
918 f
<< " = " << mangle(cell
) << access
<< mangle_wire_name(conn
.first
) << ".curr;\n";
922 void dump_cell_elided(const RTLIL::Cell
*cell
)
925 if (is_unary_cell(cell
->type
)) {
926 f
<< cell
->type
.substr(1);
927 if (is_extending_cell(cell
->type
))
928 f
<< '_' << (cell
->getParam(ID::A_SIGNED
).as_bool() ? 's' : 'u');
929 f
<< "<" << cell
->getParam(ID::Y_WIDTH
).as_int() << ">(";
930 dump_sigspec_rhs(cell
->getPort(ID::A
));
933 } else if (is_binary_cell(cell
->type
)) {
934 f
<< cell
->type
.substr(1);
935 if (is_extending_cell(cell
->type
))
936 f
<< '_' << (cell
->getParam(ID::A_SIGNED
).as_bool() ? 's' : 'u') <<
937 (cell
->getParam(ID::B_SIGNED
).as_bool() ? 's' : 'u');
938 f
<< "<" << cell
->getParam(ID::Y_WIDTH
).as_int() << ">(";
939 dump_sigspec_rhs(cell
->getPort(ID::A
));
941 dump_sigspec_rhs(cell
->getPort(ID::B
));
944 } else if (cell
->type
== ID($mux
)) {
946 dump_sigspec_rhs(cell
->getPort(ID::S
));
948 dump_sigspec_rhs(cell
->getPort(ID::B
));
950 dump_sigspec_rhs(cell
->getPort(ID::A
));
952 // Parallel (one-hot) muxes
953 } else if (cell
->type
== ID($pmux
)) {
954 int width
= cell
->getParam(ID::WIDTH
).as_int();
955 int s_width
= cell
->getParam(ID::S_WIDTH
).as_int();
956 for (int part
= 0; part
< s_width
; part
++) {
958 dump_sigspec_rhs(cell
->getPort(ID::S
).extract(part
));
960 dump_sigspec_rhs(cell
->getPort(ID::B
).extract(part
* width
, width
));
963 dump_sigspec_rhs(cell
->getPort(ID::A
));
964 for (int part
= 0; part
< s_width
; part
++) {
968 } else if (cell
->type
== ID($concat
)) {
969 dump_sigspec_rhs(cell
->getPort(ID::B
));
971 dump_sigspec_rhs(cell
->getPort(ID::A
));
974 } else if (cell
->type
== ID($slice
)) {
975 dump_sigspec_rhs(cell
->getPort(ID::A
));
977 f
<< cell
->getParam(ID::OFFSET
).as_int() + cell
->getParam(ID::Y_WIDTH
).as_int() - 1;
979 f
<< cell
->getParam(ID::OFFSET
).as_int();
986 bool is_cell_elided(const RTLIL::Cell
*cell
)
988 return is_elidable_cell(cell
->type
) && cell
->hasPort(ID::Y
) && cell
->getPort(ID::Y
).is_wire() &&
989 elided_wires
.count(cell
->getPort(ID::Y
).as_wire());
992 void collect_cell_eval(const RTLIL::Cell
*cell
, std::vector
<RTLIL::IdString
> &cells
)
994 if (!is_cell_elided(cell
))
997 cells
.push_back(cell
->name
);
998 for (auto port
: cell
->connections())
999 if (port
.first
!= ID::Y
)
1000 collect_sigspec_rhs(port
.second
, cells
);
1003 void dump_cell_eval(const RTLIL::Cell
*cell
)
1005 if (is_cell_elided(cell
))
1007 if (cell
->type
== ID($meminit
))
1008 return; // Handled elsewhere.
1010 std::vector
<RTLIL::IdString
> elided_cells
;
1011 if (is_elidable_cell(cell
->type
)) {
1012 for (auto port
: cell
->connections())
1013 if (port
.first
!= ID::Y
)
1014 collect_sigspec_rhs(port
.second
, elided_cells
);
1016 if (elided_cells
.empty()) {
1018 f
<< indent
<< "// cell " << cell
->name
.str() << "\n";
1020 f
<< indent
<< "// cells";
1021 for (auto elided_cell
: elided_cells
)
1022 f
<< " " << elided_cell
.str();
1027 if (is_elidable_cell(cell
->type
)) {
1029 dump_sigspec_lhs(cell
->getPort(ID::Y
));
1031 dump_cell_elided(cell
);
1034 } else if (is_ff_cell(cell
->type
)) {
1035 if (cell
->hasPort(ID::CLK
) && cell
->getPort(ID::CLK
).is_wire()) {
1036 // Edge-sensitive logic
1037 RTLIL::SigBit clk_bit
= cell
->getPort(ID::CLK
)[0];
1038 clk_bit
= sigmaps
[clk_bit
.wire
->module
](clk_bit
);
1040 f
<< indent
<< "if (" << (cell
->getParam(ID::CLK_POLARITY
).as_bool() ? "posedge_" : "negedge_")
1041 << mangle(clk_bit
) << ") {\n";
1043 f
<< indent
<< "if (false) {\n";
1046 if (cell
->hasPort(ID::EN
)) {
1047 f
<< indent
<< "if (";
1048 dump_sigspec_rhs(cell
->getPort(ID::EN
));
1049 f
<< " == value<1> {" << cell
->getParam(ID::EN_POLARITY
).as_bool() << "u}) {\n";
1053 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1055 dump_sigspec_rhs(cell
->getPort(ID::D
));
1057 if (cell
->hasPort(ID::EN
) && cell
->type
!= ID($sdffce
)) {
1059 f
<< indent
<< "}\n";
1061 if (cell
->hasPort(ID::SRST
)) {
1062 f
<< indent
<< "if (";
1063 dump_sigspec_rhs(cell
->getPort(ID::SRST
));
1064 f
<< " == value<1> {" << cell
->getParam(ID::SRST_POLARITY
).as_bool() << "u}) {\n";
1067 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1069 dump_const(cell
->getParam(ID::SRST_VALUE
));
1072 f
<< indent
<< "}\n";
1074 if (cell
->hasPort(ID::EN
) && cell
->type
== ID($sdffce
)) {
1076 f
<< indent
<< "}\n";
1079 f
<< indent
<< "}\n";
1080 } else if (cell
->hasPort(ID::EN
)) {
1081 // Level-sensitive logic
1082 f
<< indent
<< "if (";
1083 dump_sigspec_rhs(cell
->getPort(ID::EN
));
1084 f
<< " == value<1> {" << cell
->getParam(ID::EN_POLARITY
).as_bool() << "u}) {\n";
1087 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1089 dump_sigspec_rhs(cell
->getPort(ID::D
));
1092 f
<< indent
<< "}\n";
1094 if (cell
->hasPort(ID::ARST
)) {
1095 // Asynchronous reset (entire coarse cell at once)
1096 f
<< indent
<< "if (";
1097 dump_sigspec_rhs(cell
->getPort(ID::ARST
));
1098 f
<< " == value<1> {" << cell
->getParam(ID::ARST_POLARITY
).as_bool() << "u}) {\n";
1101 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1103 dump_const(cell
->getParam(ID::ARST_VALUE
));
1106 f
<< indent
<< "}\n";
1108 if (cell
->hasPort(ID::SET
)) {
1109 // Asynchronous set (for individual bits)
1111 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1113 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1115 dump_const(RTLIL::Const(RTLIL::S1
, cell
->getParam(ID::WIDTH
).as_int()));
1117 dump_sigspec_rhs(cell
->getPort(ID::SET
));
1118 f
<< (cell
->getParam(ID::SET_POLARITY
).as_bool() ? "" : ".bit_not()") << ");\n";
1120 if (cell
->hasPort(ID::CLR
)) {
1121 // Asynchronous clear (for individual bits; priority over set)
1123 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1125 dump_sigspec_lhs(cell
->getPort(ID::Q
));
1127 dump_const(RTLIL::Const(RTLIL::S0
, cell
->getParam(ID::WIDTH
).as_int()));
1129 dump_sigspec_rhs(cell
->getPort(ID::CLR
));
1130 f
<< (cell
->getParam(ID::CLR_POLARITY
).as_bool() ? "" : ".bit_not()") << ");\n";
1133 } else if (cell
->type
.in(ID($memrd
), ID($memwr
))) {
1134 if (cell
->getParam(ID::CLK_ENABLE
).as_bool()) {
1135 RTLIL::SigBit clk_bit
= cell
->getPort(ID::CLK
)[0];
1136 clk_bit
= sigmaps
[clk_bit
.wire
->module
](clk_bit
);
1138 f
<< indent
<< "if (" << (cell
->getParam(ID::CLK_POLARITY
).as_bool() ? "posedge_" : "negedge_")
1139 << mangle(clk_bit
) << ") {\n";
1141 f
<< indent
<< "if (false) {\n";
1145 RTLIL::Memory
*memory
= cell
->module
->memories
[cell
->getParam(ID::MEMID
).decode_string()];
1146 std::string valid_index_temp
= fresh_temporary();
1147 f
<< indent
<< "auto " << valid_index_temp
<< " = memory_index(";
1148 dump_sigspec_rhs(cell
->getPort(ID::ADDR
));
1149 f
<< ", " << memory
->start_offset
<< ", " << memory
->size
<< ");\n";
1150 if (cell
->type
== ID($memrd
)) {
1151 bool has_enable
= cell
->getParam(ID::CLK_ENABLE
).as_bool() && !cell
->getPort(ID::EN
).is_fully_ones();
1153 f
<< indent
<< "if (";
1154 dump_sigspec_rhs(cell
->getPort(ID::EN
));
1158 // The generated code has two bounds checks; one in an assertion, and another that guards the read.
1159 // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
1160 // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DNDEBUG not
1161 // just for release builds, but also to make sure the simulator (which is presumably embedded in some
1162 // larger program) will never crash the code that calls into it.
1164 // If assertions are disabled, out of bounds reads are defined to return zero.
1165 f
<< indent
<< "CXXRTL_ASSERT(" << valid_index_temp
<< ".valid && \"out of bounds read\");\n";
1166 f
<< indent
<< "if(" << valid_index_temp
<< ".valid) {\n";
1168 if (writable_memories
[memory
]) {
1169 std::string lhs_temp
= fresh_temporary();
1170 f
<< indent
<< "value<" << memory
->width
<< "> " << lhs_temp
<< " = "
1171 << mangle(memory
) << "[" << valid_index_temp
<< ".index];\n";
1172 std::vector
<const RTLIL::Cell
*> memwr_cells(transparent_for
[cell
].begin(), transparent_for
[cell
].end());
1173 if (!memwr_cells
.empty()) {
1174 std::string addr_temp
= fresh_temporary();
1175 f
<< indent
<< "const value<" << cell
->getPort(ID::ADDR
).size() << "> &" << addr_temp
<< " = ";
1176 dump_sigspec_rhs(cell
->getPort(ID::ADDR
));
1178 std::sort(memwr_cells
.begin(), memwr_cells
.end(),
1179 [](const RTLIL::Cell
*a
, const RTLIL::Cell
*b
) {
1180 return a
->getParam(ID::PRIORITY
).as_int() < b
->getParam(ID::PRIORITY
).as_int();
1182 for (auto memwr_cell
: memwr_cells
) {
1183 f
<< indent
<< "if (" << addr_temp
<< " == ";
1184 dump_sigspec_rhs(memwr_cell
->getPort(ID::ADDR
));
1187 f
<< indent
<< lhs_temp
<< " = " << lhs_temp
;
1189 dump_sigspec_rhs(memwr_cell
->getPort(ID::DATA
));
1191 dump_sigspec_rhs(memwr_cell
->getPort(ID::EN
));
1194 f
<< indent
<< "}\n";
1198 dump_sigspec_lhs(cell
->getPort(ID::DATA
));
1199 f
<< " = " << lhs_temp
<< ";\n";
1202 dump_sigspec_lhs(cell
->getPort(ID::DATA
));
1203 f
<< " = " << mangle(memory
) << "[" << valid_index_temp
<< ".index];\n";
1206 f
<< indent
<< "} else {\n";
1209 dump_sigspec_lhs(cell
->getPort(ID::DATA
));
1210 f
<< " = value<" << memory
->width
<< "> {};\n";
1212 f
<< indent
<< "}\n";
1215 f
<< indent
<< "}\n";
1217 } else /*if (cell->type == ID($memwr))*/ {
1218 log_assert(writable_memories
[memory
]);
1219 // See above for rationale of having both the assert and the condition.
1221 // If assertions are disabled, out of bounds writes are defined to do nothing.
1222 f
<< indent
<< "CXXRTL_ASSERT(" << valid_index_temp
<< ".valid && \"out of bounds write\");\n";
1223 f
<< indent
<< "if (" << valid_index_temp
<< ".valid) {\n";
1225 f
<< indent
<< mangle(memory
) << ".update(" << valid_index_temp
<< ".index, ";
1226 dump_sigspec_rhs(cell
->getPort(ID::DATA
));
1228 dump_sigspec_rhs(cell
->getPort(ID::EN
));
1229 f
<< ", " << cell
->getParam(ID::PRIORITY
).as_int() << ");\n";
1231 f
<< indent
<< "}\n";
1233 if (cell
->getParam(ID::CLK_ENABLE
).as_bool()) {
1235 f
<< indent
<< "}\n";
1238 } else if (is_internal_cell(cell
->type
)) {
1239 log_cmd_error("Unsupported internal cell `%s'.\n", cell
->type
.c_str());
1242 log_assert(cell
->known());
1243 bool buffered_inputs
= false;
1244 const char *access
= is_cxxrtl_blackbox_cell(cell
) ? "->" : ".";
1245 for (auto conn
: cell
->connections())
1246 if (cell
->input(conn
.first
)) {
1247 RTLIL::Module
*cell_module
= cell
->module
->design
->module(cell
->type
);
1248 log_assert(cell_module
!= nullptr && cell_module
->wire(conn
.first
) && conn
.second
.is_wire());
1249 RTLIL::Wire
*cell_module_wire
= cell_module
->wire(conn
.first
);
1250 f
<< indent
<< mangle(cell
) << access
<< mangle_wire_name(conn
.first
);
1251 if (!is_cxxrtl_blackbox_cell(cell
) && !unbuffered_wires
[cell_module_wire
]) {
1252 buffered_inputs
= true;
1256 dump_sigspec_rhs(conn
.second
);
1258 if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
1259 // Until we have proper clock tree detection, this really awful hack that opportunistically
1260 // propagates prev_* values for clocks can be used to estimate how much faster a design could
1261 // be if only one clock edge was simulated by replacing:
1262 // top.p_clk = value<1>{0u}; top.step();
1263 // top.p_clk = value<1>{1u}; top.step();
1265 // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
1266 // Don't rely on this; it will be removed without warning.
1267 if (edge_wires
[conn
.second
.as_wire()] && edge_wires
[cell_module_wire
]) {
1268 f
<< indent
<< mangle(cell
) << access
<< "prev_" << mangle(cell_module_wire
) << " = ";
1269 f
<< "prev_" << mangle(conn
.second
.as_wire()) << ";\n";
1273 auto assign_from_outputs
= [&](bool cell_converged
) {
1274 for (auto conn
: cell
->connections()) {
1275 if (cell
->output(conn
.first
)) {
1276 if (conn
.second
.empty())
1277 continue; // ignore disconnected ports
1278 if (is_cxxrtl_sync_port(cell
, conn
.first
))
1279 continue; // fully sync ports are handled in CELL_SYNC nodes
1281 dump_sigspec_lhs(conn
.second
);
1282 f
<< " = " << mangle(cell
) << access
<< mangle_wire_name(conn
.first
);
1283 // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
1284 // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
1285 // this optimization is valid, consider that, since the cell converged within one cycle, it would not
1286 // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
1287 // and consider the fate of the localized wires that used to be output ports.)
1289 // It is not possible to know apriori whether the cell (which may be late bound) will converge immediately.
1290 // Because of this, the choice between using .curr (appropriate for buffered outputs) and .next (appropriate
1291 // for unbuffered outputs) is made at runtime.
1292 if (cell_converged
&& is_cxxrtl_comb_port(cell
, conn
.first
))
1299 if (buffered_inputs
) {
1300 // If we have any buffered inputs, there's no chance of converging immediately.
1301 f
<< indent
<< mangle(cell
) << access
<< "eval();\n";
1302 f
<< indent
<< "converged = false;\n";
1303 assign_from_outputs(/*cell_converged=*/false);
1305 f
<< indent
<< "if (" << mangle(cell
) << access
<< "eval()) {\n";
1307 assign_from_outputs(/*cell_converged=*/true);
1309 f
<< indent
<< "} else {\n";
1311 f
<< indent
<< "converged = false;\n";
1312 assign_from_outputs(/*cell_converged=*/false);
1314 f
<< indent
<< "}\n";
1319 void dump_assign(const RTLIL::SigSig
&sigsig
)
1322 dump_sigspec_lhs(sigsig
.first
);
1324 dump_sigspec_rhs(sigsig
.second
);
1328 void dump_case_rule(const RTLIL::CaseRule
*rule
)
1330 for (auto action
: rule
->actions
)
1331 dump_assign(action
);
1332 for (auto switch_
: rule
->switches
)
1333 dump_switch_rule(switch_
);
1336 void dump_switch_rule(const RTLIL::SwitchRule
*rule
)
1338 // The switch attributes are printed before the switch condition is captured.
1340 std::string signal_temp
= fresh_temporary();
1341 f
<< indent
<< "const value<" << rule
->signal
.size() << "> &" << signal_temp
<< " = ";
1342 dump_sigspec(rule
->signal
, /*is_lhs=*/false);
1346 for (auto case_
: rule
->cases
) {
1347 // The case attributes (for nested cases) are printed before the if/else if/else statement.
1353 if (!case_
->compare
.empty()) {
1356 for (auto &compare
: case_
->compare
) {
1360 if (compare
.is_fully_def()) {
1361 f
<< signal_temp
<< " == ";
1362 dump_sigspec(compare
, /*is_lhs=*/false);
1363 } else if (compare
.is_fully_const()) {
1364 RTLIL::Const compare_mask
, compare_value
;
1365 for (auto bit
: compare
.as_const()) {
1369 compare_mask
.bits
.push_back(RTLIL::S1
);
1370 compare_value
.bits
.push_back(bit
);
1376 compare_mask
.bits
.push_back(RTLIL::S0
);
1377 compare_value
.bits
.push_back(RTLIL::S0
);
1384 f
<< "and_uu<" << compare
.size() << ">(" << signal_temp
<< ", ";
1385 dump_const(compare_mask
);
1387 dump_const(compare_value
);
1396 dump_case_rule(case_
);
1399 f
<< indent
<< "}\n";
1402 void dump_process(const RTLIL::Process
*proc
)
1405 f
<< indent
<< "// process " << proc
->name
.str() << "\n";
1406 // The case attributes (for root case) are always empty.
1407 log_assert(proc
->root_case
.attributes
.empty());
1408 dump_case_rule(&proc
->root_case
);
1409 for (auto sync
: proc
->syncs
) {
1410 RTLIL::SigBit sync_bit
;
1411 if (!sync
->signal
.empty()) {
1412 sync_bit
= sync
->signal
[0];
1413 sync_bit
= sigmaps
[sync_bit
.wire
->module
](sync_bit
);
1416 pool
<std::string
> events
;
1417 switch (sync
->type
) {
1419 log_assert(sync_bit
.wire
!= nullptr);
1420 events
.insert("posedge_" + mangle(sync_bit
));
1423 log_assert(sync_bit
.wire
!= nullptr);
1424 events
.insert("negedge_" + mangle(sync_bit
));
1427 log_assert(sync_bit
.wire
!= nullptr);
1428 events
.insert("posedge_" + mangle(sync_bit
));
1429 events
.insert("negedge_" + mangle(sync_bit
));
1433 events
.insert("true");
1442 if (!events
.empty()) {
1443 f
<< indent
<< "if (";
1445 for (auto &event
: events
) {
1453 for (auto action
: sync
->actions
)
1454 dump_assign(action
);
1456 f
<< indent
<< "}\n";
1461 void dump_wire(const RTLIL::Wire
*wire
, bool is_local_context
)
1463 if (elided_wires
.count(wire
))
1466 if (localized_wires
[wire
] && is_local_context
) {
1468 f
<< indent
<< "value<" << wire
->width
<< "> " << mangle(wire
) << ";\n";
1470 if (!localized_wires
[wire
] && !is_local_context
) {
1472 if (wire
->module
->has_attribute(ID(cxxrtl_blackbox
)) && wire
->has_attribute(ID(cxxrtl_width
))) {
1473 width
= wire
->get_string_attribute(ID(cxxrtl_width
));
1475 width
= std::to_string(wire
->width
);
1480 if (wire
->port_input
&& wire
->port_output
)
1482 else if (wire
->port_input
)
1484 else if (wire
->port_output
)
1486 f
<< (unbuffered_wires
[wire
] ? "value" : "wire") << "<" << width
<< "> " << mangle(wire
);
1487 if (wire
->has_attribute(ID::init
)) {
1489 dump_const_init(wire
->attributes
.at(ID::init
));
1492 if (edge_wires
[wire
]) {
1493 if (unbuffered_wires
[wire
]) {
1494 f
<< indent
<< "value<" << width
<< "> prev_" << mangle(wire
);
1495 if (wire
->has_attribute(ID::init
)) {
1497 dump_const_init(wire
->attributes
.at(ID::init
));
1501 for (auto edge_type
: edge_types
) {
1502 if (edge_type
.first
.wire
== wire
) {
1503 std::string prev
, next
;
1504 if (unbuffered_wires
[wire
]) {
1505 prev
= "prev_" + mangle(edge_type
.first
.wire
);
1506 next
= mangle(edge_type
.first
.wire
);
1508 prev
= mangle(edge_type
.first
.wire
) + ".curr";
1509 next
= mangle(edge_type
.first
.wire
) + ".next";
1511 prev
+= ".slice<" + std::to_string(edge_type
.first
.offset
) + ">().val()";
1512 next
+= ".slice<" + std::to_string(edge_type
.first
.offset
) + ">().val()";
1513 if (edge_type
.second
!= RTLIL::STn
) {
1514 f
<< indent
<< "bool posedge_" << mangle(edge_type
.first
) << "() const {\n";
1516 f
<< indent
<< "return !" << prev
<< " && " << next
<< ";\n";
1518 f
<< indent
<< "}\n";
1520 if (edge_type
.second
!= RTLIL::STp
) {
1521 f
<< indent
<< "bool negedge_" << mangle(edge_type
.first
) << "() const {\n";
1523 f
<< indent
<< "return " << prev
<< " && !" << next
<< ";\n";
1525 f
<< indent
<< "}\n";
1533 void dump_memory(RTLIL::Module
*module
, const RTLIL::Memory
*memory
)
1535 vector
<const RTLIL::Cell
*> init_cells
;
1536 for (auto cell
: module
->cells())
1537 if (cell
->type
== ID($meminit
) && cell
->getParam(ID::MEMID
).decode_string() == memory
->name
.str())
1538 init_cells
.push_back(cell
);
1540 std::sort(init_cells
.begin(), init_cells
.end(), [](const RTLIL::Cell
*a
, const RTLIL::Cell
*b
) {
1541 int a_addr
= a
->getPort(ID::ADDR
).as_int(), b_addr
= b
->getPort(ID::ADDR
).as_int();
1542 int a_prio
= a
->getParam(ID::PRIORITY
).as_int(), b_prio
= b
->getParam(ID::PRIORITY
).as_int();
1543 return a_prio
> b_prio
|| (a_prio
== b_prio
&& a_addr
< b_addr
);
1547 f
<< indent
<< "memory<" << memory
->width
<< "> " << mangle(memory
)
1548 << " { " << memory
->size
<< "u";
1549 if (init_cells
.empty()) {
1554 for (auto cell
: init_cells
) {
1556 RTLIL::Const data
= cell
->getPort(ID::DATA
).as_const();
1557 size_t width
= cell
->getParam(ID::WIDTH
).as_int();
1558 size_t words
= cell
->getParam(ID::WORDS
).as_int();
1559 f
<< indent
<< "memory<" << memory
->width
<< ">::init<" << words
<< "> { "
1560 << stringf("%#x", cell
->getPort(ID::ADDR
).as_int()) << ", {";
1562 for (size_t n
= 0; n
< words
; n
++) {
1564 f
<< "\n" << indent
;
1567 dump_const(data
, width
, n
* width
, /*fixed_width=*/true);
1571 f
<< "\n" << indent
<< "}},\n";
1574 f
<< indent
<< "};\n";
1578 void dump_eval_method(RTLIL::Module
*module
)
1581 f
<< indent
<< "bool converged = " << (eval_converges
.at(module
) ? "true" : "false") << ";\n";
1582 if (!module
->get_bool_attribute(ID(cxxrtl_blackbox
))) {
1583 for (auto wire
: module
->wires()) {
1584 if (edge_wires
[wire
]) {
1585 for (auto edge_type
: edge_types
) {
1586 if (edge_type
.first
.wire
== wire
) {
1587 if (edge_type
.second
!= RTLIL::STn
) {
1588 f
<< indent
<< "bool posedge_" << mangle(edge_type
.first
) << " = ";
1589 f
<< "this->posedge_" << mangle(edge_type
.first
) << "();\n";
1591 if (edge_type
.second
!= RTLIL::STp
) {
1592 f
<< indent
<< "bool negedge_" << mangle(edge_type
.first
) << " = ";
1593 f
<< "this->negedge_" << mangle(edge_type
.first
) << "();\n";
1599 for (auto wire
: module
->wires())
1600 dump_wire(wire
, /*is_local_context=*/true);
1601 for (auto node
: schedule
[module
]) {
1602 switch (node
.type
) {
1603 case FlowGraph::Node::Type::CONNECT
:
1604 dump_connect(node
.connect
);
1606 case FlowGraph::Node::Type::CELL_SYNC
:
1607 dump_cell_sync(node
.cell
);
1609 case FlowGraph::Node::Type::CELL_EVAL
:
1610 dump_cell_eval(node
.cell
);
1612 case FlowGraph::Node::Type::PROCESS
:
1613 dump_process(node
.process
);
1618 f
<< indent
<< "return converged;\n";
1622 void dump_commit_method(RTLIL::Module
*module
)
1625 f
<< indent
<< "bool changed = false;\n";
1626 for (auto wire
: module
->wires()) {
1627 if (elided_wires
.count(wire
))
1629 if (unbuffered_wires
[wire
]) {
1630 if (edge_wires
[wire
])
1631 f
<< indent
<< "prev_" << mangle(wire
) << " = " << mangle(wire
) << ";\n";
1634 if (!module
->get_bool_attribute(ID(cxxrtl_blackbox
)) || wire
->port_id
!= 0)
1635 f
<< indent
<< "changed |= " << mangle(wire
) << ".commit();\n";
1637 if (!module
->get_bool_attribute(ID(cxxrtl_blackbox
))) {
1638 for (auto memory
: module
->memories
) {
1639 if (!writable_memories
[memory
.second
])
1641 f
<< indent
<< "changed |= " << mangle(memory
.second
) << ".commit();\n";
1643 for (auto cell
: module
->cells()) {
1644 if (is_internal_cell(cell
->type
))
1646 const char *access
= is_cxxrtl_blackbox_cell(cell
) ? "->" : ".";
1647 f
<< indent
<< "changed |= " << mangle(cell
) << access
<< "commit();\n";
1650 f
<< indent
<< "return changed;\n";
1654 void dump_debug_info_method(RTLIL::Module
*module
)
1656 size_t count_public_wires
= 0;
1657 size_t count_const_wires
= 0;
1658 size_t count_alias_wires
= 0;
1659 size_t count_member_wires
= 0;
1660 size_t count_skipped_wires
= 0;
1661 size_t count_driven_sync
= 0;
1662 size_t count_driven_comb
= 0;
1663 size_t count_undriven
= 0;
1664 size_t count_mixed_driver
= 0;
1666 f
<< indent
<< "assert(path.empty() || path[path.size() - 1] == ' ');\n";
1667 for (auto wire
: module
->wires()) {
1668 if (!wire
->name
.isPublic())
1670 if (module
->get_bool_attribute(ID(cxxrtl_blackbox
)) && (wire
->port_id
== 0))
1672 count_public_wires
++;
1673 if (debug_const_wires
.count(wire
)) {
1674 // Wire tied to a constant
1675 f
<< indent
<< "static const value<" << wire
->width
<< "> const_" << mangle(wire
) << " = ";
1676 dump_const(debug_const_wires
[wire
]);
1678 f
<< indent
<< "items.add(path + " << escape_cxx_string(get_hdl_name(wire
));
1679 f
<< ", debug_item(const_" << mangle(wire
) << ", ";
1680 f
<< wire
->start_offset
<< "));\n";
1681 count_const_wires
++;
1682 } else if (debug_alias_wires
.count(wire
)) {
1683 // Alias of a member wire
1684 f
<< indent
<< "items.add(path + " << escape_cxx_string(get_hdl_name(wire
));
1685 f
<< ", debug_item(debug_alias(), " << mangle(debug_alias_wires
[wire
]) << ", ";
1686 f
<< wire
->start_offset
<< "));\n";
1687 count_alias_wires
++;
1688 } else if (!localized_wires
.count(wire
)) {
1690 std::vector
<std::string
> flags
;
1692 if (wire
->port_input
&& wire
->port_output
)
1693 flags
.push_back("INOUT");
1694 else if (wire
->port_input
)
1695 flags
.push_back("INPUT");
1696 else if (wire
->port_output
)
1697 flags
.push_back("OUTPUT");
1699 bool has_driven_sync
= false;
1700 bool has_driven_comb
= false;
1701 bool has_undriven
= false;
1703 for (auto bit
: sig
.bits())
1704 if (!bit_has_state
.count(bit
))
1705 has_undriven
= true;
1706 else if (bit_has_state
[bit
])
1707 has_driven_sync
= true;
1709 has_driven_comb
= true;
1710 if (has_driven_sync
)
1711 flags
.push_back("DRIVEN_SYNC");
1712 if (has_driven_sync
&& !has_driven_comb
&& !has_undriven
)
1713 count_driven_sync
++;
1714 if (has_driven_comb
)
1715 flags
.push_back("DRIVEN_COMB");
1716 if (!has_driven_sync
&& has_driven_comb
&& !has_undriven
)
1717 count_driven_comb
++;
1719 flags
.push_back("UNDRIVEN");
1720 if (!has_driven_sync
&& !has_driven_comb
&& has_undriven
)
1722 if (has_driven_sync
+ has_driven_comb
+ has_undriven
> 1)
1723 count_mixed_driver
++;
1725 f
<< indent
<< "items.add(path + " << escape_cxx_string(get_hdl_name(wire
));
1726 f
<< ", debug_item(" << mangle(wire
) << ", ";
1727 f
<< wire
->start_offset
;
1729 for (auto flag
: flags
) {
1736 f
<< "debug_item::" << flag
;
1739 count_member_wires
++;
1741 count_skipped_wires
++;
1744 if (!module
->get_bool_attribute(ID(cxxrtl_blackbox
))) {
1745 for (auto &memory_it
: module
->memories
) {
1746 if (!memory_it
.first
.isPublic())
1748 f
<< indent
<< "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it
.second
));
1749 f
<< ", debug_item(" << mangle(memory_it
.second
) << ", ";
1750 f
<< memory_it
.second
->start_offset
<< "));\n";
1752 for (auto cell
: module
->cells()) {
1753 if (is_internal_cell(cell
->type
))
1755 const char *access
= is_cxxrtl_blackbox_cell(cell
) ? "->" : ".";
1756 f
<< indent
<< mangle(cell
) << access
<< "debug_info(items, ";
1757 f
<< "path + " << escape_cxx_string(get_hdl_name(cell
) + ' ') << ");\n";
1762 log_debug("Debug information statistics for module `%s':\n", log_id(module
));
1763 log_debug(" Public wires: %zu, of which:\n", count_public_wires
);
1764 log_debug(" Const wires: %zu\n", count_const_wires
);
1765 log_debug(" Alias wires: %zu\n", count_alias_wires
);
1766 log_debug(" Member wires: %zu, of which:\n", count_member_wires
);
1767 log_debug(" Driven sync: %zu\n", count_driven_sync
);
1768 log_debug(" Driven comb: %zu\n", count_driven_comb
);
1769 log_debug(" Undriven: %zu\n", count_undriven
);
1770 log_debug(" Mixed driver: %zu\n", count_mixed_driver
);
1771 log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires
);
1774 void dump_metadata_map(const dict
<RTLIL::IdString
, RTLIL::Const
> &metadata_map
)
1776 if (metadata_map
.empty()) {
1777 f
<< "metadata_map()";
1780 f
<< "metadata_map({\n";
1782 for (auto metadata_item
: metadata_map
) {
1783 if (!metadata_item
.first
.begins_with("\\"))
1785 f
<< indent
<< "{ " << escape_cxx_string(metadata_item
.first
.str().substr(1)) << ", ";
1786 if (metadata_item
.second
.flags
& RTLIL::CONST_FLAG_REAL
) {
1787 f
<< std::showpoint
<< std::stod(metadata_item
.second
.decode_string()) << std::noshowpoint
;
1788 } else if (metadata_item
.second
.flags
& RTLIL::CONST_FLAG_STRING
) {
1789 f
<< escape_cxx_string(metadata_item
.second
.decode_string());
1791 f
<< metadata_item
.second
.as_int(/*is_signed=*/metadata_item
.second
.flags
& RTLIL::CONST_FLAG_SIGNED
);
1792 if (!(metadata_item
.second
.flags
& RTLIL::CONST_FLAG_SIGNED
))
1798 f
<< indent
<< "})";
1801 void dump_module_intf(RTLIL::Module
*module
)
1804 if (module
->get_bool_attribute(ID(cxxrtl_blackbox
))) {
1805 if (module
->has_attribute(ID(cxxrtl_template
)))
1806 f
<< indent
<< "template" << template_params(module
, /*is_decl=*/true) << "\n";
1807 f
<< indent
<< "struct " << mangle(module
) << " : public module {\n";
1809 for (auto wire
: module
->wires()) {
1810 if (wire
->port_id
!= 0)
1811 dump_wire(wire
, /*is_local_context=*/false);
1814 f
<< indent
<< "bool eval() override {\n";
1815 dump_eval_method(module
);
1816 f
<< indent
<< "}\n";
1818 f
<< indent
<< "bool commit() override {\n";
1819 dump_commit_method(module
);
1820 f
<< indent
<< "}\n";
1823 f
<< indent
<< "void debug_info(debug_items &items, std::string path = \"\") override {\n";
1824 dump_debug_info_method(module
);
1825 f
<< indent
<< "}\n";
1828 f
<< indent
<< "static std::unique_ptr<" << mangle(module
);
1829 f
<< template_params(module
, /*is_decl=*/false) << "> ";
1830 f
<< "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1832 f
<< indent
<< "}; // struct " << mangle(module
) << "\n";
1834 if (blackbox_specializations
.count(module
)) {
1835 // If templated black boxes are used, the constructor of any module which includes the black box cell
1836 // (which calls the declared but not defined in the generated code `create` function) may only be used
1837 // if (a) the create function is defined in the same translation unit, or (b) the create function has
1838 // a forward-declared explicit specialization.
1840 // Option (b) makes it possible to have the generated code and the black box implementation in different
1841 // translation units, which is convenient. Of course, its downside is that black boxes must predefine
1842 // a specialization for every combination of parameters the generated code may use; but since the main
1843 // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
1844 // be very few such combinations anyway.
1845 for (auto specialization
: blackbox_specializations
[module
]) {
1846 f
<< indent
<< "template<>\n";
1847 f
<< indent
<< "std::unique_ptr<" << mangle(module
) << specialization
<< "> ";
1848 f
<< mangle(module
) << specialization
<< "::";
1849 f
<< "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
1854 f
<< indent
<< "struct " << mangle(module
) << " : public module {\n";
1856 for (auto wire
: module
->wires())
1857 dump_wire(wire
, /*is_local_context=*/false);
1859 bool has_memories
= false;
1860 for (auto memory
: module
->memories
) {
1861 dump_memory(module
, memory
.second
);
1862 has_memories
= true;
1866 bool has_cells
= false;
1867 for (auto cell
: module
->cells()) {
1868 if (is_internal_cell(cell
->type
))
1871 RTLIL::Module
*cell_module
= module
->design
->module(cell
->type
);
1872 log_assert(cell_module
!= nullptr);
1873 if (cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
))) {
1874 f
<< indent
<< "std::unique_ptr<" << mangle(cell_module
) << template_args(cell
) << "> ";
1875 f
<< mangle(cell
) << " = " << mangle(cell_module
) << template_args(cell
);
1876 f
<< "::create(" << escape_cxx_string(get_hdl_name(cell
)) << ", ";
1877 dump_metadata_map(cell
->parameters
);
1879 dump_metadata_map(cell
->attributes
);
1882 f
<< indent
<< mangle(cell_module
) << " " << mangle(cell
) << ";\n";
1888 f
<< indent
<< mangle(module
) << "() {}\n";
1890 f
<< indent
<< mangle(module
) << "(adopt, " << mangle(module
) << " other) :\n";
1892 for (auto cell
: module
->cells()) {
1893 if (is_internal_cell(cell
->type
))
1900 RTLIL::Module
*cell_module
= module
->design
->module(cell
->type
);
1901 if (cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
))) {
1902 f
<< indent
<< " " << mangle(cell
) << "(std::move(other." << mangle(cell
) << "))";
1904 f
<< indent
<< " " << mangle(cell
) << "(adopt {}, std::move(other." << mangle(cell
) << "))";
1909 for (auto cell
: module
->cells()) {
1910 if (is_internal_cell(cell
->type
))
1912 RTLIL::Module
*cell_module
= module
->design
->module(cell
->type
);
1913 if (cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
)))
1914 f
<< indent
<< mangle(cell
) << "->reset();\n";
1917 f
<< indent
<< "}\n";
1919 f
<< indent
<< mangle(module
) << "(adopt, " << mangle(module
) << " other) {}\n";
1922 f
<< indent
<< "void reset() override {\n";
1924 f
<< indent
<< "*this = " << mangle(module
) << "(adopt {}, std::move(*this));\n";
1926 f
<< indent
<< "}\n";
1928 f
<< indent
<< "bool eval() override;\n";
1929 f
<< indent
<< "bool commit() override;\n";
1931 f
<< indent
<< "void debug_info(debug_items &items, std::string path = \"\") override;\n";
1933 f
<< indent
<< "}; // struct " << mangle(module
) << "\n";
1938 void dump_module_impl(RTLIL::Module
*module
)
1940 if (module
->get_bool_attribute(ID(cxxrtl_blackbox
)))
1942 f
<< indent
<< "bool " << mangle(module
) << "::eval() {\n";
1943 dump_eval_method(module
);
1944 f
<< indent
<< "}\n";
1946 f
<< indent
<< "bool " << mangle(module
) << "::commit() {\n";
1947 dump_commit_method(module
);
1948 f
<< indent
<< "}\n";
1951 f
<< indent
<< "void " << mangle(module
) << "::debug_info(debug_items &items, std::string path) {\n";
1952 dump_debug_info_method(module
);
1953 f
<< indent
<< "}\n";
1958 void dump_design(RTLIL::Design
*design
)
1960 RTLIL::Module
*top_module
= nullptr;
1961 std::vector
<RTLIL::Module
*> modules
;
1962 TopoSort
<RTLIL::Module
*> topo_design
;
1963 for (auto module
: design
->modules()) {
1964 if (!design
->selected_module(module
))
1966 if (module
->get_bool_attribute(ID(cxxrtl_blackbox
)))
1967 modules
.push_back(module
); // cxxrtl blackboxes first
1968 if (module
->get_blackbox_attribute() || module
->get_bool_attribute(ID(cxxrtl_blackbox
)))
1970 if (module
->get_bool_attribute(ID::top
))
1971 top_module
= module
;
1973 topo_design
.node(module
);
1974 for (auto cell
: module
->cells()) {
1975 if (is_internal_cell(cell
->type
) || is_cxxrtl_blackbox_cell(cell
))
1977 RTLIL::Module
*cell_module
= design
->module(cell
->type
);
1978 log_assert(cell_module
!= nullptr);
1979 topo_design
.edge(cell_module
, module
);
1982 bool no_loops
= topo_design
.sort();
1983 log_assert(no_loops
);
1984 modules
.insert(modules
.end(), topo_design
.sorted
.begin(), topo_design
.sorted
.end());
1987 // The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
1988 std::string include_guard
= design_ns
+ "_header";
1989 std::transform(include_guard
.begin(), include_guard
.end(), include_guard
.begin(), ::toupper
);
1991 f
<< "#ifndef " << include_guard
<< "\n";
1992 f
<< "#define " << include_guard
<< "\n";
1994 if (top_module
!= nullptr && debug_info
) {
1995 f
<< "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
1997 f
<< "#ifdef __cplusplus\n";
1998 f
<< "extern \"C\" {\n";
2001 f
<< "cxxrtl_toplevel " << design_ns
<< "_create();\n";
2003 f
<< "#ifdef __cplusplus\n";
2008 f
<< "// The CXXRTL C API is not available because the design is built without debug information.\n";
2011 f
<< "#ifdef __cplusplus\n";
2013 f
<< "#include <backends/cxxrtl/cxxrtl.h>\n";
2015 f
<< "using namespace cxxrtl;\n";
2017 f
<< "namespace " << design_ns
<< " {\n";
2019 for (auto module
: modules
)
2020 dump_module_intf(module
);
2021 f
<< "} // namespace " << design_ns
<< "\n";
2023 f
<< "#endif // __cplusplus\n";
2026 *intf_f
<< f
.str(); f
.str("");
2030 f
<< "#include \"" << intf_filename
<< "\"\n";
2032 f
<< "#include <backends/cxxrtl/cxxrtl.h>\n";
2034 f
<< "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
2035 f
<< " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2036 f
<< "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
2039 f
<< "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
2040 f
<< "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
2043 f
<< "using namespace cxxrtl_yosys;\n";
2045 f
<< "namespace " << design_ns
<< " {\n";
2047 for (auto module
: modules
) {
2049 dump_module_intf(module
);
2050 dump_module_impl(module
);
2052 f
<< "} // namespace " << design_ns
<< "\n";
2054 if (top_module
!= nullptr && debug_info
) {
2055 f
<< "extern \"C\"\n";
2056 f
<< "cxxrtl_toplevel " << design_ns
<< "_create() {\n";
2058 std::string top_type
= design_ns
+ "::" + mangle(top_module
);
2059 f
<< indent
<< "return new _cxxrtl_toplevel { ";
2060 f
<< "std::unique_ptr<" << top_type
<< ">(new " + top_type
+ ")";
2066 *impl_f
<< f
.str(); f
.str("");
2069 // Edge-type sync rules require us to emit edge detectors, which require coordination between
2070 // eval and commit phases. To do this we need to collect them upfront.
2072 // Note that the simulator commit phase operates at wire granularity but edge-type sync rules
2073 // operate at wire bit granularity; it is possible to have code similar to:
2074 // wire [3:0] clocks;
2075 // always @(posedge clocks[0]) ...
2076 // To handle this we track edge sensitivity both for wires and wire bits.
2077 void register_edge_signal(SigMap
&sigmap
, RTLIL::SigSpec signal
, RTLIL::SyncType type
)
2079 signal
= sigmap(signal
);
2080 log_assert(signal
.is_wire() && signal
.is_bit());
2081 log_assert(type
== RTLIL::STp
|| type
== RTLIL::STn
|| type
== RTLIL::STe
);
2083 RTLIL::SigBit sigbit
= signal
[0];
2084 if (!edge_types
.count(sigbit
))
2085 edge_types
[sigbit
] = type
;
2086 else if (edge_types
[sigbit
] != type
)
2087 edge_types
[sigbit
] = RTLIL::STe
;
2088 edge_wires
.insert(signal
.as_wire());
2091 void analyze_design(RTLIL::Design
*design
)
2093 bool has_feedback_arcs
= false;
2094 bool has_buffered_comb_wires
= false;
2096 for (auto module
: design
->modules()) {
2097 if (!design
->selected_module(module
))
2100 SigMap
&sigmap
= sigmaps
[module
];
2103 if (module
->get_bool_attribute(ID(cxxrtl_blackbox
))) {
2104 for (auto port
: module
->ports
) {
2105 RTLIL::Wire
*wire
= module
->wire(port
);
2106 if (wire
->port_input
&& !wire
->port_output
)
2107 unbuffered_wires
.insert(wire
);
2108 if (wire
->has_attribute(ID(cxxrtl_edge
))) {
2109 RTLIL::Const edge_attr
= wire
->attributes
[ID(cxxrtl_edge
)];
2110 if (!(edge_attr
.flags
& RTLIL::CONST_FLAG_STRING
) || (int)edge_attr
.decode_string().size() != GetSize(wire
))
2111 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' is not a string with one character per bit.\n",
2112 log_id(module
), log_signal(wire
));
2114 std::string edges
= wire
->get_string_attribute(ID(cxxrtl_edge
));
2115 for (int i
= 0; i
< GetSize(wire
); i
++) {
2116 RTLIL::SigSpec wire_sig
= wire
;
2119 case 'p': register_edge_signal(sigmap
, wire_sig
[i
], RTLIL::STp
); break;
2120 case 'n': register_edge_signal(sigmap
, wire_sig
[i
], RTLIL::STn
); break;
2121 case 'a': register_edge_signal(sigmap
, wire_sig
[i
], RTLIL::STe
); break;
2123 log_cmd_error("Attribute `cxxrtl_edge' of port `%s.%s' contains specifiers "
2124 "other than '-', 'p', 'n', or 'a'.\n",
2125 log_id(module
), log_signal(wire
));
2131 // Black boxes converge by default, since their implementations are quite unlikely to require
2132 // internal propagation of comb signals.
2133 eval_converges
[module
] = true;
2139 for (auto conn
: module
->connections())
2140 flow
.add_node(conn
);
2142 dict
<const RTLIL::Cell
*, FlowGraph::Node
*> memrw_cell_nodes
;
2143 dict
<std::pair
<RTLIL::SigBit
, const RTLIL::Memory
*>,
2144 pool
<const RTLIL::Cell
*>> memwr_per_domain
;
2145 for (auto cell
: module
->cells()) {
2147 log_cmd_error("Unknown cell `%s'.\n", log_id(cell
->type
));
2149 RTLIL::Module
*cell_module
= design
->module(cell
->type
);
2151 cell_module
->get_blackbox_attribute() &&
2152 !cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
)))
2153 log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell
->type
));
2156 cell_module
->get_bool_attribute(ID(cxxrtl_blackbox
)) &&
2157 cell_module
->get_bool_attribute(ID(cxxrtl_template
)))
2158 blackbox_specializations
[cell_module
].insert(template_args(cell
));
2160 FlowGraph::Node
*node
= flow
.add_node(cell
);
2162 // Various DFF cells are treated like posedge/negedge processes, see above for details.
2163 if (cell
->type
.in(ID($dff
), ID($dffe
), ID($adff
), ID($adffe
), ID($dffsr
), ID($dffsre
), ID($sdff
), ID($sdffe
), ID($sdffce
))) {
2164 if (sigmap(cell
->getPort(ID::CLK
)).is_wire())
2165 register_edge_signal(sigmap
, cell
->getPort(ID::CLK
),
2166 cell
->parameters
[ID::CLK_POLARITY
].as_bool() ? RTLIL::STp
: RTLIL::STn
);
2168 // Similar for memory port cells.
2169 if (cell
->type
.in(ID($memrd
), ID($memwr
))) {
2170 if (cell
->getParam(ID::CLK_ENABLE
).as_bool()) {
2171 if (sigmap(cell
->getPort(ID::CLK
)).is_wire())
2172 register_edge_signal(sigmap
, cell
->getPort(ID::CLK
),
2173 cell
->parameters
[ID::CLK_POLARITY
].as_bool() ? RTLIL::STp
: RTLIL::STn
);
2175 memrw_cell_nodes
[cell
] = node
;
2177 // Optimize access to read-only memories.
2178 if (cell
->type
== ID($memwr
))
2179 writable_memories
.insert(module
->memories
[cell
->getParam(ID::MEMID
).decode_string()]);
2180 // Collect groups of memory write ports in the same domain.
2181 if (cell
->type
== ID($memwr
) && cell
->getParam(ID::CLK_ENABLE
).as_bool() && cell
->getPort(ID::CLK
).is_wire()) {
2182 RTLIL::SigBit clk_bit
= sigmap(cell
->getPort(ID::CLK
))[0];
2183 const RTLIL::Memory
*memory
= module
->memories
[cell
->getParam(ID::MEMID
).decode_string()];
2184 memwr_per_domain
[{clk_bit
, memory
}].insert(cell
);
2186 // Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
2187 // of RTLIL memory objects and $memrd/$memwr/$meminit cells.
2188 if (cell
->type
.in(ID($mem
)))
2191 for (auto cell
: module
->cells()) {
2192 // Collect groups of memory write ports read by every transparent read port.
2193 if (cell
->type
== ID($memrd
) && cell
->getParam(ID::CLK_ENABLE
).as_bool() && cell
->getPort(ID::CLK
).is_wire() &&
2194 cell
->getParam(ID::TRANSPARENT
).as_bool()) {
2195 RTLIL::SigBit clk_bit
= sigmap(cell
->getPort(ID::CLK
))[0];
2196 const RTLIL::Memory
*memory
= module
->memories
[cell
->getParam(ID::MEMID
).decode_string()];
2197 for (auto memwr_cell
: memwr_per_domain
[{clk_bit
, memory
}]) {
2198 transparent_for
[cell
].insert(memwr_cell
);
2199 // Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
2200 // in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
2201 flow
.add_uses(memrw_cell_nodes
[cell
], memwr_cell
->getPort(ID::EN
));
2202 flow
.add_uses(memrw_cell_nodes
[cell
], memwr_cell
->getPort(ID::ADDR
));
2203 flow
.add_uses(memrw_cell_nodes
[cell
], memwr_cell
->getPort(ID::DATA
));
2208 for (auto proc
: module
->processes
) {
2209 flow
.add_node(proc
.second
);
2211 for (auto sync
: proc
.second
->syncs
)
2212 switch (sync
->type
) {
2213 // Edge-type sync rules require pre-registration.
2217 register_edge_signal(sigmap
, sync
->signal
, sync
->type
);
2220 // Level-type sync rules require no special handling.
2227 log_cmd_error("Global clock is not supported.\n");
2229 // Handling of init-type sync rules is delegated to the `proc_init` pass, so we can use the wire
2230 // attribute regardless of input.
2236 for (auto wire
: module
->wires()) {
2237 if (!flow
.is_elidable(wire
)) continue;
2238 if (wire
->port_id
!= 0) continue;
2239 if (wire
->get_bool_attribute(ID::keep
)) continue;
2240 if (wire
->name
.begins_with("$") && !elide_internal
) continue;
2241 if (wire
->name
.begins_with("\\") && !elide_public
) continue;
2242 if (edge_wires
[wire
]) continue;
2243 if (flow
.wire_comb_defs
[wire
].size() > 1)
2244 log_cmd_error("Wire %s.%s has multiple drivers.\n", log_id(module
), log_id(wire
));
2245 log_assert(flow
.wire_comb_defs
[wire
].size() == 1);
2246 elided_wires
[wire
] = **flow
.wire_comb_defs
[wire
].begin();
2249 dict
<FlowGraph::Node
*, pool
<const RTLIL::Wire
*>, hash_ptr_ops
> node_defs
;
2250 for (auto wire_comb_def
: flow
.wire_comb_defs
)
2251 for (auto node
: wire_comb_def
.second
)
2252 node_defs
[node
].insert(wire_comb_def
.first
);
2254 Scheduler
<FlowGraph::Node
> scheduler
;
2255 dict
<FlowGraph::Node
*, Scheduler
<FlowGraph::Node
>::Vertex
*, hash_ptr_ops
> node_map
;
2256 for (auto node
: flow
.nodes
)
2257 node_map
[node
] = scheduler
.add(node
);
2258 for (auto node_def
: node_defs
) {
2259 auto vertex
= node_map
[node_def
.first
];
2260 for (auto wire
: node_def
.second
)
2261 for (auto succ_node
: flow
.wire_uses
[wire
]) {
2262 auto succ_vertex
= node_map
[succ_node
];
2263 vertex
->succs
.insert(succ_vertex
);
2264 succ_vertex
->preds
.insert(vertex
);
2268 auto eval_order
= scheduler
.schedule();
2269 pool
<FlowGraph::Node
*, hash_ptr_ops
> evaluated
;
2270 pool
<const RTLIL::Wire
*> feedback_wires
;
2271 for (auto vertex
: eval_order
) {
2272 auto node
= vertex
->data
;
2273 schedule
[module
].push_back(*node
);
2274 // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi
2275 // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be
2276 // caused by a true logic loop, but usually are a benign result of dependency tracking that works
2277 // on wire, not bit, level. Nevertheless, feedback wires cannot be localized.
2278 evaluated
.insert(node
);
2279 for (auto wire
: node_defs
[node
])
2280 for (auto succ_node
: flow
.wire_uses
[wire
])
2281 if (evaluated
[succ_node
]) {
2282 feedback_wires
.insert(wire
);
2283 // Feedback wires may never be elided because feedback requires state, but the point of elision
2284 // (and localization) is to eliminate state.
2285 elided_wires
.erase(wire
);
2289 if (!feedback_wires
.empty()) {
2290 has_feedback_arcs
= true;
2291 log("Module `%s' contains feedback arcs through wires:\n", log_id(module
));
2292 for (auto wire
: feedback_wires
)
2293 log(" %s\n", log_id(wire
));
2296 for (auto wire
: module
->wires()) {
2297 if (feedback_wires
[wire
]) continue;
2298 if (wire
->port_output
&& !module
->get_bool_attribute(ID::top
)) continue;
2299 if (wire
->name
.begins_with("$") && !unbuffer_internal
) continue;
2300 if (wire
->name
.begins_with("\\") && !unbuffer_public
) continue;
2301 if (flow
.wire_sync_defs
.count(wire
) > 0) continue;
2302 unbuffered_wires
.insert(wire
);
2303 if (edge_wires
[wire
]) continue;
2304 if (wire
->get_bool_attribute(ID::keep
)) continue;
2305 if (wire
->port_input
|| wire
->port_output
) continue;
2306 if (wire
->name
.begins_with("$") && !localize_internal
) continue;
2307 if (wire
->name
.begins_with("\\") && !localize_public
) continue;
2308 localized_wires
.insert(wire
);
2311 // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
2312 // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
2313 // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
2314 // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
2315 // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
2316 // also require more than one delta cycle to converge.
2317 pool
<const RTLIL::Wire
*> buffered_comb_wires
;
2318 for (auto wire
: module
->wires()) {
2319 if (flow
.wire_comb_defs
[wire
].size() > 0 && !unbuffered_wires
[wire
] && !feedback_wires
[wire
])
2320 buffered_comb_wires
.insert(wire
);
2322 if (!buffered_comb_wires
.empty()) {
2323 has_buffered_comb_wires
= true;
2324 log("Module `%s' contains buffered combinatorial wires:\n", log_id(module
));
2325 for (auto wire
: buffered_comb_wires
)
2326 log(" %s\n", log_id(wire
));
2329 eval_converges
[module
] = feedback_wires
.empty() && buffered_comb_wires
.empty();
2331 for (auto item
: flow
.bit_has_state
)
2332 bit_has_state
.insert(item
);
2335 // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
2336 // at essentially zero additional cost.
2338 // Note that the information collected here can't be used for optimizing the netlist: debug information queries
2339 // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
2340 for (auto wire
: module
->wires()) {
2341 if (!wire
->name
.isPublic())
2343 if (!unbuffered_wires
[wire
])
2345 const RTLIL::Wire
*wire_it
= wire
;
2347 if (!(flow
.wire_def_elidable
.count(wire_it
) && flow
.wire_def_elidable
[wire_it
]))
2348 break; // not an alias: complex def
2349 log_assert(flow
.wire_comb_defs
[wire_it
].size() == 1);
2350 FlowGraph::Node
*node
= *flow
.wire_comb_defs
[wire_it
].begin();
2351 if (node
->type
!= FlowGraph::Node::Type::CONNECT
)
2352 break; // not an alias: def by cell
2353 RTLIL::SigSpec rhs_sig
= node
->connect
.second
;
2354 if (rhs_sig
.is_wire()) {
2355 RTLIL::Wire
*rhs_wire
= rhs_sig
.as_wire();
2356 if (unbuffered_wires
[rhs_wire
]) {
2357 wire_it
= rhs_wire
; // maybe an alias
2359 debug_alias_wires
[wire
] = rhs_wire
; // is an alias
2362 } else if (rhs_sig
.is_fully_const()) {
2363 debug_const_wires
[wire
] = rhs_sig
.as_const(); // is a const
2366 break; // not an alias: complex rhs
2372 if (has_feedback_arcs
|| has_buffered_comb_wires
) {
2373 // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
2374 // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
2375 // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
2376 const char *why_pessimistic
= nullptr;
2377 if (has_feedback_arcs
)
2378 why_pessimistic
= "feedback wires";
2379 else if (has_buffered_comb_wires
)
2380 why_pessimistic
= "buffered combinatorial wires";
2381 log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic
);
2383 log("Flattening may eliminate %s from the design.\n", why_pessimistic
);
2385 log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic
);
2389 void check_design(RTLIL::Design
*design
, bool &has_top
, bool &has_sync_init
, bool &has_packed_mem
)
2391 has_sync_init
= has_packed_mem
= has_top
= false;
2393 for (auto module
: design
->modules()) {
2394 if (module
->get_blackbox_attribute() && !module
->has_attribute(ID(cxxrtl_blackbox
)))
2397 if (!design
->selected_whole_module(module
))
2398 if (design
->selected_module(module
))
2399 log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module
->name
));
2400 if (!design
->selected_module(module
))
2403 if (module
->get_bool_attribute(ID::top
))
2406 for (auto proc
: module
->processes
)
2407 for (auto sync
: proc
.second
->syncs
)
2408 if (sync
->type
== RTLIL::STi
)
2409 has_sync_init
= true;
2411 // The Mem constructor also checks for well-formedness of $meminit cells, if any.
2412 for (auto &mem
: Mem::get_all_memories(module
))
2414 has_packed_mem
= true;
2418 void prepare_design(RTLIL::Design
*design
)
2420 bool did_anything
= false;
2421 bool has_top
, has_sync_init
, has_packed_mem
;
2423 check_design(design
, has_top
, has_sync_init
, has_packed_mem
);
2424 if (run_hierarchy
&& !has_top
) {
2425 Pass::call(design
, "hierarchy -auto-top");
2426 did_anything
= true;
2429 Pass::call(design
, "flatten");
2430 did_anything
= true;
2433 Pass::call(design
, "proc");
2434 did_anything
= true;
2435 } else if (has_sync_init
) {
2436 // We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
2437 // in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
2438 Pass::call(design
, "proc_prune");
2439 Pass::call(design
, "proc_clean");
2440 Pass::call(design
, "proc_init");
2441 did_anything
= true;
2443 if (has_packed_mem
) {
2444 Pass::call(design
, "memory_unpack");
2445 did_anything
= true;
2447 // Recheck the design if it was modified.
2449 check_design(design
, has_top
, has_sync_init
, has_packed_mem
);
2450 log_assert(has_top
&& !has_sync_init
&& !has_packed_mem
);
2454 analyze_design(design
);
2458 struct CxxrtlBackend
: public Backend
{
2459 static const int DEFAULT_OPT_LEVEL
= 6;
2460 static const int OPT_LEVEL_DEBUG
= 4;
2461 static const int DEFAULT_DEBUG_LEVEL
= 1;
2463 CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
2464 void help() override
2466 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2468 log(" write_cxxrtl [options] [filename]\n");
2470 log("Write C++ code that simulates the design. The generated code requires a driver\n");
2471 log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
2473 log("The following driver may be used as an example for a design with a single clock\n");
2474 log("driving rising edge triggered flip-flops:\n");
2476 log(" #include \"top.cc\"\n");
2478 log(" int main() {\n");
2479 log(" cxxrtl_design::p_top top;\n");
2480 log(" top.step();\n");
2481 log(" while (1) {\n");
2482 log(" /* user logic */\n");
2483 log(" top.p_clk.set(false);\n");
2484 log(" top.step();\n");
2485 log(" top.p_clk.set(true);\n");
2486 log(" top.step();\n");
2490 log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
2491 log("subject to race conditions. If, in the example above, the user logic would run\n");
2492 log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
2494 log("This backend supports replacing parts of the design with black boxes implemented\n");
2495 log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
2496 log("and the generated code consists only of an interface and a factory function.\n");
2497 log("The driver must implement the factory function that creates an implementation of\n");
2498 log("the black box, taking into account the parameters it is instantiated with.\n");
2500 log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
2501 log("a synchronous debug sink:\n");
2503 log(" (* cxxrtl_blackbox *)\n");
2504 log(" module debug(...);\n");
2505 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2506 log(" input en;\n");
2507 log(" input [7:0] i_data;\n");
2508 log(" (* cxxrtl_sync *) output [7:0] o_data;\n");
2509 log(" endmodule\n");
2511 log("For this HDL interface, this backend will generate the following C++ interface:\n");
2513 log(" struct bb_p_debug : public module {\n");
2514 log(" value<1> p_clk;\n");
2515 log(" bool posedge_p_clk() const { /* ... */ }\n");
2516 log(" value<1> p_en;\n");
2517 log(" value<8> p_i_data;\n");
2518 log(" wire<8> p_o_data;\n");
2520 log(" bool eval() override;\n");
2521 log(" bool commit() override;\n");
2523 log(" static std::unique_ptr<bb_p_debug>\n");
2524 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2527 log("The `create' function must be implemented by the driver. For example, it could\n");
2528 log("always provide an implementation logging the values to standard error stream:\n");
2530 log(" namespace cxxrtl_design {\n");
2532 log(" struct stderr_debug : public bb_p_debug {\n");
2533 log(" bool eval() override {\n");
2534 log(" if (posedge_p_clk() && p_en)\n");
2535 log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
2536 log(" p_o_data.next = p_i_data;\n");
2537 log(" return bb_p_debug::eval();\n");
2541 log(" std::unique_ptr<bb_p_debug>\n");
2542 log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
2543 log(" cxxrtl::metadata_map attributes) {\n");
2544 log(" return std::make_unique<stderr_debug>();\n");
2549 log("For complex applications of black boxes, it is possible to parameterize their\n");
2550 log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
2551 log("interface for a configurable width debug sink:\n");
2553 log(" (* cxxrtl_blackbox, cxxrtl_template = \"WIDTH\" *)\n");
2554 log(" module debug(...);\n");
2555 log(" parameter WIDTH = 8;\n");
2556 log(" (* cxxrtl_edge = \"p\" *) input clk;\n");
2557 log(" input en;\n");
2558 log(" (* cxxrtl_width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
2559 log(" (* cxxrtl_width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
2560 log(" endmodule\n");
2562 log("For this parametric HDL interface, this backend will generate the following C++\n");
2563 log("interface (only the differences are shown):\n");
2565 log(" template<size_t WIDTH>\n");
2566 log(" struct bb_p_debug : public module {\n");
2568 log(" value<WIDTH> p_i_data;\n");
2569 log(" wire<WIDTH> p_o_data;\n");
2571 log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
2572 log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
2575 log("The `create' function must be implemented by the driver, specialized for every\n");
2576 log("possible combination of template parameters. (Specialization is necessary to\n");
2577 log("enable separate compilation of generated code and black box implementations.)\n");
2579 log(" template<size_t SIZE>\n");
2580 log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
2584 log(" template<>\n");
2585 log(" std::unique_ptr<bb_p_debug<8>>\n");
2586 log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
2587 log(" cxxrtl::metadata_map attributes) {\n");
2588 log(" return std::make_unique<stderr_debug<8>>();\n");
2591 log("The following attributes are recognized by this backend:\n");
2593 log(" cxxrtl_blackbox\n");
2594 log(" only valid on modules. if specified, the module contents are ignored,\n");
2595 log(" and the generated code includes only the module interface and a factory\n");
2596 log(" function, which will be called to instantiate the module.\n");
2598 log(" cxxrtl_edge\n");
2599 log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
2600 log(" if specified on signal `clk`, the generated code includes edge detectors\n");
2601 log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
2602 log(" \"a\"), simplifying implementation of clocked black boxes.\n");
2604 log(" cxxrtl_template\n");
2605 log(" only valid on black boxes. must contain a space separated sequence of\n");
2606 log(" identifiers that have a corresponding black box parameters. for each\n");
2607 log(" of them, the generated code includes a `size_t` template parameter.\n");
2609 log(" cxxrtl_width\n");
2610 log(" only valid on ports of black boxes. must be a constant expression, which\n");
2611 log(" is directly inserted into generated code.\n");
2613 log(" cxxrtl_comb, cxxrtl_sync\n");
2614 log(" only valid on outputs of black boxes. if specified, indicates that every\n");
2615 log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
2616 log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
2617 log(" if neither is specified, the output will be pessimistically treated as\n");
2618 log(" driven by both combinatorial and synchronous logic.\n");
2620 log("The following options are supported by this backend:\n");
2623 log(" generate separate interface (.h) and implementation (.cc) files.\n");
2624 log(" if specified, the backend must be called with a filename, and filename\n");
2625 log(" of the interface is derived from filename of the implementation.\n");
2626 log(" otherwise, interface and implementation are generated together.\n");
2628 log(" -namespace <ns-name>\n");
2629 log(" place the generated code into namespace <ns-name>. if not specified,\n");
2630 log(" \"cxxrtl_design\" is used.\n");
2632 log(" -nohierarchy\n");
2633 log(" use design hierarchy as-is. in most designs, a top module should be\n");
2634 log(" present as it is exposed through the C API and has unbuffered outputs\n");
2635 log(" for improved performance; it will be determined automatically if absent.\n");
2637 log(" -noflatten\n");
2638 log(" don't flatten the design. fully flattened designs can evaluate within\n");
2639 log(" one delta cycle if they have no combinatorial feedback.\n");
2640 log(" note that the debug interface and waveform dumps use full hierarchical\n");
2641 log(" names for all wires even in flattened designs.\n");
2644 log(" don't convert processes to netlists. in most designs, converting\n");
2645 log(" processes significantly improves evaluation performance at the cost of\n");
2646 log(" slight increase in compilation time.\n");
2648 log(" -O <level>\n");
2649 log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL
);
2650 log(" levels dramatically decrease compile and run time, and highest level\n");
2651 log(" possible for a design should be used.\n");
2654 log(" no optimization.\n");
2657 log(" localize internal wires if possible.\n");
2660 log(" like -O1, and unbuffer internal wires if possible.\n");
2663 log(" like -O2, and elide internal wires if possible.\n");
2666 log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
2669 log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
2672 log(" like -O5, and elide public wires not marked (*keep*) if possible.\n");
2675 log(" highest optimization level that provides debug information for all\n");
2676 log(" public wires. currently, alias for -O%d.\n", OPT_LEVEL_DEBUG
);
2678 log(" -g <level>\n");
2679 log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL
);
2680 log(" more visibility and generate more code, but do not pessimize evaluation.\n");
2683 log(" no debug information.\n");
2686 log(" debug information for non-optimized public wires. this also makes it\n");
2687 log(" possible to use the C API.\n");
2691 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) override
2693 bool nohierarchy
= false;
2694 bool noflatten
= false;
2695 bool noproc
= false;
2696 int opt_level
= DEFAULT_OPT_LEVEL
;
2697 int debug_level
= DEFAULT_DEBUG_LEVEL
;
2698 CxxrtlWorker worker
;
2700 log_header(design
, "Executing CXXRTL backend.\n");
2703 for (argidx
= 1; argidx
< args
.size(); argidx
++)
2705 if (args
[argidx
] == "-nohierarchy") {
2709 if (args
[argidx
] == "-noflatten") {
2713 if (args
[argidx
] == "-noproc") {
2717 if (args
[argidx
] == "-Og") {
2718 opt_level
= OPT_LEVEL_DEBUG
;
2721 if (args
[argidx
] == "-O" && argidx
+1 < args
.size() && args
[argidx
+1] == "g") {
2723 opt_level
= OPT_LEVEL_DEBUG
;
2726 if (args
[argidx
] == "-O" && argidx
+1 < args
.size()) {
2727 opt_level
= std::stoi(args
[++argidx
]);
2730 if (args
[argidx
].substr(0, 2) == "-O" && args
[argidx
].size() == 3 && isdigit(args
[argidx
][2])) {
2731 opt_level
= std::stoi(args
[argidx
].substr(2));
2734 if (args
[argidx
] == "-g" && argidx
+1 < args
.size()) {
2735 debug_level
= std::stoi(args
[++argidx
]);
2738 if (args
[argidx
].substr(0, 2) == "-g" && args
[argidx
].size() == 3 && isdigit(args
[argidx
][2])) {
2739 debug_level
= std::stoi(args
[argidx
].substr(2));
2742 if (args
[argidx
] == "-header") {
2743 worker
.split_intf
= true;
2746 if (args
[argidx
] == "-namespace" && argidx
+1 < args
.size()) {
2747 worker
.design_ns
= args
[++argidx
];
2752 extra_args(f
, filename
, args
, argidx
);
2754 worker
.run_hierarchy
= !nohierarchy
;
2755 worker
.run_flatten
= !noflatten
;
2756 worker
.run_proc
= !noproc
;
2757 switch (opt_level
) {
2758 // the highest level here must match DEFAULT_OPT_LEVEL
2760 worker
.elide_public
= true;
2763 worker
.localize_public
= true;
2766 worker
.unbuffer_public
= true;
2769 worker
.elide_internal
= true;
2772 worker
.localize_internal
= true;
2775 worker
.unbuffer_internal
= true;
2780 log_cmd_error("Invalid optimization level %d.\n", opt_level
);
2782 switch (debug_level
) {
2783 // the highest level here must match DEFAULT_DEBUG_LEVEL
2785 worker
.debug_info
= true;
2790 log_cmd_error("Invalid debug information level %d.\n", debug_level
);
2793 std::ofstream intf_f
;
2794 if (worker
.split_intf
) {
2795 if (filename
== "<stdout>")
2796 log_cmd_error("Option -header must be used with a filename.\n");
2798 worker
.intf_filename
= filename
.substr(0, filename
.rfind('.')) + ".h";
2799 intf_f
.open(worker
.intf_filename
, std::ofstream::trunc
);
2801 log_cmd_error("Can't open file `%s' for writing: %s\n",
2802 worker
.intf_filename
.c_str(), strerror(errno
));
2804 worker
.intf_f
= &intf_f
;
2808 worker
.prepare_design(design
);
2809 worker
.dump_design(design
);
2813 PRIVATE_NAMESPACE_END