2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2020 whitequark <whitequark@whitequark.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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22 // This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.cc`.
24 // The CXXRTL C API makes it possible to drive CXXRTL designs using C or any other language that
25 // supports the C ABI, for example, Python. It does not provide a way to implement black boxes.
35 // Opaque reference to a design toplevel.
37 // A design toplevel can only be used to create a design handle.
38 typedef struct _cxxrtl_toplevel
*cxxrtl_toplevel
;
40 // The constructor for a design toplevel is provided as a part of generated code for that design.
41 // Its prototype matches:
43 // cxxrtl_toplevel <design-name>_create();
45 // Opaque reference to a design handle.
47 // A design handle is required by all operations in the C API.
48 typedef struct _cxxrtl_handle
*cxxrtl_handle
;
50 // Create a design handle from a design toplevel.
52 // The `design` is consumed by this operation and cannot be used afterwards.
53 cxxrtl_handle
cxxrtl_create(cxxrtl_toplevel design
);
55 // Release all resources used by a design and its handle.
56 void cxxrtl_destroy(cxxrtl_handle handle
);
58 // Evaluate the design, propagating changes on inputs to the `next` value of internal state and
61 // Returns 1 if the design is known to immediately converge, 0 otherwise.
62 int cxxrtl_eval(cxxrtl_handle handle
);
64 // Commit the design, replacing the `curr` value of internal state and output wires with the `next`
67 // Return 1 if any of the `curr` values were updated, 0 otherwise.
68 int cxxrtl_commit(cxxrtl_handle handle
);
70 // Simulate the design to a fixed point.
72 // Returns the number of delta cycles.
73 size_t cxxrtl_step(cxxrtl_handle handle
);
75 // Type of a simulated object.
77 // The type of a simulated object indicates the way it is stored and the operations that are legal
78 // to perform on it (i.e. won't crash the simulation). It says very little about object semantics,
79 // which is specified through flags.
81 // Values correspond to singly buffered netlist nodes, i.e. nodes driven exclusively by
82 // combinatorial cells, or toplevel input nodes.
84 // Values can be inspected via the `curr` pointer. If the `next` pointer is NULL, the value is
85 // driven by a constant and can never be modified. Otherwise, the value can be modified through
86 // the `next` pointer (which is equal to `curr` if not NULL). Note that changes to the bits
87 // driven by combinatorial cells will be ignored.
89 // Values always have depth 1.
92 // Wires correspond to doubly buffered netlist nodes, i.e. nodes driven, at least in part, by
93 // storage cells, or by combinatorial cells that are a part of a feedback path. They are also
94 // present in non-optimized builds.
96 // Wires can be inspected via the `curr` pointer and modified via the `next` pointer (which are
97 // distinct for wires). Note that changes to the bits driven by combinatorial cells will be
100 // Wires always have depth 1.
103 // Memories correspond to memory cells.
105 // Memories can be inspected and modified via the `curr` pointer. Due to a limitation of this
106 // API, memories cannot yet be modified in a guaranteed race-free way, and the `next` pointer is
110 // Aliases correspond to netlist nodes driven by another node such that their value is always
113 // Aliases can be inspected via the `curr` pointer. They cannot be modified, and the `next`
114 // pointer is always NULL.
117 // More object types may be added in the future, but the existing ones will never change.
120 // Flags of a simulated object.
122 // The flags of a simulated object indicate its role in the netlist:
123 // * The flags `CXXRTL_INPUT` and `CXXRTL_OUTPUT` designate module ports.
124 // * The flags `CXXRTL_DRIVEN_SYNC`, `CXXRTL_DRIVEN_COMB`, and `CXXRTL_UNDRIVEN` specify
125 // the semantics of node state. An object with several of these flags set has different bits
126 // follow different semantics.
128 // Node is a module input port.
130 // This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined
131 // with `CXXRTL_OUTPUT`, as well as other flags.
132 CXXRTL_INPUT
= 1 << 0,
134 // Node is a module output port.
136 // This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with `CXXRTL_INPUT`,
137 // as well as other flags.
138 CXXRTL_OUTPUT
= 1 << 1,
140 // Node is a module inout port.
142 // This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with other flags.
143 CXXRTL_INOUT
= (CXXRTL_INPUT
|CXXRTL_OUTPUT
),
145 // Node has bits that are driven by a storage cell.
147 // This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with
148 // `CXXRTL_DRIVEN_COMB` and `CXXRTL_UNDRIVEN`, as well as other flags.
150 // This flag is set on wires that have bits connected directly to the output of a flip-flop or
151 // a latch, and hold its state. Many `CXXRTL_WIRE` objects may not have the `CXXRTL_DRIVEN_SYNC`
152 // flag set; for example, output ports and feedback wires generally won't. Writing to the `next`
153 // pointer of these wires updates stored state, and for designs without combinatorial loops,
154 // capturing the value from every of these wires through the `curr` pointer creates a complete
155 // snapshot of the design state.
156 CXXRTL_DRIVEN_SYNC
= 1 << 2,
158 // Node has bits that are driven by a combinatorial cell or another node.
160 // This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined
161 // with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_UNDRIVEN`, as well as other flags.
163 // This flag is set on objects that have bits connected to the output of a combinatorial cell,
164 // or directly to another node. For designs without combinatorial loops, writing to such bits
165 // through the `next` pointer (if it is not NULL) has no effect.
166 CXXRTL_DRIVEN_COMB
= 1 << 3,
168 // Node has bits that are not driven.
170 // This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined
171 // with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_DRIVEN_COMB`, as well as other flags.
173 // This flag is set on objects that have bits not driven by an output of any cell or by another
174 // node, such as inputs and dangling wires.
175 CXXRTL_UNDRIVEN
= 1 << 4,
177 // More object flags may be added in the future, but the existing ones will never change.
180 // Description of a simulated object.
182 // The `data` array can be accessed directly to inspect and, if applicable, modify the bits
183 // stored in the object.
184 struct cxxrtl_object
{
185 // Type of the object.
187 // All objects have the same memory layout determined by `width` and `depth`, but the type
188 // determines all other properties of the object.
189 uint32_t type
; // actually `enum cxxrtl_type`
191 // Flags of the object.
192 uint32_t flags
; // actually bit mask of `enum cxxrtl_flags`
194 // Width of the object in bits.
197 // Index of the least significant bit.
200 // Depth of the object. Only meaningful for memories; for other objects, always 1.
203 // Index of the first word. Only meaningful for memories; for other objects, always 0;
206 // Bits stored in the object, as 32-bit chunks, least significant bits first.
208 // The width is rounded up to a multiple of 32; the padding bits are always set to 0 by
209 // the simulation code, and must be always written as 0 when modified by user code.
210 // In memories, every element is stored contiguously. Therefore, the total number of chunks
211 // in any object is `((width + 31) / 32) * depth`.
213 // To allow the simulation to be partitioned into multiple independent units communicating
214 // through wires, the bits are double buffered. To avoid race conditions, user code should
215 // always read from `curr` and write to `next`. The `curr` pointer is always valid; for objects
216 // that cannot be modified, or cannot be modified in a race-free way, `next` is NULL.
220 // More description fields may be added in the future, but the existing ones will never change.
223 // Retrieve description of a simulated object.
225 // The `name` is the full hierarchical name of the object in the Yosys notation, where public names
226 // have a `\` prefix and hierarchy levels are separated by single spaces. For example, if
227 // the top-level module instantiates a module `foo`, which in turn contains a wire `bar`, the full
228 // hierarchical name is `\foo \bar`.
230 // The storage of a single abstract object may be split (usually with the `splitnets` pass) into
231 // many physical parts, all of which correspond to the same hierarchical name. To handle such cases,
232 // this function returns an array and writes its length to `parts`. The array is sorted by `lsb_at`.
234 // Returns the object parts if it was found, NULL otherwise. The returned parts are valid until
235 // the design is destroyed.
236 struct cxxrtl_object
*cxxrtl_get_parts(cxxrtl_handle handle
, const char *name
, size_t *parts
);
238 // Retrieve description of a single part simulated object.
240 // This function is a shortcut for the most common use of `cxxrtl_get_parts`. It asserts that,
241 // if the object exists, it consists of a single part. If assertions are disabled, it returns NULL
242 // for multi-part objects.
243 inline struct cxxrtl_object
*cxxrtl_get(cxxrtl_handle handle
, const char *name
) {
245 struct cxxrtl_object
*object
= cxxrtl_get_parts(handle
, name
, &parts
);
246 assert(object
== NULL
|| parts
== 1);
247 if (object
== NULL
|| parts
== 1)
252 // Enumerate simulated objects.
254 // For every object in the simulation, `callback` is called with the provided `data`, the full
255 // hierarchical name of the object (see `cxxrtl_get` for details), and the object parts.
256 // The provided `name` and `object` values are valid until the design is destroyed.
257 void cxxrtl_enum(cxxrtl_handle handle
, void *data
,
258 void (*callback
)(void *data
, const char *name
,
259 struct cxxrtl_object
*object
, size_t parts
));