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Merge pull request #2446 from RobertBaruch/rtlil_format
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 USING_YOSYS_NAMESPACE
31 PRIVATE_NAMESPACE_BEGIN
32
33 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
34 #define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str()
35 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
36
37 struct EdifNames
38 {
39 int counter;
40 char delim_left, delim_right;
41 std::set<std::string> generated_names, used_names;
42 std::map<std::string, std::string> name_map;
43
44 EdifNames() : counter(1), delim_left('['), delim_right(']') { }
45
46 std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0)
47 {
48 if (define) {
49 std::string new_id = operator()(id, false);
50 if (port_rename)
51 return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right);
52 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
53 }
54
55 if (name_map.count(id) > 0)
56 return name_map.at(id);
57 if (generated_names.count(id) > 0)
58 goto do_rename;
59 if (id == "GND" || id == "VCC")
60 goto do_rename;
61
62 for (size_t i = 0; i < id.size(); i++) {
63 if ('A' <= id[i] && id[i] <= 'Z')
64 continue;
65 if ('a' <= id[i] && id[i] <= 'z')
66 continue;
67 if ('0' <= id[i] && id[i] <= '9' && i > 0)
68 continue;
69 if (id[i] == '_' && i > 0 && i != id.size()-1)
70 continue;
71 goto do_rename;
72 }
73
74 used_names.insert(id);
75 return id;
76
77 do_rename:;
78 std::string gen_name;
79 while (1) {
80 gen_name = stringf("id%05d", counter++);
81 if (generated_names.count(gen_name) == 0 &&
82 used_names.count(gen_name) == 0)
83 break;
84 }
85 generated_names.insert(gen_name);
86 name_map[id] = gen_name;
87 return gen_name;
88 }
89 };
90
91 struct EdifBackend : public Backend {
92 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
93 void help() override
94 {
95 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
96 log("\n");
97 log(" write_edif [options] [filename]\n");
98 log("\n");
99 log("Write the current design to an EDIF netlist file.\n");
100 log("\n");
101 log(" -top top_module\n");
102 log(" set the specified module as design top module\n");
103 log("\n");
104 log(" -nogndvcc\n");
105 log(" do not create \"GND\" and \"VCC\" cells. (this will produce an error\n");
106 log(" if the design contains constant nets. use \"hilomap\" to map to custom\n");
107 log(" constant drivers first)\n");
108 log("\n");
109 log(" -gndvccy\n");
110 log(" create \"GND\" and \"VCC\" cells with \"Y\" outputs. (the default is \"G\"\n");
111 log(" for \"GND\" and \"P\" for \"VCC\".)\n");
112 log("\n");
113 log(" -attrprop\n");
114 log(" create EDIF properties for cell attributes\n");
115 log("\n");
116 log(" -keep\n");
117 log(" create extra KEEP nets by allowing a cell to drive multiple nets.\n");
118 log("\n");
119 log(" -pvector {par|bra|ang}\n");
120 log(" sets the delimiting character for module port rename clauses to\n");
121 log(" parentheses, square brackets, or angle brackets.\n");
122 log("\n");
123 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
124 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
125 log("necessary to make small modifications to this command when a different tool\n");
126 log("is targeted.\n");
127 log("\n");
128 }
129 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
130 {
131 log_header(design, "Executing EDIF backend.\n");
132 std::string top_module_name;
133 bool port_rename = false;
134 bool attr_properties = false;
135 std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
136 bool nogndvcc = false, gndvccy = false, keepmode = false;
137 CellTypes ct(design);
138 EdifNames edif_names;
139
140 size_t argidx;
141 for (argidx = 1; argidx < args.size(); argidx++)
142 {
143 if (args[argidx] == "-top" && argidx+1 < args.size()) {
144 top_module_name = args[++argidx];
145 continue;
146 }
147 if (args[argidx] == "-nogndvcc") {
148 nogndvcc = true;
149 continue;
150 }
151 if (args[argidx] == "-gndvccy") {
152 gndvccy = true;
153 continue;
154 }
155 if (args[argidx] == "-attrprop") {
156 attr_properties = true;
157 continue;
158 }
159 if (args[argidx] == "-keep") {
160 keepmode = true;
161 continue;
162 }
163 if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
164 std::string parray;
165 port_rename = true;
166 parray = args[++argidx];
167 if (parray == "par") {
168 edif_names.delim_left = '(';edif_names.delim_right = ')';
169 } else if (parray == "ang") {
170 edif_names.delim_left = '<';edif_names.delim_right = '>';
171 } else {
172 edif_names.delim_left = '[';edif_names.delim_right = ']';
173 }
174 continue;
175 }
176 break;
177 }
178 extra_args(f, filename, args, argidx);
179
180 if (top_module_name.empty())
181 for (auto module : design->modules())
182 if (module->get_bool_attribute(ID::top))
183 top_module_name = module->name.str();
184
185 for (auto module : design->modules())
186 {
187 if (module->get_blackbox_attribute())
188 continue;
189
190 if (top_module_name.empty())
191 top_module_name = module->name.str();
192
193 if (module->processes.size() != 0)
194 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", log_id(module->name));
195 if (module->memories.size() != 0)
196 log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", log_id(module->name));
197
198 for (auto cell : module->cells())
199 {
200 if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
201 lib_cell_ports[cell->type];
202 for (auto p : cell->connections())
203 lib_cell_ports[cell->type][p.first] = GetSize(p.second);
204 }
205 }
206 }
207
208 if (top_module_name.empty())
209 log_error("No module found in design!\n");
210
211 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
212 *f << stringf(" (edifVersion 2 0 0)\n");
213 *f << stringf(" (edifLevel 0)\n");
214 *f << stringf(" (keywordMap (keywordLevel 0))\n");
215 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
216
217 *f << stringf(" (external LIB\n");
218 *f << stringf(" (edifLevel 0)\n");
219 *f << stringf(" (technology (numberDefinition))\n");
220
221 if (!nogndvcc)
222 {
223 *f << stringf(" (cell GND\n");
224 *f << stringf(" (cellType GENERIC)\n");
225 *f << stringf(" (view VIEW_NETLIST\n");
226 *f << stringf(" (viewType NETLIST)\n");
227 *f << stringf(" (interface (port %c (direction OUTPUT)))\n", gndvccy ? 'Y' : 'G');
228 *f << stringf(" )\n");
229 *f << stringf(" )\n");
230
231 *f << stringf(" (cell VCC\n");
232 *f << stringf(" (cellType GENERIC)\n");
233 *f << stringf(" (view VIEW_NETLIST\n");
234 *f << stringf(" (viewType NETLIST)\n");
235 *f << stringf(" (interface (port %c (direction OUTPUT)))\n", gndvccy ? 'Y' : 'P');
236 *f << stringf(" )\n");
237 *f << stringf(" )\n");
238 }
239
240 for (auto &cell_it : lib_cell_ports) {
241 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
242 *f << stringf(" (cellType GENERIC)\n");
243 *f << stringf(" (view VIEW_NETLIST\n");
244 *f << stringf(" (viewType NETLIST)\n");
245 *f << stringf(" (interface\n");
246 for (auto &port_it : cell_it.second) {
247 const char *dir = "INOUT";
248 if (ct.cell_known(cell_it.first)) {
249 if (!ct.cell_output(cell_it.first, port_it.first))
250 dir = "INPUT";
251 else if (!ct.cell_input(cell_it.first, port_it.first))
252 dir = "OUTPUT";
253 }
254 int width = port_it.second;
255 int start = 0;
256 bool upto = false;
257 auto m = design->module(cell_it.first);
258 if (m) {
259 auto w = m->wire(port_it.first);
260 if (w) {
261 width = GetSize(w);
262 start = w->start_offset;
263 upto = w->upto;
264 }
265 }
266 if (width == 1)
267 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
268 else {
269 int b[2];
270 b[upto ? 0 : 1] = start;
271 b[upto ? 1 : 0] = start+width-1;
272 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), width, dir);
273 }
274 }
275 *f << stringf(" )\n");
276 *f << stringf(" )\n");
277 *f << stringf(" )\n");
278 }
279 *f << stringf(" )\n");
280
281 std::vector<RTLIL::Module*> sorted_modules;
282
283 // extract module dependencies
284 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
285 for (auto module : design->modules()) {
286 module_deps[module] = std::set<RTLIL::Module*>();
287 for (auto cell : module->cells())
288 if (design->module(cell->type) != nullptr)
289 module_deps[module].insert(design->module(cell->type));
290 }
291
292 // simple good-enough topological sort
293 // (O(n*m) on n elements and depth m)
294 while (module_deps.size() > 0) {
295 size_t sorted_modules_idx = sorted_modules.size();
296 for (auto &it : module_deps) {
297 for (auto &dep : it.second)
298 if (module_deps.count(dep) > 0)
299 goto not_ready_yet;
300 // log("Next in topological sort: %s\n", log_id(it.first->name));
301 sorted_modules.push_back(it.first);
302 not_ready_yet:;
303 }
304 if (sorted_modules_idx == sorted_modules.size())
305 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name));
306 while (sorted_modules_idx < sorted_modules.size())
307 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
308 }
309
310
311 *f << stringf(" (library DESIGN\n");
312 *f << stringf(" (edifLevel 0)\n");
313 *f << stringf(" (technology (numberDefinition))\n");
314
315 auto add_prop = [&](IdString name, Const val) {
316 if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
317 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
318 else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
319 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
320 else {
321 std::string hex_string = "";
322 for (size_t i = 0; i < val.bits.size(); i += 4) {
323 int digit_value = 0;
324 if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
325 if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
326 if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
327 if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
328 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
329 hex_string = std::string(digit_str) + hex_string;
330 }
331 *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
332 }
333 };
334 for (auto module : sorted_modules)
335 {
336 if (module->get_blackbox_attribute())
337 continue;
338
339 SigMap sigmap(module);
340 std::map<RTLIL::SigSpec, std::set<std::pair<std::string, bool>>> net_join_db;
341
342 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
343 *f << stringf(" (cellType GENERIC)\n");
344 *f << stringf(" (view VIEW_NETLIST\n");
345 *f << stringf(" (viewType NETLIST)\n");
346 *f << stringf(" (interface\n");
347
348 for (auto cell : module->cells()) {
349 for (auto &conn : cell->connections())
350 if (cell->output(conn.first))
351 sigmap.add(conn.second);
352 }
353
354 for (auto wire : module->wires())
355 for (auto b1 : SigSpec(wire))
356 {
357 auto b2 = sigmap(b1);
358
359 if (b1 == b2 || !b2.wire)
360 continue;
361
362 log_assert(b1.wire != nullptr);
363
364 Wire *w1 = b1.wire;
365 Wire *w2 = b2.wire;
366
367 {
368 int c1 = w1->get_bool_attribute(ID::keep);
369 int c2 = w2->get_bool_attribute(ID::keep);
370
371 if (c1 > c2) goto promote;
372 if (c1 < c2) goto nopromote;
373 }
374
375 {
376 int c1 = w1->name.isPublic();
377 int c2 = w2->name.isPublic();
378
379 if (c1 > c2) goto promote;
380 if (c1 < c2) goto nopromote;
381 }
382
383 {
384 auto count_nontrivial_attr = [](Wire *w) {
385 int count = w->attributes.size();
386 count -= w->attributes.count(ID::src);
387 count -= w->attributes.count(ID::unused_bits);
388 return count;
389 };
390
391 int c1 = count_nontrivial_attr(w1);
392 int c2 = count_nontrivial_attr(w2);
393
394 if (c1 > c2) goto promote;
395 if (c1 < c2) goto nopromote;
396 }
397
398 {
399 int c1 = w1->port_id ? INT_MAX - w1->port_id : 0;
400 int c2 = w2->port_id ? INT_MAX - w2->port_id : 0;
401
402 if (c1 > c2) goto promote;
403 if (c1 < c2) goto nopromote;
404 }
405
406 nopromote:
407 if (0)
408 promote:
409 sigmap.add(b1);
410 }
411
412 for (auto wire : module->wires()) {
413 if (wire->port_id == 0)
414 continue;
415 const char *dir = "INOUT";
416 if (!wire->port_output)
417 dir = "INPUT";
418 else if (!wire->port_input)
419 dir = "OUTPUT";
420 if (wire->width == 1) {
421 *f << stringf(" (port %s (direction %s)", EDIF_DEF(wire->name), dir);
422 if (attr_properties)
423 for (auto &p : wire->attributes)
424 add_prop(p.first, p.second);
425 *f << ")\n";
426 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
427 net_join_db[sig].insert(make_pair(stringf("(portRef %s)", EDIF_REF(wire->name)), wire->port_input));
428 } else {
429 int b[2];
430 b[wire->upto ? 0 : 1] = wire->start_offset;
431 b[wire->upto ? 1 : 0] = wire->start_offset + GetSize(wire) - 1;
432 *f << stringf(" (port (array %s %d) (direction %s)", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
433 if (attr_properties)
434 for (auto &p : wire->attributes)
435 add_prop(p.first, p.second);
436
437 *f << ")\n";
438 for (int i = 0; i < wire->width; i++) {
439 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
440 net_join_db[sig].insert(make_pair(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1), wire->port_input));
441 }
442 }
443 }
444
445 *f << stringf(" )\n");
446 *f << stringf(" (contents\n");
447
448 if (!nogndvcc) {
449 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
450 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
451 }
452
453 for (auto cell : module->cells()) {
454 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
455 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
456 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
457 for (auto &p : cell->parameters)
458 add_prop(p.first, p.second);
459 if (attr_properties)
460 for (auto &p : cell->attributes)
461 add_prop(p.first, p.second);
462
463 *f << stringf(")\n");
464 for (auto &p : cell->connections()) {
465 RTLIL::SigSpec sig = sigmap(p.second);
466 for (int i = 0; i < GetSize(sig); i++)
467 if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1)
468 log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n",
469 i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i]));
470 else {
471 int member_idx = GetSize(sig)-i-1;
472 auto m = design->module(cell->type);
473 int width = sig.size();
474 if (m) {
475 auto w = m->wire(p.first);
476 if (w) {
477 member_idx = GetSize(w)-i-1;
478 width = GetSize(w);
479 }
480 }
481 if (width == 1)
482 net_join_db[sig[i]].insert(make_pair(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)), cell->output(p.first)));
483 else {
484 net_join_db[sig[i]].insert(make_pair(stringf("(portRef (member %s %d) (instanceRef %s))",
485 EDIF_REF(p.first), member_idx, EDIF_REF(cell->name)), cell->output(p.first)));
486 }
487 }
488 }
489 }
490
491 for (auto &it : net_join_db) {
492 RTLIL::SigBit sig = it.first;
493 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
494 if (sig == RTLIL::State::Sx) {
495 for (auto &ref : it.second)
496 log_warning("Exporting x-bit on %s as zero bit.\n", ref.first.c_str());
497 sig = RTLIL::State::S0;
498 } else if (sig == RTLIL::State::Sz) {
499 continue;
500 } else {
501 for (auto &ref : it.second)
502 log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first.c_str());
503 log_abort();
504 }
505 }
506 std::string netname;
507 if (sig == RTLIL::State::S0)
508 netname = "GND_NET";
509 else if (sig == RTLIL::State::S1)
510 netname = "VCC_NET";
511 else {
512 netname = log_signal(sig);
513 for (size_t i = 0; i < netname.size(); i++)
514 if (netname[i] == ' ' || netname[i] == '\\')
515 netname.erase(netname.begin() + i--);
516 }
517 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
518 for (auto &ref : it.second)
519 *f << stringf(" %s\n", ref.first.c_str());
520 if (sig.wire == NULL) {
521 if (nogndvcc)
522 log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
523 if (sig == RTLIL::State::S0)
524 *f << stringf(" (portRef %c (instanceRef GND))\n", gndvccy ? 'Y' : 'G');
525 if (sig == RTLIL::State::S1)
526 *f << stringf(" (portRef %c (instanceRef VCC))\n", gndvccy ? 'Y' : 'P');
527 }
528 *f << stringf(" )");
529 if (attr_properties && sig.wire != NULL)
530 for (auto &p : sig.wire->attributes)
531 add_prop(p.first, p.second);
532 *f << stringf("\n )\n");
533 }
534
535 for (auto wire : module->wires())
536 {
537 if (!wire->get_bool_attribute(ID::keep))
538 continue;
539
540 for(int i = 0; i < wire->width; i++)
541 {
542 SigBit raw_sig = RTLIL::SigSpec(wire, i);
543 SigBit mapped_sig = sigmap(raw_sig);
544
545 if (raw_sig == mapped_sig || net_join_db.count(mapped_sig) == 0)
546 continue;
547
548 std::string netname = log_signal(raw_sig);
549 for (size_t i = 0; i < netname.size(); i++)
550 if (netname[i] == ' ' || netname[i] == '\\')
551 netname.erase(netname.begin() + i--);
552
553 if (keepmode)
554 {
555 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
556
557 auto &refs = net_join_db.at(mapped_sig);
558 for (auto &ref : refs)
559 if (ref.second)
560 *f << stringf(" %s\n", ref.first.c_str());
561 *f << stringf(" )");
562
563 if (attr_properties && raw_sig.wire != NULL)
564 for (auto &p : raw_sig.wire->attributes)
565 add_prop(p.first, p.second);
566
567 *f << stringf("\n )\n");
568 }
569 else
570 {
571 log_warning("Ignoring conflicting 'keep' property on net %s. Use -keep to generate the extra net nevertheless.\n", EDIF_DEF(netname));
572 }
573 }
574 }
575
576 *f << stringf(" )\n");
577 *f << stringf(" )\n");
578 *f << stringf(" )\n");
579 }
580 *f << stringf(" )\n");
581
582 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
583 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
584 *f << stringf(" )\n");
585
586 *f << stringf(")\n");
587 }
588 } EdifBackend;
589
590 PRIVATE_NAMESPACE_END