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Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 USING_YOSYS_NAMESPACE
31 PRIVATE_NAMESPACE_BEGIN
32
33 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
34 #define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str()
35 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
36
37 struct EdifNames
38 {
39 int counter;
40 char delim_left, delim_right;
41 std::set<std::string> generated_names, used_names;
42 std::map<std::string, std::string> name_map;
43
44 EdifNames() : counter(1), delim_left('['), delim_right(']') { }
45
46 std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0)
47 {
48 if (define) {
49 std::string new_id = operator()(id, false);
50 if (port_rename)
51 return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right);
52 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
53 }
54
55 if (name_map.count(id) > 0)
56 return name_map.at(id);
57 if (generated_names.count(id) > 0)
58 goto do_rename;
59 if (id == "GND" || id == "VCC")
60 goto do_rename;
61
62 for (size_t i = 0; i < id.size(); i++) {
63 if ('A' <= id[i] && id[i] <= 'Z')
64 continue;
65 if ('a' <= id[i] && id[i] <= 'z')
66 continue;
67 if ('0' <= id[i] && id[i] <= '9' && i > 0)
68 continue;
69 if (id[i] == '_' && i > 0 && i != id.size()-1)
70 continue;
71 goto do_rename;
72 }
73
74 used_names.insert(id);
75 return id;
76
77 do_rename:;
78 std::string gen_name;
79 while (1) {
80 gen_name = stringf("id%05d", counter++);
81 if (generated_names.count(gen_name) == 0 &&
82 used_names.count(gen_name) == 0)
83 break;
84 }
85 generated_names.insert(gen_name);
86 name_map[id] = gen_name;
87 return gen_name;
88 }
89 };
90
91 struct EdifBackend : public Backend {
92 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
93 void help() YS_OVERRIDE
94 {
95 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
96 log("\n");
97 log(" write_edif [options] [filename]\n");
98 log("\n");
99 log("Write the current design to an EDIF netlist file.\n");
100 log("\n");
101 log(" -top top_module\n");
102 log(" set the specified module as design top module\n");
103 log("\n");
104 log(" -nogndvcc\n");
105 log(" do not create \"GND\" and \"VCC\" cells. (this will produce an error\n");
106 log(" if the design contains constant nets. use \"hilomap\" to map to custom\n");
107 log(" constant drivers first)\n");
108 log("\n");
109 log(" -gndvccy\n");
110 log(" create \"GND\" and \"VCC\" cells with \"Y\" outputs. (the default is \"G\"\n");
111 log(" for \"GND\" and \"P\" for \"VCC\".)\n");
112 log("\n");
113 log(" -attrprop\n");
114 log(" create EDIF properties for cell attributes\n");
115 log("\n");
116 log(" -pvector {par|bra|ang}\n");
117 log(" sets the delimiting character for module port rename clauses to\n");
118 log(" parentheses, square brackets, or angle brackets.\n");
119 log("\n");
120 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
121 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
122 log("necessary to make small modifications to this command when a different tool\n");
123 log("is targeted.\n");
124 log("\n");
125 }
126 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
127 {
128 log_header(design, "Executing EDIF backend.\n");
129 std::string top_module_name;
130 bool port_rename = false;
131 bool attr_properties = false;
132 std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
133 bool nogndvcc = false, gndvccy = false;
134 CellTypes ct(design);
135 EdifNames edif_names;
136
137 size_t argidx;
138 for (argidx = 1; argidx < args.size(); argidx++)
139 {
140 if (args[argidx] == "-top" && argidx+1 < args.size()) {
141 top_module_name = args[++argidx];
142 continue;
143 }
144 if (args[argidx] == "-nogndvcc") {
145 nogndvcc = true;
146 continue;
147 }
148 if (args[argidx] == "-gndvccy") {
149 gndvccy = true;
150 continue;
151 }
152 if (args[argidx] == "-attrprop") {
153 attr_properties = true;
154 continue;
155 }
156 if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
157 std::string parray;
158 port_rename = true;
159 parray = args[++argidx];
160 if (parray == "par") {
161 edif_names.delim_left = '(';edif_names.delim_right = ')';
162 } else if (parray == "ang") {
163 edif_names.delim_left = '<';edif_names.delim_right = '>';
164 } else {
165 edif_names.delim_left = '[';edif_names.delim_right = ']';
166 }
167 continue;
168 }
169 break;
170 }
171 extra_args(f, filename, args, argidx);
172
173 if (top_module_name.empty())
174 for (auto module : design->modules())
175 if (module->get_bool_attribute(ID::top))
176 top_module_name = module->name.str();
177
178 for (auto module : design->modules())
179 {
180 if (module->get_blackbox_attribute())
181 continue;
182
183 if (top_module_name.empty())
184 top_module_name = module->name.str();
185
186 if (module->processes.size() != 0)
187 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", log_id(module->name));
188 if (module->memories.size() != 0)
189 log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", log_id(module->name));
190
191 for (auto cell : module->cells())
192 {
193 if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
194 lib_cell_ports[cell->type];
195 for (auto p : cell->connections())
196 lib_cell_ports[cell->type][p.first] = GetSize(p.second);
197 }
198 }
199 }
200
201 if (top_module_name.empty())
202 log_error("No module found in design!\n");
203
204 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
205 *f << stringf(" (edifVersion 2 0 0)\n");
206 *f << stringf(" (edifLevel 0)\n");
207 *f << stringf(" (keywordMap (keywordLevel 0))\n");
208 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
209
210 *f << stringf(" (external LIB\n");
211 *f << stringf(" (edifLevel 0)\n");
212 *f << stringf(" (technology (numberDefinition))\n");
213
214 if (!nogndvcc)
215 {
216 *f << stringf(" (cell GND\n");
217 *f << stringf(" (cellType GENERIC)\n");
218 *f << stringf(" (view VIEW_NETLIST\n");
219 *f << stringf(" (viewType NETLIST)\n");
220 *f << stringf(" (interface (port %c (direction OUTPUT)))\n", gndvccy ? 'Y' : 'G');
221 *f << stringf(" )\n");
222 *f << stringf(" )\n");
223
224 *f << stringf(" (cell VCC\n");
225 *f << stringf(" (cellType GENERIC)\n");
226 *f << stringf(" (view VIEW_NETLIST\n");
227 *f << stringf(" (viewType NETLIST)\n");
228 *f << stringf(" (interface (port %c (direction OUTPUT)))\n", gndvccy ? 'Y' : 'P');
229 *f << stringf(" )\n");
230 *f << stringf(" )\n");
231 }
232
233 for (auto &cell_it : lib_cell_ports) {
234 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
235 *f << stringf(" (cellType GENERIC)\n");
236 *f << stringf(" (view VIEW_NETLIST\n");
237 *f << stringf(" (viewType NETLIST)\n");
238 *f << stringf(" (interface\n");
239 for (auto &port_it : cell_it.second) {
240 const char *dir = "INOUT";
241 if (ct.cell_known(cell_it.first)) {
242 if (!ct.cell_output(cell_it.first, port_it.first))
243 dir = "INPUT";
244 else if (!ct.cell_input(cell_it.first, port_it.first))
245 dir = "OUTPUT";
246 }
247 int width = port_it.second;
248 int start = 0;
249 bool upto = false;
250 auto m = design->module(cell_it.first);
251 if (m) {
252 auto w = m->wire(port_it.first);
253 if (w) {
254 width = GetSize(w);
255 start = w->start_offset;
256 upto = w->upto;
257 }
258 }
259 if (width == 1)
260 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
261 else {
262 int b[2];
263 b[upto ? 0 : 1] = start;
264 b[upto ? 1 : 0] = start+width-1;
265 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), width, dir);
266 }
267 }
268 *f << stringf(" )\n");
269 *f << stringf(" )\n");
270 *f << stringf(" )\n");
271 }
272 *f << stringf(" )\n");
273
274 std::vector<RTLIL::Module*> sorted_modules;
275
276 // extract module dependencies
277 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
278 for (auto module : design->modules()) {
279 module_deps[module] = std::set<RTLIL::Module*>();
280 for (auto cell : module->cells())
281 if (design->module(cell->type) != nullptr)
282 module_deps[module].insert(design->module(cell->type));
283 }
284
285 // simple good-enough topological sort
286 // (O(n*m) on n elements and depth m)
287 while (module_deps.size() > 0) {
288 size_t sorted_modules_idx = sorted_modules.size();
289 for (auto &it : module_deps) {
290 for (auto &dep : it.second)
291 if (module_deps.count(dep) > 0)
292 goto not_ready_yet;
293 // log("Next in topological sort: %s\n", log_id(it.first->name));
294 sorted_modules.push_back(it.first);
295 not_ready_yet:;
296 }
297 if (sorted_modules_idx == sorted_modules.size())
298 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name));
299 while (sorted_modules_idx < sorted_modules.size())
300 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
301 }
302
303
304 *f << stringf(" (library DESIGN\n");
305 *f << stringf(" (edifLevel 0)\n");
306 *f << stringf(" (technology (numberDefinition))\n");
307
308 auto add_prop = [&](IdString name, Const val) {
309 if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
310 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
311 else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
312 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
313 else {
314 std::string hex_string = "";
315 for (size_t i = 0; i < val.bits.size(); i += 4) {
316 int digit_value = 0;
317 if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
318 if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
319 if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
320 if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
321 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
322 hex_string = std::string(digit_str) + hex_string;
323 }
324 *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
325 }
326 };
327 for (auto module : sorted_modules)
328 {
329 if (module->get_blackbox_attribute())
330 continue;
331
332 SigMap sigmap(module);
333 std::map<RTLIL::SigSpec, std::set<std::pair<std::string, bool>>> net_join_db;
334
335 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
336 *f << stringf(" (cellType GENERIC)\n");
337 *f << stringf(" (view VIEW_NETLIST\n");
338 *f << stringf(" (viewType NETLIST)\n");
339 *f << stringf(" (interface\n");
340 for (auto wire : module->wires()) {
341 if (wire->port_id == 0)
342 continue;
343 const char *dir = "INOUT";
344 if (!wire->port_output)
345 dir = "INPUT";
346 else if (!wire->port_input)
347 dir = "OUTPUT";
348 if (wire->width == 1) {
349 *f << stringf(" (port %s (direction %s)", EDIF_DEF(wire->name), dir);
350 if (attr_properties)
351 for (auto &p : wire->attributes)
352 add_prop(p.first, p.second);
353 *f << ")\n";
354 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
355 net_join_db[sig].insert(make_pair(stringf("(portRef %s)", EDIF_REF(wire->name)), wire->port_input));
356 } else {
357 int b[2];
358 b[wire->upto ? 0 : 1] = wire->start_offset;
359 b[wire->upto ? 1 : 0] = wire->start_offset + GetSize(wire) - 1;
360 *f << stringf(" (port (array %s %d) (direction %s)", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
361 if (attr_properties)
362 for (auto &p : wire->attributes)
363 add_prop(p.first, p.second);
364
365 *f << ")\n";
366 for (int i = 0; i < wire->width; i++) {
367 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
368 net_join_db[sig].insert(make_pair(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1), wire->port_input));
369 }
370 }
371 }
372 *f << stringf(" )\n");
373 *f << stringf(" (contents\n");
374 if (!nogndvcc) {
375 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
376 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
377 }
378 for (auto cell : module->cells()) {
379 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
380 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
381 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
382 for (auto &p : cell->parameters)
383 add_prop(p.first, p.second);
384 if (attr_properties)
385 for (auto &p : cell->attributes)
386 add_prop(p.first, p.second);
387
388 *f << stringf(")\n");
389 for (auto &p : cell->connections()) {
390 RTLIL::SigSpec sig = sigmap(p.second);
391 for (int i = 0; i < GetSize(sig); i++)
392 if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1)
393 log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n",
394 i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i]));
395 else {
396 int member_idx = GetSize(sig)-i-1;
397 auto m = design->module(cell->type);
398 int width = sig.size();
399 if (m) {
400 auto w = m->wire(p.first);
401 if (w) {
402 member_idx = GetSize(w)-i-1;
403 width = GetSize(w);
404 }
405 }
406 if (width == 1)
407 net_join_db[sig[i]].insert(make_pair(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)), cell->output(p.first)));
408 else {
409 net_join_db[sig[i]].insert(make_pair(stringf("(portRef (member %s %d) (instanceRef %s))",
410 EDIF_REF(p.first), member_idx, EDIF_REF(cell->name)), cell->output(p.first)));
411 }
412 }
413 }
414 }
415 for (auto &it : net_join_db) {
416 RTLIL::SigBit sig = it.first;
417 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
418 if (sig == RTLIL::State::Sx) {
419 for (auto &ref : it.second)
420 log_warning("Exporting x-bit on %s as zero bit.\n", ref.first.c_str());
421 sig = RTLIL::State::S0;
422 } else if (sig == RTLIL::State::Sz) {
423 continue;
424 } else {
425 for (auto &ref : it.second)
426 log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first.c_str());
427 log_abort();
428 }
429 }
430 std::string netname;
431 if (sig == RTLIL::State::S0)
432 netname = "GND_NET";
433 else if (sig == RTLIL::State::S1)
434 netname = "VCC_NET";
435 else {
436 netname = log_signal(sig);
437 for (size_t i = 0; i < netname.size(); i++)
438 if (netname[i] == ' ' || netname[i] == '\\')
439 netname.erase(netname.begin() + i--);
440 }
441 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
442 for (auto &ref : it.second)
443 *f << stringf(" %s\n", ref.first.c_str());
444 if (sig.wire == NULL) {
445 if (nogndvcc)
446 log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
447 if (sig == RTLIL::State::S0)
448 *f << stringf(" (portRef %c (instanceRef GND))\n", gndvccy ? 'Y' : 'G');
449 if (sig == RTLIL::State::S1)
450 *f << stringf(" (portRef %c (instanceRef VCC))\n", gndvccy ? 'Y' : 'P');
451 }
452 *f << stringf(" )");
453 if (attr_properties && sig.wire != NULL)
454 for (auto &p : sig.wire->attributes)
455 add_prop(p.first, p.second);
456 *f << stringf("\n )\n");
457 }
458 for (auto wire : module->wires()) {
459 if (!wire->get_bool_attribute(ID::keep))
460 continue;
461 for(int i = 0; i < wire->width; i++) {
462 SigBit raw_sig = RTLIL::SigSpec(wire, i);
463 SigBit mapped_sig = sigmap(raw_sig);
464 if (raw_sig == mapped_sig || net_join_db.count(mapped_sig) == 0)
465 continue;
466 std::string netname = log_signal(raw_sig);
467 for (size_t i = 0; i < netname.size(); i++)
468 if (netname[i] == ' ' || netname[i] == '\\')
469 netname.erase(netname.begin() + i--);
470 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
471 auto &refs = net_join_db.at(mapped_sig);
472 for (auto &ref : refs)
473 if (ref.second)
474 *f << stringf(" %s\n", ref.first.c_str());
475 *f << stringf(" )");
476 if (attr_properties && raw_sig.wire != NULL)
477 for (auto &p : raw_sig.wire->attributes)
478 add_prop(p.first, p.second);
479 *f << stringf("\n )\n");
480 }
481 }
482 *f << stringf(" )\n");
483 *f << stringf(" )\n");
484 *f << stringf(" )\n");
485 }
486 *f << stringf(" )\n");
487
488 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
489 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
490 *f << stringf(" )\n");
491
492 *f << stringf(")\n");
493 }
494 } EdifBackend;
495
496 PRIVATE_NAMESPACE_END