projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29 #include <assert.h>
30
31 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
32 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
33
34 namespace
35 {
36 struct EdifNames
37 {
38 int counter;
39 std::set<std::string> generated_names, used_names;
40 std::map<std::string, std::string> name_map;
41
42 EdifNames() : counter(1) { }
43
44 std::string operator()(std::string id, bool define)
45 {
46 if (define) {
47 std::string new_id = operator()(id, false);
48 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
49 }
50
51 if (name_map.count(id) > 0)
52 return name_map.at(id);
53 if (generated_names.count(id) > 0)
54 goto do_rename;
55 if (id == "GND" || id == "VCC")
56 goto do_rename;
57
58 for (size_t i = 0; i < id.size(); i++) {
59 if ('A' <= id[i] && id[i] <= 'Z')
60 continue;
61 if ('a' <= id[i] && id[i] <= 'z')
62 continue;
63 if ('0' <= id[i] && id[i] <= '9' && i > 0)
64 continue;
65 if (id[i] == '_' && i > 0 && i != id.size()-1)
66 continue;
67 goto do_rename;
68 }
69
70 used_names.insert(id);
71 return id;
72
73 do_rename:;
74 std::string gen_name;
75 while (1) {
76 gen_name = stringf("id%05d", counter++);
77 if (generated_names.count(gen_name) == 0 &&
78 used_names.count(gen_name) == 0)
79 break;
80 }
81 generated_names.insert(gen_name);
82 name_map[id] = gen_name;
83 return gen_name;
84 }
85 };
86 }
87
88 struct EdifBackend : public Backend {
89 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
90 virtual void help()
91 {
92 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
93 log("\n");
94 log(" write_edif [options] [filename]\n");
95 log("\n");
96 log("Write the current design to an EDIF netlist file.\n");
97 log("\n");
98 log(" -top top_module\n");
99 log(" set the specified module as design top module\n");
100 log("\n");
101 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
102 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
103 log("necessary to make small modifications to this command when a different tool\n");
104 log("is targeted.\n");
105 log("\n");
106 }
107 virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
108 {
109 log_header("Executing EDIF backend.\n");
110
111 std::string top_module_name;
112 std::map<std::string, std::set<std::string>> lib_cell_ports;
113 CellTypes ct(design);
114 EdifNames edif_names;
115
116 size_t argidx;
117 for (argidx = 1; argidx < args.size(); argidx++)
118 {
119 if (args[argidx] == "-top" && argidx+1 < args.size()) {
120 top_module_name = args[++argidx];
121 continue;
122 }
123 break;
124 }
125 extra_args(f, filename, args, argidx);
126
127 if (top_module_name.empty())
128 for (auto & mod_it:design->modules)
129 if (mod_it.second->get_bool_attribute("\\top"))
130 top_module_name = mod_it.first;
131
132 for (auto module_it : design->modules)
133 {
134 RTLIL::Module *module = module_it.second;
135 if (module->get_bool_attribute("\\blackbox"))
136 continue;
137
138 if (top_module_name.empty())
139 top_module_name = module->name;
140
141 if (module->processes.size() != 0)
142 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
143 if (module->memories.size() != 0)
144 log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
145
146 for (auto cell_it : module->cells)
147 {
148 RTLIL::Cell *cell = cell_it.second;
149 if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
150 lib_cell_ports[cell->type];
151 for (auto p : cell->connections) {
152 if (p.second.size() > 1)
153 log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
154 RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
155 lib_cell_ports[cell->type].insert(p.first);
156 }
157 }
158 }
159 }
160
161 if (top_module_name.empty())
162 log_error("No module found in design!\n");
163
164 fprintf(f, "(edif %s\n", EDIF_DEF(top_module_name));
165 fprintf(f, " (edifVersion 2 0 0)\n");
166 fprintf(f, " (edifLevel 0)\n");
167 fprintf(f, " (keywordMap (keywordLevel 0))\n");
168 fprintf(f, " (comment \"Generated by %s\")\n", yosys_version_str);
169
170 fprintf(f, " (external LIB\n");
171 fprintf(f, " (edifLevel 0)\n");
172 fprintf(f, " (technology (numberDefinition))\n");
173
174 fprintf(f, " (cell GND\n");
175 fprintf(f, " (cellType GENERIC)\n");
176 fprintf(f, " (view VIEW_NETLIST\n");
177 fprintf(f, " (viewType NETLIST)\n");
178 fprintf(f, " (interface (port G (direction OUTPUT)))\n");
179 fprintf(f, " )\n");
180 fprintf(f, " )\n");
181
182 fprintf(f, " (cell VCC\n");
183 fprintf(f, " (cellType GENERIC)\n");
184 fprintf(f, " (view VIEW_NETLIST\n");
185 fprintf(f, " (viewType NETLIST)\n");
186 fprintf(f, " (interface (port P (direction OUTPUT)))\n");
187 fprintf(f, " )\n");
188 fprintf(f, " )\n");
189
190 for (auto &cell_it : lib_cell_ports) {
191 fprintf(f, " (cell %s\n", EDIF_DEF(cell_it.first));
192 fprintf(f, " (cellType GENERIC)\n");
193 fprintf(f, " (view VIEW_NETLIST\n");
194 fprintf(f, " (viewType NETLIST)\n");
195 fprintf(f, " (interface\n");
196 for (auto &port_it : cell_it.second) {
197 const char *dir = "INOUT";
198 if (ct.cell_known(cell_it.first)) {
199 if (!ct.cell_output(cell_it.first, port_it))
200 dir = "INPUT";
201 else if (!ct.cell_input(cell_it.first, port_it))
202 dir = "OUTPUT";
203 }
204 fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(port_it), dir);
205 }
206 fprintf(f, " )\n");
207 fprintf(f, " )\n");
208 fprintf(f, " )\n");
209 }
210 fprintf(f, " )\n");
211
212 std::vector<RTLIL::Module*> sorted_modules;
213
214 // extract module dependencies
215 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
216 for (auto &mod_it : design->modules) {
217 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
218 for (auto &cell_it : mod_it.second->cells)
219 if (design->modules.count(cell_it.second->type) > 0)
220 module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
221 }
222
223 // simple good-enough topological sort
224 // (O(n*m) on n elements and depth m)
225 while (module_deps.size() > 0) {
226 size_t sorted_modules_idx = sorted_modules.size();
227 for (auto &it : module_deps) {
228 for (auto &dep : it.second)
229 if (module_deps.count(dep) > 0)
230 goto not_ready_yet;
231 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
232 sorted_modules.push_back(it.first);
233 not_ready_yet:;
234 }
235 if (sorted_modules_idx == sorted_modules.size())
236 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
237 while (sorted_modules_idx < sorted_modules.size())
238 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
239 }
240
241
242 fprintf(f, " (library DESIGN\n");
243 fprintf(f, " (edifLevel 0)\n");
244 fprintf(f, " (technology (numberDefinition))\n");
245 for (auto module : sorted_modules)
246 {
247 if (module->get_bool_attribute("\\blackbox"))
248 continue;
249
250 SigMap sigmap(module);
251 std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
252
253 fprintf(f, " (cell %s\n", EDIF_DEF(module->name));
254 fprintf(f, " (cellType GENERIC)\n");
255 fprintf(f, " (view VIEW_NETLIST\n");
256 fprintf(f, " (viewType NETLIST)\n");
257 fprintf(f, " (interface\n");
258 for (auto &wire_it : module->wires) {
259 RTLIL::Wire *wire = wire_it.second;
260 if (wire->port_id == 0)
261 continue;
262 const char *dir = "INOUT";
263 if (!wire->port_output)
264 dir = "INPUT";
265 else if (!wire->port_input)
266 dir = "OUTPUT";
267 if (wire->width == 1) {
268 fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
269 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
270 net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
271 } else {
272 fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
273 for (int i = 0; i < wire->width; i++) {
274 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
275 net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
276 }
277 }
278 }
279 fprintf(f, " )\n");
280 fprintf(f, " (contents\n");
281 fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
282 fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
283 for (auto &cell_it : module->cells) {
284 RTLIL::Cell *cell = cell_it.second;
285 fprintf(f, " (instance %s\n", EDIF_DEF(cell->name));
286 fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
287 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
288 for (auto &p : cell->parameters)
289 if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
290 fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
291 else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
292 fprintf(f, "\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
293 else {
294 std::string hex_string = "";
295 for (size_t i = 0; i < p.second.bits.size(); i += 4) {
296 int digit_value = 0;
297 if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
298 if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
299 if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
300 if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
301 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
302 hex_string = std::string(digit_str) + hex_string;
303 }
304 fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str());
305 }
306 fprintf(f, ")\n");
307 for (auto &p : cell->connections) {
308 RTLIL::SigSpec sig = sigmap(p.second);
309 sig.expand();
310 for (int i = 0; i < sig.size(); i++) {
311 RTLIL::SigSpec sigbit(sig.chunks().at(i));
312 if (sig.size() == 1)
313 net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
314 else
315 net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
316 }
317 }
318 }
319 for (auto &it : net_join_db) {
320 RTLIL::SigSpec sig = it.first;
321 sig.optimize();
322 log_assert(sig.size() == 1);
323 if (sig.chunks().at(0).wire == NULL) {
324 if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1)
325 continue;
326 }
327 std::string netname = log_signal(sig);
328 for (size_t i = 0; i < netname.size(); i++)
329 if (netname[i] == ' ' || netname[i] == '\\')
330 netname.erase(netname.begin() + i--);
331 fprintf(f, " (net %s (joined\n", EDIF_DEF(netname));
332 for (auto &ref : it.second)
333 fprintf(f, " %s\n", ref.c_str());
334 if (sig.chunks().at(0).wire == NULL) {
335 if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0)
336 fprintf(f, " (portRef G (instanceRef GND))\n");
337 if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1)
338 fprintf(f, " (portRef P (instanceRef VCC))\n");
339 }
340 fprintf(f, " ))\n");
341 }
342 fprintf(f, " )\n");
343 fprintf(f, " )\n");
344 fprintf(f, " )\n");
345 }
346 fprintf(f, " )\n");
347
348 fprintf(f, " (design %s\n", EDIF_DEF(top_module_name));
349 fprintf(f, " (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
350 fprintf(f, " )\n");
351
352 fprintf(f, ")\n");
353 }
354 } EdifBackend;
355