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Changed backend-api from FILE to std::ostream
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
31 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
32
33 namespace
34 {
35 struct EdifNames
36 {
37 int counter;
38 std::set<std::string> generated_names, used_names;
39 std::map<std::string, std::string> name_map;
40
41 EdifNames() : counter(1) { }
42
43 std::string operator()(std::string id, bool define)
44 {
45 if (define) {
46 std::string new_id = operator()(id, false);
47 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
48 }
49
50 if (name_map.count(id) > 0)
51 return name_map.at(id);
52 if (generated_names.count(id) > 0)
53 goto do_rename;
54 if (id == "GND" || id == "VCC")
55 goto do_rename;
56
57 for (size_t i = 0; i < id.size(); i++) {
58 if ('A' <= id[i] && id[i] <= 'Z')
59 continue;
60 if ('a' <= id[i] && id[i] <= 'z')
61 continue;
62 if ('0' <= id[i] && id[i] <= '9' && i > 0)
63 continue;
64 if (id[i] == '_' && i > 0 && i != id.size()-1)
65 continue;
66 goto do_rename;
67 }
68
69 used_names.insert(id);
70 return id;
71
72 do_rename:;
73 std::string gen_name;
74 while (1) {
75 gen_name = stringf("id%05d", counter++);
76 if (generated_names.count(gen_name) == 0 &&
77 used_names.count(gen_name) == 0)
78 break;
79 }
80 generated_names.insert(gen_name);
81 name_map[id] = gen_name;
82 return gen_name;
83 }
84 };
85 }
86
87 struct EdifBackend : public Backend {
88 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
89 virtual void help()
90 {
91 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
92 log("\n");
93 log(" write_edif [options] [filename]\n");
94 log("\n");
95 log("Write the current design to an EDIF netlist file.\n");
96 log("\n");
97 log(" -top top_module\n");
98 log(" set the specified module as design top module\n");
99 log("\n");
100 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
101 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
102 log("necessary to make small modifications to this command when a different tool\n");
103 log("is targeted.\n");
104 log("\n");
105 }
106 virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
107 {
108 log_header("Executing EDIF backend.\n");
109
110 std::string top_module_name;
111 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> lib_cell_ports;
112 CellTypes ct(design);
113 EdifNames edif_names;
114
115 size_t argidx;
116 for (argidx = 1; argidx < args.size(); argidx++)
117 {
118 if (args[argidx] == "-top" && argidx+1 < args.size()) {
119 top_module_name = args[++argidx];
120 continue;
121 }
122 break;
123 }
124 extra_args(f, filename, args, argidx);
125
126 if (top_module_name.empty())
127 for (auto & mod_it:design->modules_)
128 if (mod_it.second->get_bool_attribute("\\top"))
129 top_module_name = mod_it.first.str();
130
131 for (auto module_it : design->modules_)
132 {
133 RTLIL::Module *module = module_it.second;
134 if (module->get_bool_attribute("\\blackbox"))
135 continue;
136
137 if (top_module_name.empty())
138 top_module_name = module->name.str();
139
140 if (module->processes.size() != 0)
141 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
142 if (module->memories.size() != 0)
143 log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
144
145 for (auto cell_it : module->cells_)
146 {
147 RTLIL::Cell *cell = cell_it.second;
148 if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
149 lib_cell_ports[cell->type];
150 for (auto p : cell->connections()) {
151 if (p.second.size() > 1)
152 log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
153 RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
154 lib_cell_ports[cell->type].insert(p.first);
155 }
156 }
157 }
158 }
159
160 if (top_module_name.empty())
161 log_error("No module found in design!\n");
162
163 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
164 *f << stringf(" (edifVersion 2 0 0)\n");
165 *f << stringf(" (edifLevel 0)\n");
166 *f << stringf(" (keywordMap (keywordLevel 0))\n");
167 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
168
169 *f << stringf(" (external LIB\n");
170 *f << stringf(" (edifLevel 0)\n");
171 *f << stringf(" (technology (numberDefinition))\n");
172
173 *f << stringf(" (cell GND\n");
174 *f << stringf(" (cellType GENERIC)\n");
175 *f << stringf(" (view VIEW_NETLIST\n");
176 *f << stringf(" (viewType NETLIST)\n");
177 *f << stringf(" (interface (port G (direction OUTPUT)))\n");
178 *f << stringf(" )\n");
179 *f << stringf(" )\n");
180
181 *f << stringf(" (cell VCC\n");
182 *f << stringf(" (cellType GENERIC)\n");
183 *f << stringf(" (view VIEW_NETLIST\n");
184 *f << stringf(" (viewType NETLIST)\n");
185 *f << stringf(" (interface (port P (direction OUTPUT)))\n");
186 *f << stringf(" )\n");
187 *f << stringf(" )\n");
188
189 for (auto &cell_it : lib_cell_ports) {
190 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
191 *f << stringf(" (cellType GENERIC)\n");
192 *f << stringf(" (view VIEW_NETLIST\n");
193 *f << stringf(" (viewType NETLIST)\n");
194 *f << stringf(" (interface\n");
195 for (auto &port_it : cell_it.second) {
196 const char *dir = "INOUT";
197 if (ct.cell_known(cell_it.first)) {
198 if (!ct.cell_output(cell_it.first, port_it))
199 dir = "INPUT";
200 else if (!ct.cell_input(cell_it.first, port_it))
201 dir = "OUTPUT";
202 }
203 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it), dir);
204 }
205 *f << stringf(" )\n");
206 *f << stringf(" )\n");
207 *f << stringf(" )\n");
208 }
209 *f << stringf(" )\n");
210
211 std::vector<RTLIL::Module*> sorted_modules;
212
213 // extract module dependencies
214 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
215 for (auto &mod_it : design->modules_) {
216 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
217 for (auto &cell_it : mod_it.second->cells_)
218 if (design->modules_.count(cell_it.second->type) > 0)
219 module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
220 }
221
222 // simple good-enough topological sort
223 // (O(n*m) on n elements and depth m)
224 while (module_deps.size() > 0) {
225 size_t sorted_modules_idx = sorted_modules.size();
226 for (auto &it : module_deps) {
227 for (auto &dep : it.second)
228 if (module_deps.count(dep) > 0)
229 goto not_ready_yet;
230 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
231 sorted_modules.push_back(it.first);
232 not_ready_yet:;
233 }
234 if (sorted_modules_idx == sorted_modules.size())
235 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
236 while (sorted_modules_idx < sorted_modules.size())
237 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
238 }
239
240
241 *f << stringf(" (library DESIGN\n");
242 *f << stringf(" (edifLevel 0)\n");
243 *f << stringf(" (technology (numberDefinition))\n");
244 for (auto module : sorted_modules)
245 {
246 if (module->get_bool_attribute("\\blackbox"))
247 continue;
248
249 SigMap sigmap(module);
250 std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
251
252 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
253 *f << stringf(" (cellType GENERIC)\n");
254 *f << stringf(" (view VIEW_NETLIST\n");
255 *f << stringf(" (viewType NETLIST)\n");
256 *f << stringf(" (interface\n");
257 for (auto &wire_it : module->wires_) {
258 RTLIL::Wire *wire = wire_it.second;
259 if (wire->port_id == 0)
260 continue;
261 const char *dir = "INOUT";
262 if (!wire->port_output)
263 dir = "INPUT";
264 else if (!wire->port_input)
265 dir = "OUTPUT";
266 if (wire->width == 1) {
267 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
268 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
269 net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
270 } else {
271 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
272 for (int i = 0; i < wire->width; i++) {
273 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
274 net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
275 }
276 }
277 }
278 *f << stringf(" )\n");
279 *f << stringf(" (contents\n");
280 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
281 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
282 for (auto &cell_it : module->cells_) {
283 RTLIL::Cell *cell = cell_it.second;
284 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
285 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
286 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
287 for (auto &p : cell->parameters)
288 if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
289 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
290 else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
291 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
292 else {
293 std::string hex_string = "";
294 for (size_t i = 0; i < p.second.bits.size(); i += 4) {
295 int digit_value = 0;
296 if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
297 if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
298 if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
299 if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
300 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
301 hex_string = std::string(digit_str) + hex_string;
302 }
303 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str());
304 }
305 *f << stringf(")\n");
306 for (auto &p : cell->connections()) {
307 RTLIL::SigSpec sig = sigmap(p.second);
308 for (int i = 0; i < SIZE(sig); i++)
309 if (sig.size() == 1)
310 net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
311 else
312 net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
313 }
314 }
315 for (auto &it : net_join_db) {
316 RTLIL::SigBit sig = it.first;
317 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
318 continue;
319 std::string netname = log_signal(sig);
320 for (size_t i = 0; i < netname.size(); i++)
321 if (netname[i] == ' ' || netname[i] == '\\')
322 netname.erase(netname.begin() + i--);
323 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
324 for (auto &ref : it.second)
325 *f << stringf(" %s\n", ref.c_str());
326 if (sig.wire == NULL) {
327 if (sig == RTLIL::State::S0)
328 *f << stringf(" (portRef G (instanceRef GND))\n");
329 if (sig == RTLIL::State::S1)
330 *f << stringf(" (portRef P (instanceRef VCC))\n");
331 }
332 *f << stringf(" ))\n");
333 }
334 *f << stringf(" )\n");
335 *f << stringf(" )\n");
336 *f << stringf(" )\n");
337 }
338 *f << stringf(" )\n");
339
340 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
341 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
342 *f << stringf(" )\n");
343
344 *f << stringf(")\n");
345 }
346 } EdifBackend;
347