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Added EDIF backend support for multi-bit cell ports
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 USING_YOSYS_NAMESPACE
31 PRIVATE_NAMESPACE_BEGIN
32
33 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
34 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
35
36 namespace
37 {
38 struct EdifNames
39 {
40 int counter;
41 std::set<std::string> generated_names, used_names;
42 std::map<std::string, std::string> name_map;
43
44 EdifNames() : counter(1) { }
45
46 std::string operator()(std::string id, bool define)
47 {
48 if (define) {
49 std::string new_id = operator()(id, false);
50 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
51 }
52
53 if (name_map.count(id) > 0)
54 return name_map.at(id);
55 if (generated_names.count(id) > 0)
56 goto do_rename;
57 if (id == "GND" || id == "VCC")
58 goto do_rename;
59
60 for (size_t i = 0; i < id.size(); i++) {
61 if ('A' <= id[i] && id[i] <= 'Z')
62 continue;
63 if ('a' <= id[i] && id[i] <= 'z')
64 continue;
65 if ('0' <= id[i] && id[i] <= '9' && i > 0)
66 continue;
67 if (id[i] == '_' && i > 0 && i != id.size()-1)
68 continue;
69 goto do_rename;
70 }
71
72 used_names.insert(id);
73 return id;
74
75 do_rename:;
76 std::string gen_name;
77 while (1) {
78 gen_name = stringf("id%05d", counter++);
79 if (generated_names.count(gen_name) == 0 &&
80 used_names.count(gen_name) == 0)
81 break;
82 }
83 generated_names.insert(gen_name);
84 name_map[id] = gen_name;
85 return gen_name;
86 }
87 };
88 }
89
90 struct EdifBackend : public Backend {
91 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
92 virtual void help()
93 {
94 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
95 log("\n");
96 log(" write_edif [options] [filename]\n");
97 log("\n");
98 log("Write the current design to an EDIF netlist file.\n");
99 log("\n");
100 log(" -top top_module\n");
101 log(" set the specified module as design top module\n");
102 log("\n");
103 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
104 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
105 log("necessary to make small modifications to this command when a different tool\n");
106 log("is targeted.\n");
107 log("\n");
108 }
109 virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
110 {
111 log_header("Executing EDIF backend.\n");
112
113 std::string top_module_name;
114 std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
115 CellTypes ct(design);
116 EdifNames edif_names;
117
118 size_t argidx;
119 for (argidx = 1; argidx < args.size(); argidx++)
120 {
121 if (args[argidx] == "-top" && argidx+1 < args.size()) {
122 top_module_name = args[++argidx];
123 continue;
124 }
125 break;
126 }
127 extra_args(f, filename, args, argidx);
128
129 if (top_module_name.empty())
130 for (auto & mod_it:design->modules_)
131 if (mod_it.second->get_bool_attribute("\\top"))
132 top_module_name = mod_it.first.str();
133
134 for (auto module_it : design->modules_)
135 {
136 RTLIL::Module *module = module_it.second;
137 if (module->get_bool_attribute("\\blackbox"))
138 continue;
139
140 if (top_module_name.empty())
141 top_module_name = module->name.str();
142
143 if (module->processes.size() != 0)
144 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
145 if (module->memories.size() != 0)
146 log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
147
148 for (auto cell_it : module->cells_)
149 {
150 RTLIL::Cell *cell = cell_it.second;
151 if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
152 lib_cell_ports[cell->type];
153 for (auto p : cell->connections())
154 lib_cell_ports[cell->type][p.first] = GetSize(p.second);
155 }
156 }
157 }
158
159 if (top_module_name.empty())
160 log_error("No module found in design!\n");
161
162 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
163 *f << stringf(" (edifVersion 2 0 0)\n");
164 *f << stringf(" (edifLevel 0)\n");
165 *f << stringf(" (keywordMap (keywordLevel 0))\n");
166 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
167
168 *f << stringf(" (external LIB\n");
169 *f << stringf(" (edifLevel 0)\n");
170 *f << stringf(" (technology (numberDefinition))\n");
171
172 *f << stringf(" (cell GND\n");
173 *f << stringf(" (cellType GENERIC)\n");
174 *f << stringf(" (view VIEW_NETLIST\n");
175 *f << stringf(" (viewType NETLIST)\n");
176 *f << stringf(" (interface (port G (direction OUTPUT)))\n");
177 *f << stringf(" )\n");
178 *f << stringf(" )\n");
179
180 *f << stringf(" (cell VCC\n");
181 *f << stringf(" (cellType GENERIC)\n");
182 *f << stringf(" (view VIEW_NETLIST\n");
183 *f << stringf(" (viewType NETLIST)\n");
184 *f << stringf(" (interface (port P (direction OUTPUT)))\n");
185 *f << stringf(" )\n");
186 *f << stringf(" )\n");
187
188 for (auto &cell_it : lib_cell_ports) {
189 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
190 *f << stringf(" (cellType GENERIC)\n");
191 *f << stringf(" (view VIEW_NETLIST\n");
192 *f << stringf(" (viewType NETLIST)\n");
193 *f << stringf(" (interface\n");
194 for (auto &port_it : cell_it.second) {
195 const char *dir = "INOUT";
196 if (ct.cell_known(cell_it.first)) {
197 if (!ct.cell_output(cell_it.first, port_it.first))
198 dir = "INPUT";
199 else if (!ct.cell_input(cell_it.first, port_it.first))
200 dir = "OUTPUT";
201 }
202 if (port_it.second == 1)
203 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
204 else
205 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(port_it.first), port_it.second, dir);
206 }
207 *f << stringf(" )\n");
208 *f << stringf(" )\n");
209 *f << stringf(" )\n");
210 }
211 *f << stringf(" )\n");
212
213 std::vector<RTLIL::Module*> sorted_modules;
214
215 // extract module dependencies
216 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
217 for (auto &mod_it : design->modules_) {
218 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
219 for (auto &cell_it : mod_it.second->cells_)
220 if (design->modules_.count(cell_it.second->type) > 0)
221 module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
222 }
223
224 // simple good-enough topological sort
225 // (O(n*m) on n elements and depth m)
226 while (module_deps.size() > 0) {
227 size_t sorted_modules_idx = sorted_modules.size();
228 for (auto &it : module_deps) {
229 for (auto &dep : it.second)
230 if (module_deps.count(dep) > 0)
231 goto not_ready_yet;
232 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
233 sorted_modules.push_back(it.first);
234 not_ready_yet:;
235 }
236 if (sorted_modules_idx == sorted_modules.size())
237 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
238 while (sorted_modules_idx < sorted_modules.size())
239 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
240 }
241
242
243 *f << stringf(" (library DESIGN\n");
244 *f << stringf(" (edifLevel 0)\n");
245 *f << stringf(" (technology (numberDefinition))\n");
246 for (auto module : sorted_modules)
247 {
248 if (module->get_bool_attribute("\\blackbox"))
249 continue;
250
251 SigMap sigmap(module);
252 std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
253
254 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
255 *f << stringf(" (cellType GENERIC)\n");
256 *f << stringf(" (view VIEW_NETLIST\n");
257 *f << stringf(" (viewType NETLIST)\n");
258 *f << stringf(" (interface\n");
259 for (auto &wire_it : module->wires_) {
260 RTLIL::Wire *wire = wire_it.second;
261 if (wire->port_id == 0)
262 continue;
263 const char *dir = "INOUT";
264 if (!wire->port_output)
265 dir = "INPUT";
266 else if (!wire->port_input)
267 dir = "OUTPUT";
268 if (wire->width == 1) {
269 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
270 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
271 net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
272 } else {
273 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
274 for (int i = 0; i < wire->width; i++) {
275 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
276 net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
277 }
278 }
279 }
280 *f << stringf(" )\n");
281 *f << stringf(" (contents\n");
282 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
283 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
284 for (auto &cell_it : module->cells_) {
285 RTLIL::Cell *cell = cell_it.second;
286 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
287 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
288 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
289 for (auto &p : cell->parameters)
290 if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
291 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
292 else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
293 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
294 else {
295 std::string hex_string = "";
296 for (size_t i = 0; i < p.second.bits.size(); i += 4) {
297 int digit_value = 0;
298 if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
299 if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
300 if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
301 if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
302 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
303 hex_string = std::string(digit_str) + hex_string;
304 }
305 *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
306 }
307 *f << stringf(")\n");
308 for (auto &p : cell->connections()) {
309 RTLIL::SigSpec sig = sigmap(p.second);
310 for (int i = 0; i < GetSize(sig); i++)
311 if (sig.size() == 1)
312 net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
313 else
314 net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
315 }
316 }
317 for (auto &it : net_join_db) {
318 RTLIL::SigBit sig = it.first;
319 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
320 continue;
321 std::string netname = log_signal(sig);
322 for (size_t i = 0; i < netname.size(); i++)
323 if (netname[i] == ' ' || netname[i] == '\\')
324 netname.erase(netname.begin() + i--);
325 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
326 for (auto &ref : it.second)
327 *f << stringf(" %s\n", ref.c_str());
328 if (sig.wire == NULL) {
329 if (sig == RTLIL::State::S0)
330 *f << stringf(" (portRef G (instanceRef GND))\n");
331 if (sig == RTLIL::State::S1)
332 *f << stringf(" (portRef P (instanceRef VCC))\n");
333 }
334 *f << stringf(" ))\n");
335 }
336 *f << stringf(" )\n");
337 *f << stringf(" )\n");
338 *f << stringf(" )\n");
339 }
340 *f << stringf(" )\n");
341
342 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
343 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
344 *f << stringf(" )\n");
345
346 *f << stringf(")\n");
347 }
348 } EdifBackend;
349
350 PRIVATE_NAMESPACE_END