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Merge pull request #658 from daveshah1/ecp5_bram
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 USING_YOSYS_NAMESPACE
31 PRIVATE_NAMESPACE_BEGIN
32
33 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
34 #define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str()
35 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
36
37 struct EdifNames
38 {
39 int counter;
40 char delim_left, delim_right;
41 std::set<std::string> generated_names, used_names;
42 std::map<std::string, std::string> name_map;
43
44 EdifNames() : counter(1), delim_left('['), delim_right(']') { }
45
46 std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0)
47 {
48 if (define) {
49 std::string new_id = operator()(id, false);
50 if (port_rename)
51 return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right);
52 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
53 }
54
55 if (name_map.count(id) > 0)
56 return name_map.at(id);
57 if (generated_names.count(id) > 0)
58 goto do_rename;
59 if (id == "GND" || id == "VCC")
60 goto do_rename;
61
62 for (size_t i = 0; i < id.size(); i++) {
63 if ('A' <= id[i] && id[i] <= 'Z')
64 continue;
65 if ('a' <= id[i] && id[i] <= 'z')
66 continue;
67 if ('0' <= id[i] && id[i] <= '9' && i > 0)
68 continue;
69 if (id[i] == '_' && i > 0 && i != id.size()-1)
70 continue;
71 goto do_rename;
72 }
73
74 used_names.insert(id);
75 return id;
76
77 do_rename:;
78 std::string gen_name;
79 while (1) {
80 gen_name = stringf("id%05d", counter++);
81 if (generated_names.count(gen_name) == 0 &&
82 used_names.count(gen_name) == 0)
83 break;
84 }
85 generated_names.insert(gen_name);
86 name_map[id] = gen_name;
87 return gen_name;
88 }
89 };
90
91 struct EdifBackend : public Backend {
92 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
93 void help() YS_OVERRIDE
94 {
95 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
96 log("\n");
97 log(" write_edif [options] [filename]\n");
98 log("\n");
99 log("Write the current design to an EDIF netlist file.\n");
100 log("\n");
101 log(" -top top_module\n");
102 log(" set the specified module as design top module\n");
103 log("\n");
104 log(" -nogndvcc\n");
105 log(" do not create \"GND\" and \"VCC\" cells. (this will produce an error\n");
106 log(" if the design contains constant nets. use \"hilomap\" to map to custom\n");
107 log(" constant drivers first)\n");
108 log("\n");
109 log(" -attrprop\n");
110 log(" create EDIF properties for cell attributes\n");
111 log("\n");
112 log(" -pvector {par|bra|ang}\n");
113 log(" sets the delimiting character for module port rename clauses to\n");
114 log(" parentheses, square brackets, or angle brackets.\n");
115 log("\n");
116 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
117 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
118 log("necessary to make small modifications to this command when a different tool\n");
119 log("is targeted.\n");
120 log("\n");
121 }
122 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
123 {
124 log_header(design, "Executing EDIF backend.\n");
125 std::string top_module_name;
126 bool port_rename = false;
127 bool attr_properties = false;
128 std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
129 bool nogndvcc = false;
130 CellTypes ct(design);
131 EdifNames edif_names;
132
133 size_t argidx;
134 for (argidx = 1; argidx < args.size(); argidx++)
135 {
136 if (args[argidx] == "-top" && argidx+1 < args.size()) {
137 top_module_name = args[++argidx];
138 continue;
139 }
140 if (args[argidx] == "-nogndvcc") {
141 nogndvcc = true;
142 continue;
143 }
144 if (args[argidx] == "-attrprop") {
145 attr_properties = true;
146 continue;
147 }
148 if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
149 std::string parray;
150 port_rename = true;
151 parray = args[++argidx];
152 if (parray == "par") {
153 edif_names.delim_left = '(';edif_names.delim_right = ')';
154 } else if (parray == "ang") {
155 edif_names.delim_left = '<';edif_names.delim_right = '>';
156 } else {
157 edif_names.delim_left = '[';edif_names.delim_right = ']';
158 }
159 continue;
160 }
161 break;
162 }
163 extra_args(f, filename, args, argidx);
164
165 if (top_module_name.empty())
166 for (auto & mod_it:design->modules_)
167 if (mod_it.second->get_bool_attribute("\\top"))
168 top_module_name = mod_it.first.str();
169
170 for (auto module_it : design->modules_)
171 {
172 RTLIL::Module *module = module_it.second;
173 if (module->get_bool_attribute("\\blackbox"))
174 continue;
175
176 if (top_module_name.empty())
177 top_module_name = module->name.str();
178
179 if (module->processes.size() != 0)
180 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
181 if (module->memories.size() != 0)
182 log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
183
184 for (auto cell_it : module->cells_)
185 {
186 RTLIL::Cell *cell = cell_it.second;
187 if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
188 lib_cell_ports[cell->type];
189 for (auto p : cell->connections())
190 lib_cell_ports[cell->type][p.first] = GetSize(p.second);
191 }
192 }
193 }
194
195 if (top_module_name.empty())
196 log_error("No module found in design!\n");
197
198 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
199 *f << stringf(" (edifVersion 2 0 0)\n");
200 *f << stringf(" (edifLevel 0)\n");
201 *f << stringf(" (keywordMap (keywordLevel 0))\n");
202 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
203
204 *f << stringf(" (external LIB\n");
205 *f << stringf(" (edifLevel 0)\n");
206 *f << stringf(" (technology (numberDefinition))\n");
207
208 if (!nogndvcc)
209 {
210 *f << stringf(" (cell GND\n");
211 *f << stringf(" (cellType GENERIC)\n");
212 *f << stringf(" (view VIEW_NETLIST\n");
213 *f << stringf(" (viewType NETLIST)\n");
214 *f << stringf(" (interface (port G (direction OUTPUT)))\n");
215 *f << stringf(" )\n");
216 *f << stringf(" )\n");
217
218 *f << stringf(" (cell VCC\n");
219 *f << stringf(" (cellType GENERIC)\n");
220 *f << stringf(" (view VIEW_NETLIST\n");
221 *f << stringf(" (viewType NETLIST)\n");
222 *f << stringf(" (interface (port P (direction OUTPUT)))\n");
223 *f << stringf(" )\n");
224 *f << stringf(" )\n");
225 }
226
227 for (auto &cell_it : lib_cell_ports) {
228 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
229 *f << stringf(" (cellType GENERIC)\n");
230 *f << stringf(" (view VIEW_NETLIST\n");
231 *f << stringf(" (viewType NETLIST)\n");
232 *f << stringf(" (interface\n");
233 for (auto &port_it : cell_it.second) {
234 const char *dir = "INOUT";
235 if (ct.cell_known(cell_it.first)) {
236 if (!ct.cell_output(cell_it.first, port_it.first))
237 dir = "INPUT";
238 else if (!ct.cell_input(cell_it.first, port_it.first))
239 dir = "OUTPUT";
240 }
241 if (port_it.second == 1)
242 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
243 else {
244 int b[2] = {port_it.second-1, 0};
245 auto m = design->module(cell_it.first);
246 if (m) {
247 auto w = m->wire(port_it.first);
248 if (w) {
249 b[w->upto ? 0 : 1] = w->start_offset;
250 b[w->upto ? 1 : 0] = w->start_offset+GetSize(w)-1;
251 }
252 }
253 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), port_it.second, dir);
254 }
255 }
256 *f << stringf(" )\n");
257 *f << stringf(" )\n");
258 *f << stringf(" )\n");
259 }
260 *f << stringf(" )\n");
261
262 std::vector<RTLIL::Module*> sorted_modules;
263
264 // extract module dependencies
265 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
266 for (auto &mod_it : design->modules_) {
267 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
268 for (auto &cell_it : mod_it.second->cells_)
269 if (design->modules_.count(cell_it.second->type) > 0)
270 module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
271 }
272
273 // simple good-enough topological sort
274 // (O(n*m) on n elements and depth m)
275 while (module_deps.size() > 0) {
276 size_t sorted_modules_idx = sorted_modules.size();
277 for (auto &it : module_deps) {
278 for (auto &dep : it.second)
279 if (module_deps.count(dep) > 0)
280 goto not_ready_yet;
281 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
282 sorted_modules.push_back(it.first);
283 not_ready_yet:;
284 }
285 if (sorted_modules_idx == sorted_modules.size())
286 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
287 while (sorted_modules_idx < sorted_modules.size())
288 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
289 }
290
291
292 *f << stringf(" (library DESIGN\n");
293 *f << stringf(" (edifLevel 0)\n");
294 *f << stringf(" (technology (numberDefinition))\n");
295 for (auto module : sorted_modules)
296 {
297 if (module->get_bool_attribute("\\blackbox"))
298 continue;
299
300 SigMap sigmap(module);
301 std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
302
303 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
304 *f << stringf(" (cellType GENERIC)\n");
305 *f << stringf(" (view VIEW_NETLIST\n");
306 *f << stringf(" (viewType NETLIST)\n");
307 *f << stringf(" (interface\n");
308 for (auto &wire_it : module->wires_) {
309 RTLIL::Wire *wire = wire_it.second;
310 if (wire->port_id == 0)
311 continue;
312 const char *dir = "INOUT";
313 if (!wire->port_output)
314 dir = "INPUT";
315 else if (!wire->port_input)
316 dir = "OUTPUT";
317 if (wire->width == 1) {
318 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
319 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
320 net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
321 } else {
322 int b[2];
323 b[wire->upto ? 0 : 1] = wire->start_offset;
324 b[wire->upto ? 1 : 0] = wire->start_offset + GetSize(wire) - 1;
325 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
326 for (int i = 0; i < wire->width; i++) {
327 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
328 net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1));
329 }
330 }
331 }
332 *f << stringf(" )\n");
333 *f << stringf(" (contents\n");
334 if (!nogndvcc) {
335 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
336 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
337 }
338 for (auto &cell_it : module->cells_) {
339 RTLIL::Cell *cell = cell_it.second;
340 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
341 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
342 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
343
344 auto add_prop = [&](IdString name, Const val) {
345 if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
346 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
347 else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
348 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
349 else {
350 std::string hex_string = "";
351 for (size_t i = 0; i < val.bits.size(); i += 4) {
352 int digit_value = 0;
353 if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
354 if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
355 if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
356 if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
357 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
358 hex_string = std::string(digit_str) + hex_string;
359 }
360 *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
361 }
362 };
363
364 for (auto &p : cell->parameters)
365 add_prop(p.first, p.second);
366 if (attr_properties)
367 for (auto &p : cell->attributes)
368 add_prop(p.first, p.second);
369
370 *f << stringf(")\n");
371 for (auto &p : cell->connections()) {
372 RTLIL::SigSpec sig = sigmap(p.second);
373 for (int i = 0; i < GetSize(sig); i++)
374 if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1)
375 log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n",
376 i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i]));
377 else if (sig.size() == 1)
378 net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
379 else {
380 int member_idx = GetSize(sig)-i-1;
381 auto m = design->module(cell->type);
382 if (m) {
383 auto w = m->wire(p.first);
384 if (w)
385 member_idx = GetSize(w)-i-1;
386 }
387 net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))",
388 EDIF_REF(p.first), member_idx, EDIF_REF(cell->name)));
389 }
390 }
391 }
392 for (auto &it : net_join_db) {
393 RTLIL::SigBit sig = it.first;
394 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
395 if (sig == RTLIL::State::Sx) {
396 for (auto &ref : it.second)
397 log_warning("Exporting x-bit on %s as zero bit.\n", ref.c_str());
398 sig = RTLIL::State::S0;
399 } else {
400 for (auto &ref : it.second)
401 log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.c_str());
402 log_abort();
403 }
404 }
405 std::string netname;
406 if (sig == RTLIL::State::S0)
407 netname = "GND_NET";
408 else if (sig == RTLIL::State::S1)
409 netname = "VCC_NET";
410 else {
411 netname = log_signal(sig);
412 for (size_t i = 0; i < netname.size(); i++)
413 if (netname[i] == ' ' || netname[i] == '\\')
414 netname.erase(netname.begin() + i--);
415 }
416 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
417 for (auto &ref : it.second)
418 *f << stringf(" %s\n", ref.c_str());
419 if (sig.wire == NULL) {
420 if (nogndvcc)
421 log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
422 if (sig == RTLIL::State::S0)
423 *f << stringf(" (portRef G (instanceRef GND))\n");
424 if (sig == RTLIL::State::S1)
425 *f << stringf(" (portRef P (instanceRef VCC))\n");
426 }
427 *f << stringf(" ))\n");
428 }
429 *f << stringf(" )\n");
430 *f << stringf(" )\n");
431 *f << stringf(" )\n");
432 }
433 *f << stringf(" )\n");
434
435 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
436 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
437 *f << stringf(" )\n");
438
439 *f << stringf(")\n");
440 }
441 } EdifBackend;
442
443 PRIVATE_NAMESPACE_END