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Merge https://github.com/cliffordwolf/yosys
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 USING_YOSYS_NAMESPACE
31 PRIVATE_NAMESPACE_BEGIN
32
33 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
34 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
35
36 namespace
37 {
38 struct EdifNames
39 {
40 int counter;
41 std::set<std::string> generated_names, used_names;
42 std::map<std::string, std::string> name_map;
43
44 EdifNames() : counter(1) { }
45
46 std::string operator()(std::string id, bool define)
47 {
48 if (define) {
49 std::string new_id = operator()(id, false);
50 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
51 }
52
53 if (name_map.count(id) > 0)
54 return name_map.at(id);
55 if (generated_names.count(id) > 0)
56 goto do_rename;
57 if (id == "GND" || id == "VCC")
58 goto do_rename;
59
60 for (size_t i = 0; i < id.size(); i++) {
61 if ('A' <= id[i] && id[i] <= 'Z')
62 continue;
63 if ('a' <= id[i] && id[i] <= 'z')
64 continue;
65 if ('0' <= id[i] && id[i] <= '9' && i > 0)
66 continue;
67 if (id[i] == '_' && i > 0 && i != id.size()-1)
68 continue;
69 goto do_rename;
70 }
71
72 used_names.insert(id);
73 return id;
74
75 do_rename:;
76 std::string gen_name;
77 while (1) {
78 gen_name = stringf("id%05d", counter++);
79 if (generated_names.count(gen_name) == 0 &&
80 used_names.count(gen_name) == 0)
81 break;
82 }
83 generated_names.insert(gen_name);
84 name_map[id] = gen_name;
85 return gen_name;
86 }
87 };
88 }
89
90 struct EdifBackend : public Backend {
91 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
92 virtual void help()
93 {
94 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
95 log("\n");
96 log(" write_edif [options] [filename]\n");
97 log("\n");
98 log("Write the current design to an EDIF netlist file.\n");
99 log("\n");
100 log(" -top top_module\n");
101 log(" set the specified module as design top module\n");
102 log("\n");
103 log(" -nogndvcc\n");
104 log(" do not create \"GND\" and \"VCC\" cells. (this will produce an error\n");
105 log(" if the design contains constant nets. use \"hilomap\" to map to custom\n");
106 log(" constant drivers first)\n");
107 log("\n");
108 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
109 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
110 log("necessary to make small modifications to this command when a different tool\n");
111 log("is targeted.\n");
112 log("\n");
113 }
114 virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
115 {
116 log_header(design, "Executing EDIF backend.\n");
117
118 std::string top_module_name;
119 std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
120 bool nogndvcc = false;
121 CellTypes ct(design);
122 EdifNames edif_names;
123
124 size_t argidx;
125 for (argidx = 1; argidx < args.size(); argidx++)
126 {
127 if (args[argidx] == "-top" && argidx+1 < args.size()) {
128 top_module_name = args[++argidx];
129 continue;
130 }
131 if (args[argidx] == "-nogndvcc") {
132 nogndvcc = true;
133 continue;
134 }
135 break;
136 }
137 extra_args(f, filename, args, argidx);
138
139 if (top_module_name.empty())
140 for (auto & mod_it:design->modules_)
141 if (mod_it.second->get_bool_attribute("\\top"))
142 top_module_name = mod_it.first.str();
143
144 for (auto module_it : design->modules_)
145 {
146 RTLIL::Module *module = module_it.second;
147 if (module->get_bool_attribute("\\blackbox"))
148 continue;
149
150 if (top_module_name.empty())
151 top_module_name = module->name.str();
152
153 if (module->processes.size() != 0)
154 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
155 if (module->memories.size() != 0)
156 log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
157
158 for (auto cell_it : module->cells_)
159 {
160 RTLIL::Cell *cell = cell_it.second;
161 if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
162 lib_cell_ports[cell->type];
163 for (auto p : cell->connections())
164 lib_cell_ports[cell->type][p.first] = GetSize(p.second);
165 }
166 }
167 }
168
169 if (top_module_name.empty())
170 log_error("No module found in design!\n");
171
172 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
173 *f << stringf(" (edifVersion 2 0 0)\n");
174 *f << stringf(" (edifLevel 0)\n");
175 *f << stringf(" (keywordMap (keywordLevel 0))\n");
176 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
177
178 *f << stringf(" (external LIB\n");
179 *f << stringf(" (edifLevel 0)\n");
180 *f << stringf(" (technology (numberDefinition))\n");
181
182 if (!nogndvcc)
183 {
184 *f << stringf(" (cell GND\n");
185 *f << stringf(" (cellType GENERIC)\n");
186 *f << stringf(" (view VIEW_NETLIST\n");
187 *f << stringf(" (viewType NETLIST)\n");
188 *f << stringf(" (interface (port G (direction OUTPUT)))\n");
189 *f << stringf(" )\n");
190 *f << stringf(" )\n");
191
192 *f << stringf(" (cell VCC\n");
193 *f << stringf(" (cellType GENERIC)\n");
194 *f << stringf(" (view VIEW_NETLIST\n");
195 *f << stringf(" (viewType NETLIST)\n");
196 *f << stringf(" (interface (port P (direction OUTPUT)))\n");
197 *f << stringf(" )\n");
198 *f << stringf(" )\n");
199 }
200
201 for (auto &cell_it : lib_cell_ports) {
202 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
203 *f << stringf(" (cellType GENERIC)\n");
204 *f << stringf(" (view VIEW_NETLIST\n");
205 *f << stringf(" (viewType NETLIST)\n");
206 *f << stringf(" (interface\n");
207 for (auto &port_it : cell_it.second) {
208 const char *dir = "INOUT";
209 if (ct.cell_known(cell_it.first)) {
210 if (!ct.cell_output(cell_it.first, port_it.first))
211 dir = "INPUT";
212 else if (!ct.cell_input(cell_it.first, port_it.first))
213 dir = "OUTPUT";
214 }
215 if (port_it.second == 1)
216 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
217 else
218 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(port_it.first), port_it.second, dir);
219 }
220 *f << stringf(" )\n");
221 *f << stringf(" )\n");
222 *f << stringf(" )\n");
223 }
224 *f << stringf(" )\n");
225
226 std::vector<RTLIL::Module*> sorted_modules;
227
228 // extract module dependencies
229 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
230 for (auto &mod_it : design->modules_) {
231 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
232 for (auto &cell_it : mod_it.second->cells_)
233 if (design->modules_.count(cell_it.second->type) > 0)
234 module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
235 }
236
237 // simple good-enough topological sort
238 // (O(n*m) on n elements and depth m)
239 while (module_deps.size() > 0) {
240 size_t sorted_modules_idx = sorted_modules.size();
241 for (auto &it : module_deps) {
242 for (auto &dep : it.second)
243 if (module_deps.count(dep) > 0)
244 goto not_ready_yet;
245 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
246 sorted_modules.push_back(it.first);
247 not_ready_yet:;
248 }
249 if (sorted_modules_idx == sorted_modules.size())
250 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
251 while (sorted_modules_idx < sorted_modules.size())
252 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
253 }
254
255
256 *f << stringf(" (library DESIGN\n");
257 *f << stringf(" (edifLevel 0)\n");
258 *f << stringf(" (technology (numberDefinition))\n");
259 for (auto module : sorted_modules)
260 {
261 if (module->get_bool_attribute("\\blackbox"))
262 continue;
263
264 SigMap sigmap(module);
265 std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
266
267 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
268 *f << stringf(" (cellType GENERIC)\n");
269 *f << stringf(" (view VIEW_NETLIST\n");
270 *f << stringf(" (viewType NETLIST)\n");
271 *f << stringf(" (interface\n");
272 for (auto &wire_it : module->wires_) {
273 RTLIL::Wire *wire = wire_it.second;
274 if (wire->port_id == 0)
275 continue;
276 const char *dir = "INOUT";
277 if (!wire->port_output)
278 dir = "INPUT";
279 else if (!wire->port_input)
280 dir = "OUTPUT";
281 if (wire->width == 1) {
282 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
283 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
284 net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
285 } else {
286 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
287 for (int i = 0; i < wire->width; i++) {
288 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
289 net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
290 }
291 }
292 }
293 *f << stringf(" )\n");
294 *f << stringf(" (contents\n");
295 if (!nogndvcc) {
296 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
297 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
298 }
299 for (auto &cell_it : module->cells_) {
300 RTLIL::Cell *cell = cell_it.second;
301 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
302 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
303 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
304 for (auto &p : cell->parameters)
305 if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
306 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
307 else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
308 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
309 else {
310 std::string hex_string = "";
311 for (size_t i = 0; i < p.second.bits.size(); i += 4) {
312 int digit_value = 0;
313 if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
314 if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
315 if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
316 if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
317 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
318 hex_string = std::string(digit_str) + hex_string;
319 }
320 *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
321 }
322 *f << stringf(")\n");
323 for (auto &p : cell->connections()) {
324 RTLIL::SigSpec sig = sigmap(p.second);
325 for (int i = 0; i < GetSize(sig); i++)
326 if (sig.size() == 1)
327 net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
328 else
329 net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
330 }
331 }
332 for (auto &it : net_join_db) {
333 RTLIL::SigBit sig = it.first;
334 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
335 continue;
336 std::string netname = log_signal(sig);
337 for (size_t i = 0; i < netname.size(); i++)
338 if (netname[i] == ' ' || netname[i] == '\\')
339 netname.erase(netname.begin() + i--);
340 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
341 for (auto &ref : it.second)
342 *f << stringf(" %s\n", ref.c_str());
343 if (sig.wire == NULL) {
344 if (nogndvcc)
345 log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
346 if (sig == RTLIL::State::S0)
347 *f << stringf(" (portRef G (instanceRef GND))\n");
348 if (sig == RTLIL::State::S1)
349 *f << stringf(" (portRef P (instanceRef VCC))\n");
350 }
351 *f << stringf(" ))\n");
352 }
353 *f << stringf(" )\n");
354 *f << stringf(" )\n");
355 *f << stringf(" )\n");
356 }
357 *f << stringf(" )\n");
358
359 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
360 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
361 *f << stringf(" )\n");
362
363 *f << stringf(")\n");
364 }
365 } EdifBackend;
366
367 PRIVATE_NAMESPACE_END