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Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 USING_YOSYS_NAMESPACE
31 PRIVATE_NAMESPACE_BEGIN
32
33 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
34 #define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str()
35 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
36
37 namespace
38 {
39 struct EdifNames
40 {
41 int counter;
42 char delim_left;
43 char delim_right;
44 std::set<std::string> generated_names, used_names;
45 std::map<std::string, std::string> name_map;
46
47 EdifNames() : counter(1), delim_left('['), delim_right(']') { }
48
49 std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0)
50 {
51 if (define) {
52 std::string new_id = operator()(id, false);
53 if (port_rename)
54 return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right);
55 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
56 }
57
58 if (name_map.count(id) > 0)
59 return name_map.at(id);
60 if (generated_names.count(id) > 0)
61 goto do_rename;
62 if (id == "GND" || id == "VCC")
63 goto do_rename;
64
65 for (size_t i = 0; i < id.size(); i++) {
66 if ('A' <= id[i] && id[i] <= 'Z')
67 continue;
68 if ('a' <= id[i] && id[i] <= 'z')
69 continue;
70 if ('0' <= id[i] && id[i] <= '9' && i > 0)
71 continue;
72 if (id[i] == '_' && i > 0 && i != id.size()-1)
73 continue;
74 goto do_rename;
75 }
76
77 used_names.insert(id);
78 return id;
79
80 do_rename:;
81 std::string gen_name;
82 while (1) {
83 gen_name = stringf("id%05d", counter++);
84 if (generated_names.count(gen_name) == 0 &&
85 used_names.count(gen_name) == 0)
86 break;
87 }
88 generated_names.insert(gen_name);
89 name_map[id] = gen_name;
90 return gen_name;
91 }
92 };
93 }
94
95 struct EdifBackend : public Backend {
96 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
97 virtual void help()
98 {
99 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
100 log("\n");
101 log(" write_edif [options] [filename]\n");
102 log("\n");
103 log("Write the current design to an EDIF netlist file.\n");
104 log("\n");
105 log(" -top top_module\n");
106 log(" set the specified module as design top module\n");
107 log("\n");
108 log(" -nogndvcc\n");
109 log(" do not create \"GND\" and \"VCC\" cells. (this will produce an error\n");
110 log(" if the design contains constant nets. use \"hilomap\" to map to custom\n");
111 log(" constant drivers first)\n");
112 log("\n");
113 log(" -pvector {par|bra|ang}\n");
114 log(" sets the delimiting character for module port rename clauses.\n");
115 log(" if it is par, The example from above will be:\n");
116 log(" (rename mcu_addr \"mcu_addr(0:23)\")\n");
117 log(" if it is ang, The example from above will be:\n");
118 log(" (rename mcu_addr \"mcu_addr<0:23>\")\n");
119 log(" otherwise:\n");
120 log(" (rename mcu_addr \"mcu_addr[0:23]\")\n");
121 log("\n");
122 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
123 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
124 log("necessary to make small modifications to this command when a different tool\n");
125 log("is targeted.\n");
126 log("\n");
127 }
128 virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
129 {
130 log_header(design, "Executing EDIF backend.\n");
131 std::string top_module_name;
132 bool port_rename = false;
133 std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
134 bool nogndvcc = false;
135 CellTypes ct(design);
136 EdifNames edif_names;
137
138 size_t argidx;
139 for (argidx = 1; argidx < args.size(); argidx++)
140 {
141 if (args[argidx] == "-top" && argidx+1 < args.size()) {
142 top_module_name = args[++argidx];
143 continue;
144 }
145 if (args[argidx] == "-nogndvcc") {
146 nogndvcc = true;
147 continue;
148 }
149 if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
150 std::string parray;
151 port_rename = true;
152 parray = args[++argidx];
153 if (parray == "par") {
154 edif_names.delim_left = '(';edif_names.delim_right = ')';
155 } else if (parray == "ang") {
156 edif_names.delim_left = '<';edif_names.delim_right = '>';
157 } else {
158 edif_names.delim_left = '[';edif_names.delim_right = ']';
159 }
160 continue;
161 }
162 break;
163 }
164 extra_args(f, filename, args, argidx);
165
166 if (top_module_name.empty())
167 for (auto & mod_it:design->modules_)
168 if (mod_it.second->get_bool_attribute("\\top"))
169 top_module_name = mod_it.first.str();
170
171 for (auto module_it : design->modules_)
172 {
173 RTLIL::Module *module = module_it.second;
174 if (module->get_bool_attribute("\\blackbox"))
175 continue;
176
177 if (top_module_name.empty())
178 top_module_name = module->name.str();
179
180 if (module->processes.size() != 0)
181 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
182 if (module->memories.size() != 0)
183 log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
184
185 for (auto cell_it : module->cells_)
186 {
187 RTLIL::Cell *cell = cell_it.second;
188 if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
189 lib_cell_ports[cell->type];
190 for (auto p : cell->connections())
191 lib_cell_ports[cell->type][p.first] = GetSize(p.second);
192 }
193 }
194 }
195
196 if (top_module_name.empty())
197 log_error("No module found in design!\n");
198
199 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
200 *f << stringf(" (edifVersion 2 0 0)\n");
201 *f << stringf(" (edifLevel 0)\n");
202 *f << stringf(" (keywordMap (keywordLevel 0))\n");
203 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
204
205 *f << stringf(" (external LIB\n");
206 *f << stringf(" (edifLevel 0)\n");
207 *f << stringf(" (technology (numberDefinition))\n");
208
209 if (!nogndvcc)
210 {
211 *f << stringf(" (cell GND\n");
212 *f << stringf(" (cellType GENERIC)\n");
213 *f << stringf(" (view VIEW_NETLIST\n");
214 *f << stringf(" (viewType NETLIST)\n");
215 *f << stringf(" (interface (port G (direction OUTPUT)))\n");
216 *f << stringf(" )\n");
217 *f << stringf(" )\n");
218
219 *f << stringf(" (cell VCC\n");
220 *f << stringf(" (cellType GENERIC)\n");
221 *f << stringf(" (view VIEW_NETLIST\n");
222 *f << stringf(" (viewType NETLIST)\n");
223 *f << stringf(" (interface (port P (direction OUTPUT)))\n");
224 *f << stringf(" )\n");
225 *f << stringf(" )\n");
226 }
227
228 for (auto &cell_it : lib_cell_ports) {
229 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
230 *f << stringf(" (cellType GENERIC)\n");
231 *f << stringf(" (view VIEW_NETLIST\n");
232 *f << stringf(" (viewType NETLIST)\n");
233 *f << stringf(" (interface\n");
234 for (auto &port_it : cell_it.second) {
235 const char *dir = "INOUT";
236 if (ct.cell_known(cell_it.first)) {
237 if (!ct.cell_output(cell_it.first, port_it.first))
238 dir = "INPUT";
239 else if (!ct.cell_input(cell_it.first, port_it.first))
240 dir = "OUTPUT";
241 }
242 if (port_it.second == 1)
243 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
244 else {
245 int b[2] = {0,port_it.second-1};
246 auto m = design->module(cell_it.first);
247 if(m) {
248 auto w = m->wire(port_it.first);
249 if(w) {
250 b[!w->upto] = w->start_offset;
251 b[!!w->upto] = w->start_offset+GetSize(w)-1;
252 }
253 }
254 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), port_it.second, dir);
255 }
256 }
257 *f << stringf(" )\n");
258 *f << stringf(" )\n");
259 *f << stringf(" )\n");
260 }
261 *f << stringf(" )\n");
262
263 std::vector<RTLIL::Module*> sorted_modules;
264
265 // extract module dependencies
266 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
267 for (auto &mod_it : design->modules_) {
268 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
269 for (auto &cell_it : mod_it.second->cells_)
270 if (design->modules_.count(cell_it.second->type) > 0)
271 module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
272 }
273
274 // simple good-enough topological sort
275 // (O(n*m) on n elements and depth m)
276 while (module_deps.size() > 0) {
277 size_t sorted_modules_idx = sorted_modules.size();
278 for (auto &it : module_deps) {
279 for (auto &dep : it.second)
280 if (module_deps.count(dep) > 0)
281 goto not_ready_yet;
282 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
283 sorted_modules.push_back(it.first);
284 not_ready_yet:;
285 }
286 if (sorted_modules_idx == sorted_modules.size())
287 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
288 while (sorted_modules_idx < sorted_modules.size())
289 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
290 }
291
292
293 *f << stringf(" (library DESIGN\n");
294 *f << stringf(" (edifLevel 0)\n");
295 *f << stringf(" (technology (numberDefinition))\n");
296 for (auto module : sorted_modules)
297 {
298 if (module->get_bool_attribute("\\blackbox"))
299 continue;
300
301 SigMap sigmap(module);
302 std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
303
304 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
305 *f << stringf(" (cellType GENERIC)\n");
306 *f << stringf(" (view VIEW_NETLIST\n");
307 *f << stringf(" (viewType NETLIST)\n");
308 *f << stringf(" (interface\n");
309 for (auto &wire_it : module->wires_) {
310 RTLIL::Wire *wire = wire_it.second;
311 if (wire->port_id == 0)
312 continue;
313 const char *dir = "INOUT";
314 if (!wire->port_output)
315 dir = "INPUT";
316 else if (!wire->port_input)
317 dir = "OUTPUT";
318 if (wire->width == 1) {
319 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
320 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
321 net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
322 } else {
323 int b[2] = {0,wire->width-1};
324 b[!wire->upto] = wire->start_offset;
325 b[!!wire->upto] = wire->start_offset+GetSize(wire)-1;
326 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
327 for (int i = 0; i < wire->width; i++) {
328 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
329 net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
330 }
331 }
332 }
333 *f << stringf(" )\n");
334 *f << stringf(" (contents\n");
335 if (!nogndvcc) {
336 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
337 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
338 }
339 for (auto &cell_it : module->cells_) {
340 RTLIL::Cell *cell = cell_it.second;
341 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
342 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
343 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
344 for (auto &p : cell->parameters)
345 if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
346 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
347 else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
348 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
349 else {
350 std::string hex_string = "";
351 for (size_t i = 0; i < p.second.bits.size(); i += 4) {
352 int digit_value = 0;
353 if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
354 if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
355 if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
356 if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
357 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
358 hex_string = std::string(digit_str) + hex_string;
359 }
360 *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
361 }
362 *f << stringf(")\n");
363 for (auto &p : cell->connections()) {
364 RTLIL::SigSpec sig = sigmap(p.second);
365 for (int i = 0; i < GetSize(sig); i++)
366 if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1)
367 log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n",
368 i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i]));
369 else if (sig.size() == 1)
370 net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
371 else
372 net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
373 }
374 }
375 for (auto &it : net_join_db) {
376 RTLIL::SigBit sig = it.first;
377 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
378 log_abort();
379 std::string netname = log_signal(sig);
380 for (size_t i = 0; i < netname.size(); i++)
381 if (netname[i] == ' ' || netname[i] == '\\')
382 netname.erase(netname.begin() + i--);
383 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
384 for (auto &ref : it.second)
385 *f << stringf(" %s\n", ref.c_str());
386 if (sig.wire == NULL) {
387 if (nogndvcc)
388 log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
389 if (sig == RTLIL::State::S0)
390 *f << stringf(" (portRef G (instanceRef GND))\n");
391 if (sig == RTLIL::State::S1)
392 *f << stringf(" (portRef P (instanceRef VCC))\n");
393 }
394 *f << stringf(" ))\n");
395 }
396 *f << stringf(" )\n");
397 *f << stringf(" )\n");
398 *f << stringf(" )\n");
399 }
400 *f << stringf(" )\n");
401
402 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
403 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
404 *f << stringf(" )\n");
405
406 *f << stringf(")\n");
407 }
408 } EdifBackend;
409
410 PRIVATE_NAMESPACE_END