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Merge branch 'master' into pr_reg_wire_error
[yosys.git] / backends / edif / edif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] EDIF Version 2 0 0 Grammar
21 // http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
22
23 #include "kernel/rtlil.h"
24 #include "kernel/register.h"
25 #include "kernel/sigtools.h"
26 #include "kernel/celltypes.h"
27 #include "kernel/log.h"
28 #include <string>
29
30 USING_YOSYS_NAMESPACE
31 PRIVATE_NAMESPACE_BEGIN
32
33 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
34 #define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str()
35 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
36
37 struct EdifNames
38 {
39 int counter;
40 char delim_left, delim_right;
41 std::set<std::string> generated_names, used_names;
42 std::map<std::string, std::string> name_map;
43
44 EdifNames() : counter(1), delim_left('['), delim_right(']') { }
45
46 std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0)
47 {
48 if (define) {
49 std::string new_id = operator()(id, false);
50 if (port_rename)
51 return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right);
52 return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id;
53 }
54
55 if (name_map.count(id) > 0)
56 return name_map.at(id);
57 if (generated_names.count(id) > 0)
58 goto do_rename;
59 if (id == "GND" || id == "VCC")
60 goto do_rename;
61
62 for (size_t i = 0; i < id.size(); i++) {
63 if ('A' <= id[i] && id[i] <= 'Z')
64 continue;
65 if ('a' <= id[i] && id[i] <= 'z')
66 continue;
67 if ('0' <= id[i] && id[i] <= '9' && i > 0)
68 continue;
69 if (id[i] == '_' && i > 0 && i != id.size()-1)
70 continue;
71 goto do_rename;
72 }
73
74 used_names.insert(id);
75 return id;
76
77 do_rename:;
78 std::string gen_name;
79 while (1) {
80 gen_name = stringf("id%05d", counter++);
81 if (generated_names.count(gen_name) == 0 &&
82 used_names.count(gen_name) == 0)
83 break;
84 }
85 generated_names.insert(gen_name);
86 name_map[id] = gen_name;
87 return gen_name;
88 }
89 };
90
91 struct EdifBackend : public Backend {
92 EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
93 void help() YS_OVERRIDE
94 {
95 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
96 log("\n");
97 log(" write_edif [options] [filename]\n");
98 log("\n");
99 log("Write the current design to an EDIF netlist file.\n");
100 log("\n");
101 log(" -top top_module\n");
102 log(" set the specified module as design top module\n");
103 log("\n");
104 log(" -nogndvcc\n");
105 log(" do not create \"GND\" and \"VCC\" cells. (this will produce an error\n");
106 log(" if the design contains constant nets. use \"hilomap\" to map to custom\n");
107 log(" constant drivers first)\n");
108 log("\n");
109 log(" -pvector {par|bra|ang}\n");
110 log(" sets the delimiting character for module port rename clauses to\n");
111 log(" parentheses, square brackets, or angle brackets.\n");
112 log("\n");
113 log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
114 log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
115 log("necessary to make small modifications to this command when a different tool\n");
116 log("is targeted.\n");
117 log("\n");
118 }
119 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
120 {
121 log_header(design, "Executing EDIF backend.\n");
122 std::string top_module_name;
123 bool port_rename = false;
124 std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
125 bool nogndvcc = false;
126 CellTypes ct(design);
127 EdifNames edif_names;
128
129 size_t argidx;
130 for (argidx = 1; argidx < args.size(); argidx++)
131 {
132 if (args[argidx] == "-top" && argidx+1 < args.size()) {
133 top_module_name = args[++argidx];
134 continue;
135 }
136 if (args[argidx] == "-nogndvcc") {
137 nogndvcc = true;
138 continue;
139 }
140 if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
141 std::string parray;
142 port_rename = true;
143 parray = args[++argidx];
144 if (parray == "par") {
145 edif_names.delim_left = '(';edif_names.delim_right = ')';
146 } else if (parray == "ang") {
147 edif_names.delim_left = '<';edif_names.delim_right = '>';
148 } else {
149 edif_names.delim_left = '[';edif_names.delim_right = ']';
150 }
151 continue;
152 }
153 break;
154 }
155 extra_args(f, filename, args, argidx);
156
157 if (top_module_name.empty())
158 for (auto & mod_it:design->modules_)
159 if (mod_it.second->get_bool_attribute("\\top"))
160 top_module_name = mod_it.first.str();
161
162 for (auto module_it : design->modules_)
163 {
164 RTLIL::Module *module = module_it.second;
165 if (module->get_bool_attribute("\\blackbox"))
166 continue;
167
168 if (top_module_name.empty())
169 top_module_name = module->name.str();
170
171 if (module->processes.size() != 0)
172 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
173 if (module->memories.size() != 0)
174 log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
175
176 for (auto cell_it : module->cells_)
177 {
178 RTLIL::Cell *cell = cell_it.second;
179 if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
180 lib_cell_ports[cell->type];
181 for (auto p : cell->connections())
182 lib_cell_ports[cell->type][p.first] = GetSize(p.second);
183 }
184 }
185 }
186
187 if (top_module_name.empty())
188 log_error("No module found in design!\n");
189
190 *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
191 *f << stringf(" (edifVersion 2 0 0)\n");
192 *f << stringf(" (edifLevel 0)\n");
193 *f << stringf(" (keywordMap (keywordLevel 0))\n");
194 *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
195
196 *f << stringf(" (external LIB\n");
197 *f << stringf(" (edifLevel 0)\n");
198 *f << stringf(" (technology (numberDefinition))\n");
199
200 if (!nogndvcc)
201 {
202 *f << stringf(" (cell GND\n");
203 *f << stringf(" (cellType GENERIC)\n");
204 *f << stringf(" (view VIEW_NETLIST\n");
205 *f << stringf(" (viewType NETLIST)\n");
206 *f << stringf(" (interface (port G (direction OUTPUT)))\n");
207 *f << stringf(" )\n");
208 *f << stringf(" )\n");
209
210 *f << stringf(" (cell VCC\n");
211 *f << stringf(" (cellType GENERIC)\n");
212 *f << stringf(" (view VIEW_NETLIST\n");
213 *f << stringf(" (viewType NETLIST)\n");
214 *f << stringf(" (interface (port P (direction OUTPUT)))\n");
215 *f << stringf(" )\n");
216 *f << stringf(" )\n");
217 }
218
219 for (auto &cell_it : lib_cell_ports) {
220 *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
221 *f << stringf(" (cellType GENERIC)\n");
222 *f << stringf(" (view VIEW_NETLIST\n");
223 *f << stringf(" (viewType NETLIST)\n");
224 *f << stringf(" (interface\n");
225 for (auto &port_it : cell_it.second) {
226 const char *dir = "INOUT";
227 if (ct.cell_known(cell_it.first)) {
228 if (!ct.cell_output(cell_it.first, port_it.first))
229 dir = "INPUT";
230 else if (!ct.cell_input(cell_it.first, port_it.first))
231 dir = "OUTPUT";
232 }
233 if (port_it.second == 1)
234 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
235 else {
236 int b[2] = {port_it.second-1, 0};
237 auto m = design->module(cell_it.first);
238 if (m) {
239 auto w = m->wire(port_it.first);
240 if (w) {
241 b[w->upto ? 0 : 1] = w->start_offset;
242 b[w->upto ? 1 : 0] = w->start_offset+GetSize(w)-1;
243 }
244 }
245 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), port_it.second, dir);
246 }
247 }
248 *f << stringf(" )\n");
249 *f << stringf(" )\n");
250 *f << stringf(" )\n");
251 }
252 *f << stringf(" )\n");
253
254 std::vector<RTLIL::Module*> sorted_modules;
255
256 // extract module dependencies
257 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
258 for (auto &mod_it : design->modules_) {
259 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
260 for (auto &cell_it : mod_it.second->cells_)
261 if (design->modules_.count(cell_it.second->type) > 0)
262 module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
263 }
264
265 // simple good-enough topological sort
266 // (O(n*m) on n elements and depth m)
267 while (module_deps.size() > 0) {
268 size_t sorted_modules_idx = sorted_modules.size();
269 for (auto &it : module_deps) {
270 for (auto &dep : it.second)
271 if (module_deps.count(dep) > 0)
272 goto not_ready_yet;
273 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
274 sorted_modules.push_back(it.first);
275 not_ready_yet:;
276 }
277 if (sorted_modules_idx == sorted_modules.size())
278 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
279 while (sorted_modules_idx < sorted_modules.size())
280 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
281 }
282
283
284 *f << stringf(" (library DESIGN\n");
285 *f << stringf(" (edifLevel 0)\n");
286 *f << stringf(" (technology (numberDefinition))\n");
287 for (auto module : sorted_modules)
288 {
289 if (module->get_bool_attribute("\\blackbox"))
290 continue;
291
292 SigMap sigmap(module);
293 std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
294
295 *f << stringf(" (cell %s\n", EDIF_DEF(module->name));
296 *f << stringf(" (cellType GENERIC)\n");
297 *f << stringf(" (view VIEW_NETLIST\n");
298 *f << stringf(" (viewType NETLIST)\n");
299 *f << stringf(" (interface\n");
300 for (auto &wire_it : module->wires_) {
301 RTLIL::Wire *wire = wire_it.second;
302 if (wire->port_id == 0)
303 continue;
304 const char *dir = "INOUT";
305 if (!wire->port_output)
306 dir = "INPUT";
307 else if (!wire->port_input)
308 dir = "OUTPUT";
309 if (wire->width == 1) {
310 *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
311 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
312 net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
313 } else {
314 int b[2];
315 b[wire->upto ? 0 : 1] = wire->start_offset;
316 b[wire->upto ? 1 : 0] = wire->start_offset + GetSize(wire) - 1;
317 *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
318 for (int i = 0; i < wire->width; i++) {
319 RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
320 net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1));
321 }
322 }
323 }
324 *f << stringf(" )\n");
325 *f << stringf(" (contents\n");
326 if (!nogndvcc) {
327 *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
328 *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
329 }
330 for (auto &cell_it : module->cells_) {
331 RTLIL::Cell *cell = cell_it.second;
332 *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
333 *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
334 lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
335 for (auto &p : cell->parameters)
336 if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
337 *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
338 else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
339 *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
340 else {
341 std::string hex_string = "";
342 for (size_t i = 0; i < p.second.bits.size(); i += 4) {
343 int digit_value = 0;
344 if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
345 if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
346 if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
347 if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
348 char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
349 hex_string = std::string(digit_str) + hex_string;
350 }
351 *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
352 }
353 *f << stringf(")\n");
354 for (auto &p : cell->connections()) {
355 RTLIL::SigSpec sig = sigmap(p.second);
356 for (int i = 0; i < GetSize(sig); i++)
357 if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1)
358 log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n",
359 i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i]));
360 else if (sig.size() == 1)
361 net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
362 else {
363 int member_idx = GetSize(sig)-i-1;
364 auto m = design->module(cell->type);
365 if (m) {
366 auto w = m->wire(p.first);
367 if (w)
368 member_idx = GetSize(w)-i-1;
369 }
370 net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))",
371 EDIF_REF(p.first), member_idx, EDIF_REF(cell->name)));
372 }
373 }
374 }
375 for (auto &it : net_join_db) {
376 RTLIL::SigBit sig = it.first;
377 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
378 if (sig == RTLIL::State::Sx) {
379 for (auto &ref : it.second)
380 log_warning("Exporting x-bit on %s as zero bit.\n", ref.c_str());
381 sig = RTLIL::State::S0;
382 } else {
383 for (auto &ref : it.second)
384 log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.c_str());
385 log_abort();
386 }
387 }
388 std::string netname;
389 if (sig == RTLIL::State::S0)
390 netname = "GND_NET";
391 else if (sig == RTLIL::State::S1)
392 netname = "VCC_NET";
393 else {
394 netname = log_signal(sig);
395 for (size_t i = 0; i < netname.size(); i++)
396 if (netname[i] == ' ' || netname[i] == '\\')
397 netname.erase(netname.begin() + i--);
398 }
399 *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
400 for (auto &ref : it.second)
401 *f << stringf(" %s\n", ref.c_str());
402 if (sig.wire == NULL) {
403 if (nogndvcc)
404 log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
405 if (sig == RTLIL::State::S0)
406 *f << stringf(" (portRef G (instanceRef GND))\n");
407 if (sig == RTLIL::State::S1)
408 *f << stringf(" (portRef P (instanceRef VCC))\n");
409 }
410 *f << stringf(" ))\n");
411 }
412 *f << stringf(" )\n");
413 *f << stringf(" )\n");
414 *f << stringf(" )\n");
415 }
416 *f << stringf(" )\n");
417
418 *f << stringf(" (design %s\n", EDIF_DEF(top_module_name));
419 *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
420 *f << stringf(" )\n");
421
422 *f << stringf(")\n");
423 }
424 } EdifBackend;
425
426 PRIVATE_NAMESPACE_END