backends/edif/runtest.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import numpy as np
   5
   6 enable_upto = True
   7 enable_offset = True
   8 enable_hierarchy = True
   9 enable_logic = True
  10
  11 def make_module(f, modname, width, subs):
  12     print("module %s (A, B, C, X, Y, Z);" % modname, file=f)
  13     inbits = list()
  14     outbits = list()
  15
  16     for p in "ABC":
  17         offset = np.random.randint(10) if enable_offset else 0
  18         if enable_upto and np.random.randint(2):
  19             print("  input [%d:%d] %s;" % (offset, offset+width-1, p), file=f)
  20         else:
  21             print("  input [%d:%d] %s;" % (offset+width-1, offset, p), file=f)
  22         for i in range(offset, offset+width):
  23             inbits.append("%s[%d]" % (p, i))
  24
  25     for p in "XYZ":
  26         offset = np.random.randint(10) if enable_offset else 0
  27         if enable_upto and np.random.randint(2):
  28             print("  output [%d:%d] %s;" % (offset, offset+width-1, p), file=f)
  29         else:
  30             print("  output [%d:%d] %s;" % (offset+width-1, offset, p), file=f)
  31         for i in range(offset, offset+width):
  32             outbits.append("%s[%d]" % (p, i))
  33
  34     instidx = 0
  35     subcandidates = list(subs.keys())
  36
  37     while len(outbits) > 0:
  38         submod = None
  39         if len(subcandidates):
  40             submod = np.random.choice(subcandidates)
  41             subcandidates.remove(submod)
  42
  43         if submod is None or 3*subs[submod] >= len(outbits):
  44             for bit in outbits:
  45                 if enable_logic:
  46                     print("  assign %s = %s & ~%s;" % (bit,  np.random.choice(inbits), np.random.choice(inbits)), file=f)
  47                 else:
  48                     print("  assign %s = %s;" % (bit,  np.random.choice(inbits)), file=f)
  49             break
  50
  51         instidx += 1
  52         print("  %s inst%d (" % (submod, instidx), file=f)
  53
  54         for p in "ABC":
  55             print("    .%s({%s})," % (p, ",".join(np.random.choice(inbits, subs[submod]))), file=f)
  56
  57         for p in "XYZ":
  58             bits = list(np.random.choice(outbits, subs[submod], False))
  59             for bit in bits:
  60                 outbits.remove(bit)
  61             print("    .%s({%s})%s" % (p, ",".join(bits), "," if p != "Z" else ""), file=f)
  62
  63         print("  );", file=f);
  64
  65     print("endmodule", file=f)
  66
  67 with open("test_top.v", "w") as f:
  68     if enable_hierarchy:
  69         make_module(f, "sub1", 2, {})
  70         make_module(f, "sub2", 3, {})
  71         make_module(f, "sub3", 4, {})
  72         make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
  73         make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
  74         make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
  75         make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8})
  76     else:
  77         make_module(f, "top", 32, {})
  78
  79 os.system("set -x; ../../yosys -p 'synth_xilinx -top top; write_edif -pvector par test_syn.edif' test_top.v")
  80
  81 with open("test_syn.tcl", "w") as f:
  82     print("read_edif test_syn.edif", file=f)
  83     print("link_design", file=f)
  84     print("write_verilog -force test_syn.v", file=f)
  85
  86 os.system("set -x; vivado -nojournal -nolog -mode batch -source test_syn.tcl")
  87
  88 with open("test_tb.v", "w") as f:
  89     print("module tb;", file=f)
  90     print("  reg [31:0] A, B, C;", file=f)
  91     print("  wire [31:0] X, Y, Z;", file=f)
  92     print("", file=f)
  93     print("  top uut (", file=f)
  94     print("    .A(A),", file=f)
  95     print("    .B(B),", file=f)
  96     print("    .C(C),", file=f)
  97     print("    .X(X),", file=f)
  98     print("    .Y(Y),", file=f)
  99     print("    .Z(Z)", file=f)
 100     print("  );", file=f)
 101     print("", file=f)
 102     print("  initial begin", file=f)
 103     for i in range(100):
 104         print("    A = 32'h%08x;" % np.random.randint(2**32), file=f)
 105         print("    B = 32'h%08x;" % np.random.randint(2**32), file=f)
 106         print("    C = 32'h%08x;" % np.random.randint(2**32), file=f)
 107         print("    #10;", file=f)
 108         print("    $display(\"%x %x %x\", X, Y, Z);", file=f)
 109         print("    #10;", file=f)
 110     print("    $finish;", file=f)
 111     print("  end", file=f)
 112     print("endmodule", file=f)
 113
 114 os.system("set -x; iverilog -o test_gold test_tb.v test_top.v")
 115 os.system("set -x; iverilog -o test_gate test_tb.v test_syn.v ../../techlibs/xilinx/cells_sim.v")
 116
 117 os.system("set -x; ./test_gold > test_gold.out")
 118 os.system("set -x; ./test_gate > test_gate.out")
 119
 120 os.system("set -x; md5sum test_gold.out test_gate.out")
 121