2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
26 #include "backends/ilang/ilang_backend.h"
33 PRIVATE_NAMESPACE_BEGIN
35 pool
<string
> used_names
;
36 dict
<IdString
, string
> namecache
;
39 typedef unsigned FDirection
;
40 static const FDirection FD_NODIRECTION
= 0x0;
41 static const FDirection FD_IN
= 0x1;
42 static const FDirection FD_OUT
= 0x2;
43 static const FDirection FD_INOUT
= 0x3;
44 static const int FIRRTL_MAX_DSH_WIDTH_ERROR
= 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
46 std::string
getFileinfo(const RTLIL::AttrObject
*design_entity
)
48 std::string
src(design_entity
->get_src_attribute());
50 std::ostringstream fileinfo
;
52 fileinfo
<< "@[" << src
<< "]";
55 // Remove quotes from src attribute as firrtl automatically escapes and
56 // double-quotes them.
57 std::string
fileinfo_str(fileinfo
.str());
58 fileinfo_str
.erase(std::remove(fileinfo_str
.begin(), fileinfo_str
.end(), '\"'), fileinfo_str
.end());
63 // Get a port direction with respect to a specific module.
64 FDirection
getPortFDirection(IdString id
, Module
*module
)
66 Wire
*wire
= module
->wires_
.at(id
);
67 FDirection direction
= FD_NODIRECTION
;
68 if (wire
&& wire
->port_id
)
72 if (wire
->port_output
)
83 new_id
= stringf("_%d", autoid_counter
++);
84 if (used_names
.count(new_id
) == 0) break;
87 used_names
.insert(new_id
);
91 const char *make_id(IdString id
)
93 if (namecache
.count(id
) != 0)
94 return namecache
.at(id
).c_str();
96 string new_id
= log_id(id
);
98 for (int i
= 0; i
< GetSize(new_id
); i
++)
100 char &ch
= new_id
[i
];
101 if ('a' <= ch
&& ch
<= 'z') continue;
102 if ('A' <= ch
&& ch
<= 'Z') continue;
103 if ('0' <= ch
&& ch
<= '9' && i
!= 0) continue;
104 if ('_' == ch
) continue;
108 while (used_names
.count(new_id
) != 0)
111 namecache
[id
] = new_id
;
112 used_names
.insert(new_id
);
113 return namecache
.at(id
).c_str();
121 dict
<SigBit
, pair
<string
, int>> reverse_wire_map
;
123 RTLIL::Design
*design
;
126 // Define read/write ports and memories.
127 // We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
128 // For the moment, we don't handle $readmemh or $readmemb.
129 // These will be part of a subsequent PR.
138 read_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
) : name(name
), clk_enable(clk_enable
), clk_parity(clk_parity
), transparent(transparent
), clk(clk
), ena(ena
), addr(addr
) {
139 // Current (3/13/2019) conventions:
140 // generate a constant 0 for clock and a constant 1 for enable if they are undefined.
141 if (!clk
.is_fully_def())
142 this->clk
= SigSpec(State::S0
);
143 if (!ena
.is_fully_def())
144 this->ena
= SigSpec(State::S1
);
146 string
gen_read(const char * indent
) {
147 string addr_expr
= make_expr(addr
);
148 string ena_expr
= make_expr(ena
);
149 string clk_expr
= make_expr(clk
);
150 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
151 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
152 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
153 return addr_str
+ ena_str
+ clk_str
;
156 struct write_port
: read_port
{
158 write_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
, RTLIL::SigSpec mask
) : read_port(name
, clk_enable
, clk_parity
, transparent
, clk
, ena
, addr
), mask(mask
) {
159 if (!clk
.is_fully_def())
160 this->clk
= SigSpec(RTLIL::Const(0));
161 if (!ena
.is_fully_def())
162 this->ena
= SigSpec(RTLIL::Const(0));
163 if (!mask
.is_fully_def())
164 this->ena
= SigSpec(RTLIL::Const(1));
166 string
gen_read(const char * /* indent */) {
167 log_error("gen_read called on write_port: %s\n", name
.c_str());
168 return stringf("gen_read called on write_port: %s\n", name
.c_str());
170 string
gen_write(const char * indent
) {
171 string addr_expr
= make_expr(addr
);
172 string ena_expr
= make_expr(ena
);
173 string clk_expr
= make_expr(clk
);
174 string mask_expr
= make_expr(mask
);
175 string mask_str
= stringf("%s%s.mask <= %s\n", indent
, name
.c_str(), mask_expr
.c_str());
176 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
177 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
178 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
179 return addr_str
+ ena_str
+ clk_str
+ mask_str
;
182 /* Memories defined within this module. */
184 Cell
*pCell
; // for error reporting
185 string name
; // memory name
186 int abits
; // number of address bits
187 int size
; // size (in units) of the memory
188 int width
; // size (in bits) of each element
191 vector
<read_port
> read_ports
;
192 vector
<write_port
> write_ports
;
193 std::string init_file
;
194 std::string init_file_srcFileSpec
;
196 memory(Cell
*pCell
, string name
, int abits
, int size
, int width
) : pCell(pCell
), name(name
), abits(abits
), size(size
), width(width
), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
197 // Provide defaults for abits or size if one (but not the other) is specified.
198 if (this->abits
== 0 && this->size
!= 0) {
199 this->abits
= ceil_log2(this->size
);
200 } else if (this->abits
!= 0 && this->size
== 0) {
201 this->size
= 1 << this->abits
;
203 // Sanity-check this construction.
204 if (this->name
== "") {
205 log_error("Nameless memory%s\n", this->atLine());
207 if (this->abits
== 0 && this->size
== 0) {
208 log_error("Memory %s has zero address bits and size%s\n", this->name
.c_str(), this->atLine());
210 if (this->width
== 0) {
211 log_error("Memory %s has zero width%s\n", this->name
.c_str(), this->atLine());
215 // We need a default constructor for the dict insert.
216 memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
218 const char *atLine() {
221 auto p
= pCell
->attributes
.find("\\src");
222 srcLine
= " at " + p
->second
.decode_string();
225 return srcLine
.c_str();
227 void add_memory_read_port(read_port
&rp
) {
228 read_ports
.push_back(rp
);
230 void add_memory_write_port(write_port
&wp
) {
231 write_ports
.push_back(wp
);
233 void add_memory_file(std::string init_file
, std::string init_file_srcFileSpec
) {
234 this->init_file
= init_file
;
235 this->init_file_srcFileSpec
= init_file_srcFileSpec
;
239 dict
<string
, memory
> memories
;
241 void register_memory(memory
&m
)
243 memories
[m
.name
] = m
;
246 void register_reverse_wire_map(string id
, SigSpec sig
)
248 for (int i
= 0; i
< GetSize(sig
); i
++)
249 reverse_wire_map
[sig
[i
]] = make_pair(id
, i
);
252 FirrtlWorker(Module
*module
, std::ostream
&f
, RTLIL::Design
*theDesign
) : module(module
), f(f
), design(theDesign
), indent(" ")
256 static string
make_expr(const SigSpec
&sig
)
260 for (auto chunk
: sig
.chunks())
264 if (chunk
.wire
== nullptr)
266 std::vector
<RTLIL::State
> bits
= chunk
.data
;
267 new_expr
= stringf("UInt<%d>(\"h", GetSize(bits
));
269 while (GetSize(bits
) % 4 != 0)
270 bits
.push_back(State::S0
);
272 for (int i
= GetSize(bits
)-4; i
>= 0; i
-= 4)
275 if (bits
[i
+0] == State::S1
) val
+= 1;
276 if (bits
[i
+1] == State::S1
) val
+= 2;
277 if (bits
[i
+2] == State::S1
) val
+= 4;
278 if (bits
[i
+3] == State::S1
) val
+= 8;
279 new_expr
.push_back(val
< 10 ? '0' + val
: 'a' + val
- 10);
284 else if (chunk
.offset
== 0 && chunk
.width
== chunk
.wire
->width
)
286 new_expr
= make_id(chunk
.wire
->name
);
290 string wire_id
= make_id(chunk
.wire
->name
);
291 new_expr
= stringf("bits(%s, %d, %d)", wire_id
.c_str(), chunk
.offset
+ chunk
.width
- 1, chunk
.offset
);
297 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
303 std::string
fid(RTLIL::IdString internal_id
)
305 return make_id(internal_id
);
308 std::string
cellname(RTLIL::Cell
*cell
)
310 return fid(cell
->name
).c_str();
313 void process_instance(RTLIL::Cell
*cell
, vector
<string
> &wire_exprs
)
315 std::string cell_type
= fid(cell
->type
);
316 std::string instanceOf
;
317 // If this is a parameterized module, its parent module is encoded in the cell type
318 if (cell
->type
.begins_with("$paramod"))
320 std::string::iterator it
;
321 for (it
= cell_type
.begin(); it
< cell_type
.end(); it
++)
324 case '\\': /* FALL_THROUGH */
325 case '=': /* FALL_THROUGH */
326 case '\'': /* FALL_THROUGH */
327 case '$': instanceOf
.append("_"); break;
328 default: instanceOf
.append(1, *it
); break;
334 instanceOf
= cell_type
;
337 std::string cell_name
= cellname(cell
);
338 std::string cell_name_comment
;
339 if (cell_name
!= fid(cell
->name
))
340 cell_name_comment
= " /* " + fid(cell
->name
) + " */ ";
342 cell_name_comment
= "";
343 // Find the module corresponding to this instance.
344 auto instModule
= design
->module(cell
->type
);
345 // If there is no instance for this, just return.
346 if (instModule
== NULL
)
348 log_warning("No instance for %s.%s\n", cell_type
.c_str(), cell_name
.c_str());
351 auto cellFileinfo
= getFileinfo(cell
);
352 wire_exprs
.push_back(stringf("%s" "inst %s%s of %s %s", indent
.c_str(), cell_name
.c_str(), cell_name_comment
.c_str(), instanceOf
.c_str(), cellFileinfo
.c_str()));
354 for (auto it
= cell
->connections().begin(); it
!= cell
->connections().end(); ++it
) {
355 if (it
->second
.size() > 0) {
356 const SigSpec
&secondSig
= it
->second
;
357 const std::string firstName
= cell_name
+ "." + make_id(it
->first
);
358 const std::string secondExpr
= make_expr(secondSig
);
359 // Find the direction for this port.
360 FDirection dir
= getPortFDirection(it
->first
, instModule
);
361 std::string sourceExpr
, sinkExpr
;
362 const SigSpec
*sinkSig
= nullptr;
365 log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type
.c_str(), log_signal(it
->second
));
368 sourceExpr
= firstName
;
369 sinkExpr
= secondExpr
;
370 sinkSig
= &secondSig
;
373 log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type
.c_str(), log_signal(it
->second
));
376 sourceExpr
= secondExpr
;
377 sinkExpr
= firstName
;
380 log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type
.c_str(), log_signal(it
->second
), dir
);
383 // Check for subfield assignment.
384 std::string bitsString
= "bits(";
385 if (sinkExpr
.compare(0, bitsString
.length(), bitsString
) == 0) {
386 if (sinkSig
== nullptr)
387 log_error("Unknown subfield %s.%s\n", cell_type
.c_str(), sinkExpr
.c_str());
388 // Don't generate the assignment here.
389 // Add the source and sink to the "reverse_wire_map" and we'll output the assignment
390 // as part of the coalesced subfield assignments for this wire.
391 register_reverse_wire_map(sourceExpr
, *sinkSig
);
393 wire_exprs
.push_back(stringf("\n%s%s <= %s %s", indent
.c_str(), sinkExpr
.c_str(), sourceExpr
.c_str(), cellFileinfo
.c_str()));
397 wire_exprs
.push_back(stringf("\n"));
401 // Given an expression for a shift amount, and a maximum width,
402 // generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
403 std::string
gen_dshl(const string b_expr
, const int b_width
)
405 string result
= b_expr
;
406 if (b_width
>= FIRRTL_MAX_DSH_WIDTH_ERROR
) {
407 int max_shift_width_bits
= FIRRTL_MAX_DSH_WIDTH_ERROR
- 1;
408 string max_shift_string
= stringf("UInt<%d>(%d)", max_shift_width_bits
, (1<<max_shift_width_bits
) - 1);
409 // Deal with the difference in semantics between FIRRTL and verilog
410 result
= stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr
.c_str(), max_shift_string
.c_str(), max_shift_string
.c_str(), b_expr
.c_str(), max_shift_width_bits
- 1);
417 auto moduleFileinfo
= getFileinfo(module
);
418 f
<< stringf(" module %s: %s\n", make_id(module
->name
), moduleFileinfo
.c_str());
419 vector
<string
> port_decls
, wire_decls
, cell_exprs
, wire_exprs
;
421 for (auto wire
: module
->wires())
423 const auto wireName
= make_id(wire
->name
);
424 auto wireFileinfo
= getFileinfo(wire
);
426 // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
427 if (wire
->attributes
.count("\\init")) {
428 log_warning("Initial value (%s) for (%s.%s) not supported\n",
429 wire
->attributes
.at("\\init").as_string().c_str(),
430 log_id(module
), log_id(wire
));
434 if (wire
->port_input
&& wire
->port_output
)
435 log_error("Module port %s.%s is inout!\n", log_id(module
), log_id(wire
));
436 port_decls
.push_back(stringf(" %s %s: UInt<%d> %s\n", wire
->port_input
? "input" : "output",
437 wireName
, wire
->width
, wireFileinfo
.c_str()));
441 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", wireName
, wire
->width
, wireFileinfo
.c_str()));
445 for (auto cell
: module
->cells())
447 static Const
ndef(0, 0);
449 // Is this cell is a module instance?
450 if (cell
->type
[0] != '$')
452 process_instance(cell
, wire_exprs
);
455 // Not a module instance. Set up cell properties
456 bool extract_y_bits
= false; // Assume no extraction of final bits will be required.
457 int a_width
= cell
->parameters
.at("\\A_WIDTH", ndef
).as_int(); // The width of "A"
458 int b_width
= cell
->parameters
.at("\\B_WIDTH", ndef
).as_int(); // The width of "A"
459 const int y_width
= cell
->parameters
.at("\\Y_WIDTH", ndef
).as_int(); // The width of the result
460 const bool a_signed
= cell
->parameters
.at("\\A_SIGNED", ndef
).as_bool();
461 const bool b_signed
= cell
->parameters
.at("\\B_SIGNED", ndef
).as_bool();
462 bool firrtl_is_signed
= a_signed
; // The result is signed (subsequent code may change this).
463 int firrtl_width
= 0;
465 bool always_uint
= false;
466 string y_id
= make_id(cell
->name
);
467 std::string cellFileinfo
= getFileinfo(cell
);
469 if (cell
->type
.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
471 string a_expr
= make_expr(cell
->getPort("\\A"));
472 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), y_width
, cellFileinfo
.c_str()));
475 a_expr
= "asSInt(" + a_expr
+ ")";
478 // Don't use the results of logical operations (a single bit) to control padding
479 if (!(cell
->type
.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width
== 1) ) {
480 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
483 // Assume the FIRRTL width is a single bit.
485 if (cell
->type
== "$not") primop
= "not";
486 else if (cell
->type
== "$neg") {
488 firrtl_is_signed
= true; // Result of "neg" is signed (an SInt).
489 firrtl_width
= a_width
;
490 } else if (cell
->type
== "$logic_not") {
492 a_expr
= stringf("%s, UInt(0)", a_expr
.c_str());
494 else if (cell
->type
== "$reduce_and") primop
= "andr";
495 else if (cell
->type
== "$reduce_or") primop
= "orr";
496 else if (cell
->type
== "$reduce_xor") primop
= "xorr";
497 else if (cell
->type
== "$reduce_xnor") {
499 a_expr
= stringf("xorr(%s)", a_expr
.c_str());
501 else if (cell
->type
== "$reduce_bool") {
503 // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
504 a_expr
= stringf("%s, %cInt<%d>(0)", a_expr
.c_str(), a_signed
? 'S' : 'U', a_width
);
507 string expr
= stringf("%s(%s)", primop
.c_str(), a_expr
.c_str());
509 if ((firrtl_is_signed
&& !always_uint
))
510 expr
= stringf("asUInt(%s)", expr
.c_str());
512 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
513 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
517 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx",
518 "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
519 "$logic_and", "$logic_or", "$pow"))
521 string a_expr
= make_expr(cell
->getPort("\\A"));
522 string b_expr
= make_expr(cell
->getPort("\\B"));
523 std::string cellFileinfo
= getFileinfo(cell
);
524 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), y_width
, cellFileinfo
.c_str()));
527 a_expr
= "asSInt(" + a_expr
+ ")";
528 // Expand the "A" operand to the result width
529 if (a_width
< y_width
) {
530 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
534 // Shift amount is always unsigned, and needn't be padded to result width,
535 // otherwise, we need to cast the b_expr appropriately
536 if (b_signed
&& !cell
->type
.in("$shr", "$sshr", "$shl", "$sshl", "$pow")) {
537 b_expr
= "asSInt(" + b_expr
+ ")";
538 // Expand the "B" operand to the result width
539 if (b_width
< y_width
) {
540 b_expr
= stringf("pad(%s, %d)", b_expr
.c_str(), y_width
);
545 // For the arithmetic ops, expand operand widths to result widths befor performing the operation.
546 // This corresponds (according to iverilog) to what verilog compilers implement.
547 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or"))
549 if (a_width
< y_width
) {
550 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
553 if (b_width
< y_width
) {
554 b_expr
= stringf("pad(%s, %d)", b_expr
.c_str(), y_width
);
558 // Assume the FIRRTL width is the width of "A"
559 firrtl_width
= a_width
;
560 auto a_sig
= cell
->getPort("\\A");
562 if (cell
->type
== "$add") {
564 firrtl_is_signed
= a_signed
| b_signed
;
565 firrtl_width
= max(a_width
, b_width
);
566 } else if (cell
->type
== "$sub") {
568 firrtl_is_signed
= true;
569 int a_widthInc
= (!a_signed
&& b_signed
) ? 2 : (a_signed
&& !b_signed
) ? 1 : 0;
570 int b_widthInc
= (a_signed
&& !b_signed
) ? 2 : (!a_signed
&& b_signed
) ? 1 : 0;
571 firrtl_width
= max(a_width
+ a_widthInc
, b_width
+ b_widthInc
);
572 } else if (cell
->type
== "$mul") {
574 firrtl_is_signed
= a_signed
| b_signed
;
575 firrtl_width
= a_width
+ b_width
;
576 } else if (cell
->type
== "$div") {
578 firrtl_is_signed
= a_signed
| b_signed
;
579 firrtl_width
= a_width
;
580 } else if (cell
->type
== "$mod") {
582 firrtl_width
= min(a_width
, b_width
);
583 } else if (cell
->type
== "$and") {
586 firrtl_width
= max(a_width
, b_width
);
588 else if (cell
->type
== "$or" ) {
591 firrtl_width
= max(a_width
, b_width
);
593 else if (cell
->type
== "$xor") {
596 firrtl_width
= max(a_width
, b_width
);
598 else if (cell
->type
== "$xnor") {
601 firrtl_width
= max(a_width
, b_width
);
603 else if ((cell
->type
== "$eq") | (cell
->type
== "$eqx")) {
608 else if ((cell
->type
== "$ne") | (cell
->type
== "$nex")) {
613 else if (cell
->type
== "$gt") {
618 else if (cell
->type
== "$ge") {
623 else if (cell
->type
== "$lt") {
628 else if (cell
->type
== "$le") {
633 else if ((cell
->type
== "$shl") | (cell
->type
== "$sshl")) {
634 // FIRRTL will widen the result (y) by the amount of the shift.
635 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
636 extract_y_bits
= true;
637 // Is the shift amount constant?
638 auto b_sig
= cell
->getPort("\\B");
639 if (b_sig
.is_fully_const()) {
641 int shift_amount
= b_sig
.as_int();
642 b_expr
= std::to_string(shift_amount
);
643 firrtl_width
= a_width
+ shift_amount
;
646 // Convert from FIRRTL left shift semantics.
647 b_expr
= gen_dshl(b_expr
, b_width
);
648 firrtl_width
= a_width
+ (1 << b_width
) - 1;
651 else if ((cell
->type
== "$shr") | (cell
->type
== "$sshr")) {
652 // We don't need to extract a specific range of bits.
653 extract_y_bits
= false;
654 // Is the shift amount constant?
655 auto b_sig
= cell
->getPort("\\B");
656 if (b_sig
.is_fully_const()) {
658 int shift_amount
= b_sig
.as_int();
659 b_expr
= std::to_string(shift_amount
);
660 firrtl_width
= max(1, a_width
- shift_amount
);
663 firrtl_width
= a_width
;
665 // We'll need to do some special fixups if the source (and thus result) is signed.
666 if (firrtl_is_signed
) {
667 // If this is a "logical" shift right, pretend the source is unsigned.
668 if (cell
->type
== "$shr") {
669 a_expr
= "asUInt(" + a_expr
+ ")";
673 else if ((cell
->type
== "$logic_and")) {
675 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
676 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
680 else if ((cell
->type
== "$logic_or")) {
682 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
683 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
687 else if ((cell
->type
== "$pow")) {
688 if (a_sig
.is_fully_const() && a_sig
.as_int() == 2) {
689 // We'll convert this to a shift. To simplify things, change the a_expr to "1"
690 // so we can use b_expr directly as a shift amount.
691 // Only support 2 ** N (i.e., shift left)
692 // FIRRTL will widen the result (y) by the amount of the shift.
693 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
694 a_expr
= firrtl_is_signed
? "SInt(1)" : "UInt(1)";
695 extract_y_bits
= true;
696 // Is the shift amount constant?
697 auto b_sig
= cell
->getPort("\\B");
698 if (b_sig
.is_fully_const()) {
700 int shiftAmount
= b_sig
.as_int();
701 if (shiftAmount
< 0) {
702 log_error("Negative power exponent - %d: %s.%s\n", shiftAmount
, log_id(module
), log_id(cell
));
704 b_expr
= std::to_string(shiftAmount
);
705 firrtl_width
= a_width
+ shiftAmount
;
708 // Convert from FIRRTL left shift semantics.
709 b_expr
= gen_dshl(b_expr
, b_width
);
710 firrtl_width
= a_width
+ (1 << b_width
) - 1;
713 log_error("Non power 2: %s.%s\n", log_id(module
), log_id(cell
));
717 if (!cell
->parameters
.at("\\B_SIGNED").as_bool()) {
718 b_expr
= "asUInt(" + b_expr
+ ")";
722 // Deal with $xnor == ~^ (not xor)
723 if (primop
== "xnor") {
724 expr
= stringf("not(xor(%s, %s))", a_expr
.c_str(), b_expr
.c_str());
726 expr
= stringf("%s(%s, %s)", primop
.c_str(), a_expr
.c_str(), b_expr
.c_str());
729 // Deal with FIRRTL's "shift widens" semantics, or the need to widen the FIRRTL result.
730 // If the operation is signed, the FIRRTL width will be 1 one bit larger.
731 if (extract_y_bits
) {
732 expr
= stringf("bits(%s, %d, 0)", expr
.c_str(), y_width
- 1);
733 } else if (firrtl_is_signed
&& (firrtl_width
+ 1) < y_width
) {
734 expr
= stringf("pad(%s, %d)", expr
.c_str(), y_width
);
737 if ((firrtl_is_signed
&& !always_uint
))
738 expr
= stringf("asUInt(%s)", expr
.c_str());
740 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
741 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
746 if (cell
->type
.in("$mux"))
748 int width
= cell
->parameters
.at("\\WIDTH").as_int();
749 string a_expr
= make_expr(cell
->getPort("\\A"));
750 string b_expr
= make_expr(cell
->getPort("\\B"));
751 string s_expr
= make_expr(cell
->getPort("\\S"));
752 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), width
, cellFileinfo
.c_str()));
754 string expr
= stringf("mux(%s, %s, %s)", s_expr
.c_str(), b_expr
.c_str(), a_expr
.c_str());
756 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
757 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
762 if (cell
->type
.in("$mem"))
764 string mem_id
= make_id(cell
->name
);
765 int abits
= cell
->parameters
.at("\\ABITS").as_int();
766 int width
= cell
->parameters
.at("\\WIDTH").as_int();
767 int size
= cell
->parameters
.at("\\SIZE").as_int();
768 memory
m(cell
, mem_id
, abits
, size
, width
);
769 int rd_ports
= cell
->parameters
.at("\\RD_PORTS").as_int();
770 int wr_ports
= cell
->parameters
.at("\\WR_PORTS").as_int();
772 Const initdata
= cell
->parameters
.at("\\INIT");
773 for (State bit
: initdata
.bits
)
774 if (bit
!= State::Sx
)
775 log_error("Memory with initialization data: %s.%s\n", log_id(module
), log_id(cell
));
777 Const rd_clk_enable
= cell
->parameters
.at("\\RD_CLK_ENABLE");
778 Const wr_clk_enable
= cell
->parameters
.at("\\WR_CLK_ENABLE");
779 Const wr_clk_polarity
= cell
->parameters
.at("\\WR_CLK_POLARITY");
781 int offset
= cell
->parameters
.at("\\OFFSET").as_int();
783 log_error("Memory with nonzero offset: %s.%s\n", log_id(module
), log_id(cell
));
785 for (int i
= 0; i
< rd_ports
; i
++)
787 if (rd_clk_enable
[i
] != State::S0
)
788 log_error("Clocked read port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
790 SigSpec addr_sig
= cell
->getPort("\\RD_ADDR").extract(i
*abits
, abits
);
791 SigSpec data_sig
= cell
->getPort("\\RD_DATA").extract(i
*width
, width
);
792 string addr_expr
= make_expr(addr_sig
);
793 string
name(stringf("%s.r%d", m
.name
.c_str(), i
));
794 bool clk_enable
= false;
795 bool clk_parity
= true;
796 bool transparency
= false;
797 SigSpec ena_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
798 SigSpec clk_sig
= RTLIL::SigSpec(RTLIL::State::S0
, 1);
799 read_port
rp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, ena_sig
, addr_sig
);
800 m
.add_memory_read_port(rp
);
801 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
802 register_reverse_wire_map(stringf("%s.data", name
.c_str()), data_sig
);
805 for (int i
= 0; i
< wr_ports
; i
++)
807 if (wr_clk_enable
[i
] != State::S1
)
808 log_error("Unclocked write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
810 if (wr_clk_polarity
[i
] != State::S1
)
811 log_error("Negedge write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
813 string
name(stringf("%s.w%d", m
.name
.c_str(), i
));
814 bool clk_enable
= true;
815 bool clk_parity
= true;
816 bool transparency
= false;
817 SigSpec addr_sig
=cell
->getPort("\\WR_ADDR").extract(i
*abits
, abits
);
818 string addr_expr
= make_expr(addr_sig
);
819 SigSpec data_sig
=cell
->getPort("\\WR_DATA").extract(i
*width
, width
);
820 string data_expr
= make_expr(data_sig
);
821 SigSpec clk_sig
= cell
->getPort("\\WR_CLK").extract(i
);
822 string clk_expr
= make_expr(clk_sig
);
824 SigSpec wen_sig
= cell
->getPort("\\WR_EN").extract(i
*width
, width
);
825 string wen_expr
= make_expr(wen_sig
[0]);
827 for (int i
= 1; i
< GetSize(wen_sig
); i
++)
828 if (wen_sig
[0] != wen_sig
[i
])
829 log_error("Complex write enable on port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
831 SigSpec mask_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
832 write_port
wp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, wen_sig
[0], addr_sig
, mask_sig
);
833 m
.add_memory_write_port(wp
);
834 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), name
.c_str(), data_expr
.c_str()));
835 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
841 if (cell
->type
.in("$memwr", "$memrd", "$meminit"))
843 std::string cell_type
= fid(cell
->type
);
844 std::string mem_id
= make_id(cell
->parameters
["\\MEMID"].decode_string());
845 int abits
= cell
->parameters
.at("\\ABITS").as_int();
846 int width
= cell
->parameters
.at("\\WIDTH").as_int();
847 memory
*mp
= nullptr;
848 if (cell
->type
== "$meminit" ) {
849 log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module
), log_id(cell
), mem_id
.c_str());
851 // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
852 auto addrSig
= cell
->getPort("\\ADDR");
853 auto dataSig
= cell
->getPort("\\DATA");
854 auto enableSig
= cell
->getPort("\\EN");
855 auto clockSig
= cell
->getPort("\\CLK");
856 Const clk_enable
= cell
->parameters
.at("\\CLK_ENABLE");
857 Const clk_polarity
= cell
->parameters
.at("\\CLK_POLARITY");
859 // Do we already have an entry for this memory?
860 if (memories
.count(mem_id
) == 0) {
861 memory
m(cell
, mem_id
, abits
, 0, width
);
864 mp
= &memories
.at(mem_id
);
866 bool transparency
= false;
867 string data_expr
= make_expr(dataSig
);
868 if (cell
->type
.in("$memwr")) {
869 portNum
= (int) mp
->write_ports
.size();
870 write_port
wp(stringf("%s.w%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
, dataSig
);
871 mp
->add_memory_write_port(wp
);
872 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), wp
.name
.c_str(), data_expr
.c_str()));
873 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
874 } else if (cell
->type
.in("$memrd")) {
875 portNum
= (int) mp
->read_ports
.size();
876 read_port
rp(stringf("%s.r%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
);
877 mp
->add_memory_read_port(rp
);
878 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
879 register_reverse_wire_map(stringf("%s.data", rp
.name
.c_str()), dataSig
);
885 if (cell
->type
.in("$dff"))
887 bool clkpol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool();
889 log_error("Negative edge clock on FF %s.%s.\n", log_id(module
), log_id(cell
));
891 int width
= cell
->parameters
.at("\\WIDTH").as_int();
892 string expr
= make_expr(cell
->getPort("\\D"));
893 string clk_expr
= "asClock(" + make_expr(cell
->getPort("\\CLK")) + ")";
895 wire_decls
.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id
.c_str(), width
, clk_expr
.c_str(), cellFileinfo
.c_str()));
897 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
898 register_reverse_wire_map(y_id
, cell
->getPort("\\Q"));
903 // This may be a parameterized module - paramod.
904 if (cell
->type
.begins_with("$paramod"))
906 process_instance(cell
, wire_exprs
);
909 if (cell
->type
== "$shiftx") {
910 // assign y = a[b +: y_width];
911 // We'll extract the correct bits as part of the primop.
913 string a_expr
= make_expr(cell
->getPort("\\A"));
914 // Get the initial bit selector
915 string b_expr
= make_expr(cell
->getPort("\\B"));
916 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
918 if (cell
->getParam("\\B_SIGNED").as_bool()) {
919 // Use validif to constrain the selection (test the sign bit)
920 auto b_string
= b_expr
.c_str();
921 int b_sign
= cell
->parameters
.at("\\B_WIDTH").as_int() - 1;
922 b_expr
= stringf("validif(not(bits(%s, %d, %d)), %s)", b_string
, b_sign
, b_sign
, b_string
);
924 string expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_expr
.c_str());
926 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
927 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
930 if (cell
->type
== "$shift") {
931 // assign y = a >> b;
932 // where b may be negative
934 string a_expr
= make_expr(cell
->getPort("\\A"));
935 string b_expr
= make_expr(cell
->getPort("\\B"));
936 auto b_string
= b_expr
.c_str();
938 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
940 if (cell
->getParam("\\B_SIGNED").as_bool()) {
941 // We generate a left or right shift based on the sign of b.
942 std::string dshl
= stringf("bits(dshl(%s, %s), 0, %d)", a_expr
.c_str(), gen_dshl(b_expr
, b_width
).c_str(), y_width
);
943 std::string dshr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
944 expr
= stringf("mux(%s < 0, %s, %s)",
950 expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
952 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
953 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
956 if (cell
->type
== "$pos") {
959 string a_expr
= make_expr(cell
->getPort("\\A"));
960 // Verilog appears to treat the result as signed, so if the result is wider than "A",
962 if (a_width
< y_width
) {
963 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
965 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
966 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), a_expr
.c_str()));
967 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
970 log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell
->type
), log_id(module
), log_id(cell
));
973 for (auto conn
: module
->connections())
975 string y_id
= next_id();
976 int y_width
= GetSize(conn
.first
);
977 string expr
= make_expr(conn
.second
);
979 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
980 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
981 register_reverse_wire_map(y_id
, conn
.first
);
984 for (auto wire
: module
->wires())
987 std::string wireFileinfo
= getFileinfo(wire
);
989 if (wire
->port_input
)
993 bool is_valid
= false;
994 bool make_unconn_id
= false;
996 while (cursor
< wire
->width
)
1001 SigBit
start_bit(wire
, cursor
);
1003 if (reverse_wire_map
.count(start_bit
))
1005 pair
<string
, int> start_map
= reverse_wire_map
.at(start_bit
);
1007 while (cursor
+chunk_width
< wire
->width
)
1009 SigBit
stop_bit(wire
, cursor
+chunk_width
);
1011 if (reverse_wire_map
.count(stop_bit
) == 0)
1014 pair
<string
, int> stop_map
= reverse_wire_map
.at(stop_bit
);
1015 stop_map
.second
-= chunk_width
;
1017 if (start_map
!= stop_map
)
1023 new_expr
= stringf("bits(%s, %d, %d)", start_map
.first
.c_str(),
1024 start_map
.second
+ chunk_width
- 1, start_map
.second
);
1029 if (unconn_id
.empty()) {
1030 unconn_id
= next_id();
1031 make_unconn_id
= true;
1033 new_expr
= unconn_id
;
1039 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
1041 cursor
+= chunk_width
;
1045 if (make_unconn_id
) {
1046 wire_decls
.push_back(stringf(" wire %s: UInt<1> %s\n", unconn_id
.c_str(), wireFileinfo
.c_str()));
1047 // `invalid` is a firrtl construction for simulation so we will not
1048 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1049 // a specific line of verilog code.
1050 wire_decls
.push_back(stringf(" %s is invalid\n", unconn_id
.c_str()));
1052 wire_exprs
.push_back(stringf(" %s <= %s %s\n", make_id(wire
->name
), expr
.c_str(), wireFileinfo
.c_str()));
1054 if (make_unconn_id
) {
1057 // `invalid` is a firrtl construction for simulation so we will not
1058 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1059 // a specific line of verilog code.
1060 wire_decls
.push_back(stringf(" %s is invalid\n", make_id(wire
->name
)));
1064 for (auto str
: port_decls
)
1069 for (auto str
: wire_decls
)
1074 // If we have any memory definitions, output them.
1075 for (auto kv
: memories
) {
1076 memory
&m
= kv
.second
;
1077 f
<< stringf(" mem %s:\n", m
.name
.c_str());
1078 f
<< stringf(" data-type => UInt<%d>\n", m
.width
);
1079 f
<< stringf(" depth => %d\n", m
.size
);
1080 for (int i
= 0; i
< (int) m
.read_ports
.size(); i
+= 1) {
1081 f
<< stringf(" reader => r%d\n", i
);
1083 for (int i
= 0; i
< (int) m
.write_ports
.size(); i
+= 1) {
1084 f
<< stringf(" writer => w%d\n", i
);
1086 f
<< stringf(" read-latency => %d\n", m
.read_latency
);
1087 f
<< stringf(" write-latency => %d\n", m
.write_latency
);
1088 f
<< stringf(" read-under-write => undefined\n");
1092 for (auto str
: cell_exprs
)
1097 for (auto str
: wire_exprs
)
1102 struct FirrtlBackend
: public Backend
{
1103 FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
1104 void help() YS_OVERRIDE
1106 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1108 log(" write_firrtl [options] [filename]\n");
1110 log("Write a FIRRTL netlist of the current design.\n");
1111 log("The following commands are executed by this command:\n");
1115 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1117 size_t argidx
= args
.size(); // We aren't expecting any arguments.
1119 // If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
1120 if (filename
== "") {
1121 if (argidx
> 0 && args
[argidx
- 1][0] != '-') {
1122 // extra_args and friends need to see this argument.
1124 filename
= args
[argidx
];
1127 extra_args(f
, filename
, args
, argidx
);
1129 if (!design
->full_selection())
1130 log_cmd_error("This command only operates on fully selected designs!\n");
1132 log_header(design
, "Executing FIRRTL backend.\n");
1135 Pass::call(design
, stringf("pmuxtree"));
1140 // Get the top module, or a reasonable facsimile - we need something for the circuit name.
1141 Module
*top
= design
->top_module();
1142 Module
*last
= nullptr;
1143 // Generate module and wire names.
1144 for (auto module
: design
->modules()) {
1145 make_id(module
->name
);
1147 if (top
== nullptr && module
->get_bool_attribute("\\top")) {
1150 for (auto wire
: module
->wires())
1152 make_id(wire
->name
);
1158 auto circuitFileinfo
= getFileinfo(top
);
1159 *f
<< stringf("circuit %s: %s\n", make_id(top
->name
), circuitFileinfo
.c_str());
1161 for (auto module
: design
->modules())
1163 FirrtlWorker
worker(module
, *f
, design
);
1172 PRIVATE_NAMESPACE_END