2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
32 PRIVATE_NAMESPACE_BEGIN
34 pool
<string
> used_names
;
35 dict
<IdString
, string
> namecache
;
38 typedef unsigned FDirection
;
39 static const FDirection FD_NODIRECTION
= 0x0;
40 static const FDirection FD_IN
= 0x1;
41 static const FDirection FD_OUT
= 0x2;
42 static const FDirection FD_INOUT
= 0x3;
43 static const int FIRRTL_MAX_DSH_WIDTH_ERROR
= 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
45 std::string
getFileinfo(const RTLIL::AttrObject
*design_entity
)
47 std::string
src(design_entity
->get_src_attribute());
48 std::string fileinfo_str
= src
.empty() ? "" : "@[" + src
+ "]";
52 // Get a port direction with respect to a specific module.
53 FDirection
getPortFDirection(IdString id
, Module
*module
)
55 Wire
*wire
= module
->wires_
.at(id
);
56 FDirection direction
= FD_NODIRECTION
;
57 if (wire
&& wire
->port_id
)
61 if (wire
->port_output
)
72 new_id
= stringf("_%d", autoid_counter
++);
73 if (used_names
.count(new_id
) == 0) break;
76 used_names
.insert(new_id
);
80 const char *make_id(IdString id
)
82 if (namecache
.count(id
) != 0)
83 return namecache
.at(id
).c_str();
85 string new_id
= log_id(id
);
87 for (int i
= 0; i
< GetSize(new_id
); i
++)
90 if ('a' <= ch
&& ch
<= 'z') continue;
91 if ('A' <= ch
&& ch
<= 'Z') continue;
92 if ('0' <= ch
&& ch
<= '9' && i
!= 0) continue;
93 if ('_' == ch
) continue;
97 while (used_names
.count(new_id
) != 0)
100 namecache
[id
] = new_id
;
101 used_names
.insert(new_id
);
102 return namecache
.at(id
).c_str();
110 dict
<SigBit
, pair
<string
, int>> reverse_wire_map
;
112 RTLIL::Design
*design
;
115 // Define read/write ports and memories.
116 // We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
117 // For the moment, we don't handle $readmemh or $readmemb.
118 // These will be part of a subsequent PR.
127 read_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
) : name(name
), clk_enable(clk_enable
), clk_parity(clk_parity
), transparent(transparent
), clk(clk
), ena(ena
), addr(addr
) {
128 // Current (3/13/2019) conventions:
129 // generate a constant 0 for clock and a constant 1 for enable if they are undefined.
130 if (!clk
.is_fully_def())
131 this->clk
= SigSpec(State::S0
);
132 if (!ena
.is_fully_def())
133 this->ena
= SigSpec(State::S1
);
135 string
gen_read(const char * indent
) {
136 string addr_expr
= make_expr(addr
);
137 string ena_expr
= make_expr(ena
);
138 string clk_expr
= make_expr(clk
);
139 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
140 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
141 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
142 return addr_str
+ ena_str
+ clk_str
;
145 struct write_port
: read_port
{
147 write_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
, RTLIL::SigSpec mask
) : read_port(name
, clk_enable
, clk_parity
, transparent
, clk
, ena
, addr
), mask(mask
) {
148 if (!clk
.is_fully_def())
149 this->clk
= SigSpec(RTLIL::Const(0));
150 if (!ena
.is_fully_def())
151 this->ena
= SigSpec(RTLIL::Const(0));
152 if (!mask
.is_fully_def())
153 this->ena
= SigSpec(RTLIL::Const(1));
155 string
gen_read(const char * /* indent */) {
156 log_error("gen_read called on write_port: %s\n", name
.c_str());
157 return stringf("gen_read called on write_port: %s\n", name
.c_str());
159 string
gen_write(const char * indent
) {
160 string addr_expr
= make_expr(addr
);
161 string ena_expr
= make_expr(ena
);
162 string clk_expr
= make_expr(clk
);
163 string mask_expr
= make_expr(mask
);
164 string mask_str
= stringf("%s%s.mask <= %s\n", indent
, name
.c_str(), mask_expr
.c_str());
165 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
166 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
167 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
168 return addr_str
+ ena_str
+ clk_str
+ mask_str
;
171 /* Memories defined within this module. */
173 Cell
*pCell
; // for error reporting
174 string name
; // memory name
175 int abits
; // number of address bits
176 int size
; // size (in units) of the memory
177 int width
; // size (in bits) of each element
180 vector
<read_port
> read_ports
;
181 vector
<write_port
> write_ports
;
182 std::string init_file
;
183 std::string init_file_srcFileSpec
;
185 memory(Cell
*pCell
, string name
, int abits
, int size
, int width
) : pCell(pCell
), name(name
), abits(abits
), size(size
), width(width
), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
186 // Provide defaults for abits or size if one (but not the other) is specified.
187 if (this->abits
== 0 && this->size
!= 0) {
188 this->abits
= ceil_log2(this->size
);
189 } else if (this->abits
!= 0 && this->size
== 0) {
190 this->size
= 1 << this->abits
;
192 // Sanity-check this construction.
193 if (this->name
== "") {
194 log_error("Nameless memory%s\n", this->atLine());
196 if (this->abits
== 0 && this->size
== 0) {
197 log_error("Memory %s has zero address bits and size%s\n", this->name
.c_str(), this->atLine());
199 if (this->width
== 0) {
200 log_error("Memory %s has zero width%s\n", this->name
.c_str(), this->atLine());
204 // We need a default constructor for the dict insert.
205 memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
207 const char *atLine() {
210 auto p
= pCell
->attributes
.find(ID::src
);
211 srcLine
= " at " + p
->second
.decode_string();
214 return srcLine
.c_str();
216 void add_memory_read_port(read_port
&rp
) {
217 read_ports
.push_back(rp
);
219 void add_memory_write_port(write_port
&wp
) {
220 write_ports
.push_back(wp
);
222 void add_memory_file(std::string init_file
, std::string init_file_srcFileSpec
) {
223 this->init_file
= init_file
;
224 this->init_file_srcFileSpec
= init_file_srcFileSpec
;
228 dict
<string
, memory
> memories
;
230 void register_memory(memory
&m
)
232 memories
[m
.name
] = m
;
235 void register_reverse_wire_map(string id
, SigSpec sig
)
237 for (int i
= 0; i
< GetSize(sig
); i
++)
238 reverse_wire_map
[sig
[i
]] = make_pair(id
, i
);
241 FirrtlWorker(Module
*module
, std::ostream
&f
, RTLIL::Design
*theDesign
) : module(module
), f(f
), design(theDesign
), indent(" ")
245 static string
make_expr(const SigSpec
&sig
)
249 for (auto chunk
: sig
.chunks())
253 if (chunk
.wire
== nullptr)
255 std::vector
<RTLIL::State
> bits
= chunk
.data
;
256 new_expr
= stringf("UInt<%d>(\"h", GetSize(bits
));
258 while (GetSize(bits
) % 4 != 0)
259 bits
.push_back(State::S0
);
261 for (int i
= GetSize(bits
)-4; i
>= 0; i
-= 4)
264 if (bits
[i
+0] == State::S1
) val
+= 1;
265 if (bits
[i
+1] == State::S1
) val
+= 2;
266 if (bits
[i
+2] == State::S1
) val
+= 4;
267 if (bits
[i
+3] == State::S1
) val
+= 8;
268 new_expr
.push_back(val
< 10 ? '0' + val
: 'a' + val
- 10);
273 else if (chunk
.offset
== 0 && chunk
.width
== chunk
.wire
->width
)
275 new_expr
= make_id(chunk
.wire
->name
);
279 string wire_id
= make_id(chunk
.wire
->name
);
280 new_expr
= stringf("bits(%s, %d, %d)", wire_id
.c_str(), chunk
.offset
+ chunk
.width
- 1, chunk
.offset
);
286 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
292 std::string
fid(RTLIL::IdString internal_id
)
294 return make_id(internal_id
);
297 std::string
cellname(RTLIL::Cell
*cell
)
299 return fid(cell
->name
).c_str();
302 void process_instance(RTLIL::Cell
*cell
, vector
<string
> &wire_exprs
)
304 std::string cell_type
= fid(cell
->type
);
305 std::string instanceOf
;
306 // If this is a parameterized module, its parent module is encoded in the cell type
307 if (cell
->type
.begins_with("$paramod"))
309 log_assert(cell
->has_attribute(ID::hdlname
));
310 instanceOf
= cell
->get_string_attribute(ID::hdlname
);
314 instanceOf
= cell_type
;
317 std::string cell_name
= cellname(cell
);
318 std::string cell_name_comment
;
319 if (cell_name
!= fid(cell
->name
))
320 cell_name_comment
= " /* " + fid(cell
->name
) + " */ ";
322 cell_name_comment
= "";
323 // Find the module corresponding to this instance.
324 auto instModule
= design
->module(cell
->type
);
325 // If there is no instance for this, just return.
326 if (instModule
== NULL
)
328 log_warning("No instance for %s.%s\n", cell_type
.c_str(), cell_name
.c_str());
331 std::string cellFileinfo
= getFileinfo(cell
);
332 wire_exprs
.push_back(stringf("%s" "inst %s%s of %s %s", indent
.c_str(), cell_name
.c_str(), cell_name_comment
.c_str(), instanceOf
.c_str(), cellFileinfo
.c_str()));
334 for (auto it
= cell
->connections().begin(); it
!= cell
->connections().end(); ++it
) {
335 if (it
->second
.size() > 0) {
336 const SigSpec
&secondSig
= it
->second
;
337 const std::string firstName
= cell_name
+ "." + make_id(it
->first
);
338 const std::string secondExpr
= make_expr(secondSig
);
339 // Find the direction for this port.
340 FDirection dir
= getPortFDirection(it
->first
, instModule
);
341 std::string sourceExpr
, sinkExpr
;
342 const SigSpec
*sinkSig
= nullptr;
345 log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type
.c_str(), log_signal(it
->second
));
348 sourceExpr
= firstName
;
349 sinkExpr
= secondExpr
;
350 sinkSig
= &secondSig
;
353 log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type
.c_str(), log_signal(it
->second
));
356 sourceExpr
= secondExpr
;
357 sinkExpr
= firstName
;
360 log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type
.c_str(), log_signal(it
->second
), dir
);
363 // Check for subfield assignment.
364 std::string bitsString
= "bits(";
365 if (sinkExpr
.compare(0, bitsString
.length(), bitsString
) == 0) {
366 if (sinkSig
== nullptr)
367 log_error("Unknown subfield %s.%s\n", cell_type
.c_str(), sinkExpr
.c_str());
368 // Don't generate the assignment here.
369 // Add the source and sink to the "reverse_wire_map" and we'll output the assignment
370 // as part of the coalesced subfield assignments for this wire.
371 register_reverse_wire_map(sourceExpr
, *sinkSig
);
373 wire_exprs
.push_back(stringf("\n%s%s <= %s %s", indent
.c_str(), sinkExpr
.c_str(), sourceExpr
.c_str(), cellFileinfo
.c_str()));
377 wire_exprs
.push_back(stringf("\n"));
381 // Given an expression for a shift amount, and a maximum width,
382 // generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
383 std::string
gen_dshl(const string b_expr
, const int b_width
)
385 string result
= b_expr
;
386 if (b_width
>= FIRRTL_MAX_DSH_WIDTH_ERROR
) {
387 int max_shift_width_bits
= FIRRTL_MAX_DSH_WIDTH_ERROR
- 1;
388 string max_shift_string
= stringf("UInt<%d>(%d)", max_shift_width_bits
, (1<<max_shift_width_bits
) - 1);
389 // Deal with the difference in semantics between FIRRTL and verilog
390 result
= stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr
.c_str(), max_shift_string
.c_str(), max_shift_string
.c_str(), b_expr
.c_str(), max_shift_width_bits
- 1);
395 void emit_extmodule()
397 std::string moduleFileinfo
= getFileinfo(module
);
398 f
<< stringf(" extmodule %s: %s\n", make_id(module
->name
), moduleFileinfo
.c_str());
399 vector
<std::string
> port_decls
;
401 for (auto wire
: module
->wires())
403 const auto wireName
= make_id(wire
->name
);
404 std::string wireFileinfo
= getFileinfo(wire
);
406 if (wire
->port_input
&& wire
->port_output
)
408 log_error("Module port %s.%s is inout!\n", log_id(module
), log_id(wire
));
410 port_decls
.push_back(stringf(" %s %s: UInt<%d> %s\n", wire
->port_input
? "input" : "output",
411 wireName
, wire
->width
, wireFileinfo
.c_str()));
414 for (auto &str
: port_decls
)
424 std::string moduleFileinfo
= getFileinfo(module
);
425 f
<< stringf(" module %s: %s\n", make_id(module
->name
), moduleFileinfo
.c_str());
426 vector
<string
> port_decls
, wire_decls
, cell_exprs
, wire_exprs
;
428 for (auto wire
: module
->wires())
430 const auto wireName
= make_id(wire
->name
);
431 std::string wireFileinfo
= getFileinfo(wire
);
433 // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
434 if (wire
->attributes
.count(ID::init
)) {
435 log_warning("Initial value (%s) for (%s.%s) not supported\n",
436 wire
->attributes
.at(ID::init
).as_string().c_str(),
437 log_id(module
), log_id(wire
));
441 if (wire
->port_input
&& wire
->port_output
)
442 log_error("Module port %s.%s is inout!\n", log_id(module
), log_id(wire
));
443 port_decls
.push_back(stringf(" %s %s: UInt<%d> %s\n", wire
->port_input
? "input" : "output",
444 wireName
, wire
->width
, wireFileinfo
.c_str()));
448 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", wireName
, wire
->width
, wireFileinfo
.c_str()));
452 for (auto cell
: module
->cells())
454 static Const
ndef(0, 0);
456 // Is this cell is a module instance?
457 if (cell
->type
[0] != '$')
459 process_instance(cell
, wire_exprs
);
462 // Not a module instance. Set up cell properties
463 bool extract_y_bits
= false; // Assume no extraction of final bits will be required.
464 int a_width
= cell
->parameters
.at(ID::A_WIDTH
, ndef
).as_int(); // The width of "A"
465 int b_width
= cell
->parameters
.at(ID::B_WIDTH
, ndef
).as_int(); // The width of "A"
466 const int y_width
= cell
->parameters
.at(ID::Y_WIDTH
, ndef
).as_int(); // The width of the result
467 const bool a_signed
= cell
->parameters
.at(ID::A_SIGNED
, ndef
).as_bool();
468 const bool b_signed
= cell
->parameters
.at(ID::B_SIGNED
, ndef
).as_bool();
469 bool firrtl_is_signed
= a_signed
; // The result is signed (subsequent code may change this).
470 int firrtl_width
= 0;
472 bool always_uint
= false;
473 string y_id
= make_id(cell
->name
);
474 std::string cellFileinfo
= getFileinfo(cell
);
476 if (cell
->type
.in(ID($
not), ID($logic_not
), ID($neg
), ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_bool
), ID($reduce_xnor
)))
478 string a_expr
= make_expr(cell
->getPort(ID::A
));
479 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), y_width
, cellFileinfo
.c_str()));
482 a_expr
= "asSInt(" + a_expr
+ ")";
485 // Don't use the results of logical operations (a single bit) to control padding
486 if (!(cell
->type
.in(ID($eq
), ID($eqx
), ID($gt
), ID($ge
), ID($lt
), ID($le
), ID($ne
), ID($nex
), ID($reduce_bool
), ID($logic_not
)) && y_width
== 1) ) {
487 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
490 // Assume the FIRRTL width is a single bit.
492 if (cell
->type
== ID($
not)) primop
= "not";
493 else if (cell
->type
== ID($neg
)) {
495 firrtl_is_signed
= true; // Result of "neg" is signed (an SInt).
496 firrtl_width
= a_width
;
497 } else if (cell
->type
== ID($logic_not
)) {
499 a_expr
= stringf("%s, UInt(0)", a_expr
.c_str());
501 else if (cell
->type
== ID($reduce_and
)) primop
= "andr";
502 else if (cell
->type
== ID($reduce_or
)) primop
= "orr";
503 else if (cell
->type
== ID($reduce_xor
)) primop
= "xorr";
504 else if (cell
->type
== ID($reduce_xnor
)) {
506 a_expr
= stringf("xorr(%s)", a_expr
.c_str());
508 else if (cell
->type
== ID($reduce_bool
)) {
510 // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
511 a_expr
= stringf("%s, %cInt<%d>(0)", a_expr
.c_str(), a_signed
? 'S' : 'U', a_width
);
514 string expr
= stringf("%s(%s)", primop
.c_str(), a_expr
.c_str());
516 if ((firrtl_is_signed
&& !always_uint
))
517 expr
= stringf("asUInt(%s)", expr
.c_str());
519 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
520 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
524 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($
xor), ID($xnor
), ID($
and), ID($
or), ID($eq
), ID($eqx
),
525 ID($gt
), ID($ge
), ID($lt
), ID($le
), ID($ne
), ID($nex
), ID($shr
), ID($sshr
), ID($sshl
), ID($shl
),
526 ID($logic_and
), ID($logic_or
), ID($pow
)))
528 string a_expr
= make_expr(cell
->getPort(ID::A
));
529 string b_expr
= make_expr(cell
->getPort(ID::B
));
530 std::string cellFileinfo
= getFileinfo(cell
);
531 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), y_width
, cellFileinfo
.c_str()));
534 a_expr
= "asSInt(" + a_expr
+ ")";
535 // Expand the "A" operand to the result width
536 if (a_width
< y_width
) {
537 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
541 // Shift amount is always unsigned, and needn't be padded to result width,
542 // otherwise, we need to cast the b_expr appropriately
543 if (b_signed
&& !cell
->type
.in(ID($shr
), ID($sshr
), ID($shl
), ID($sshl
), ID($pow
))) {
544 b_expr
= "asSInt(" + b_expr
+ ")";
545 // Expand the "B" operand to the result width
546 if (b_width
< y_width
) {
547 b_expr
= stringf("pad(%s, %d)", b_expr
.c_str(), y_width
);
552 // For the arithmetic ops, expand operand widths to result widths befor performing the operation.
553 // This corresponds (according to iverilog) to what verilog compilers implement.
554 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($
xor), ID($xnor
), ID($
and), ID($
or)))
556 if (a_width
< y_width
) {
557 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
560 if (b_width
< y_width
) {
561 b_expr
= stringf("pad(%s, %d)", b_expr
.c_str(), y_width
);
565 // Assume the FIRRTL width is the width of "A"
566 firrtl_width
= a_width
;
567 auto a_sig
= cell
->getPort(ID::A
);
569 if (cell
->type
== ID($add
)) {
571 firrtl_is_signed
= a_signed
| b_signed
;
572 firrtl_width
= max(a_width
, b_width
);
573 } else if (cell
->type
== ID($sub
)) {
575 firrtl_is_signed
= true;
576 int a_widthInc
= (!a_signed
&& b_signed
) ? 2 : (a_signed
&& !b_signed
) ? 1 : 0;
577 int b_widthInc
= (a_signed
&& !b_signed
) ? 2 : (!a_signed
&& b_signed
) ? 1 : 0;
578 firrtl_width
= max(a_width
+ a_widthInc
, b_width
+ b_widthInc
);
579 } else if (cell
->type
== ID($mul
)) {
581 firrtl_is_signed
= a_signed
| b_signed
;
582 firrtl_width
= a_width
+ b_width
;
583 } else if (cell
->type
== ID($div
)) {
585 firrtl_is_signed
= a_signed
| b_signed
;
586 firrtl_width
= a_width
;
587 } else if (cell
->type
== ID($mod
)) {
589 firrtl_width
= min(a_width
, b_width
);
590 } else if (cell
->type
== ID($
and)) {
593 firrtl_width
= max(a_width
, b_width
);
595 else if (cell
->type
== ID($
or) ) {
598 firrtl_width
= max(a_width
, b_width
);
600 else if (cell
->type
== ID($
xor)) {
603 firrtl_width
= max(a_width
, b_width
);
605 else if (cell
->type
== ID($xnor
)) {
608 firrtl_width
= max(a_width
, b_width
);
610 else if ((cell
->type
== ID($eq
)) | (cell
->type
== ID($eqx
))) {
615 else if ((cell
->type
== ID($ne
)) | (cell
->type
== ID($nex
))) {
620 else if (cell
->type
== ID($gt
)) {
625 else if (cell
->type
== ID($ge
)) {
630 else if (cell
->type
== ID($lt
)) {
635 else if (cell
->type
== ID($le
)) {
640 else if ((cell
->type
== ID($shl
)) | (cell
->type
== ID($sshl
))) {
641 // FIRRTL will widen the result (y) by the amount of the shift.
642 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
643 extract_y_bits
= true;
644 // Is the shift amount constant?
645 auto b_sig
= cell
->getPort(ID::B
);
646 if (b_sig
.is_fully_const()) {
648 int shift_amount
= b_sig
.as_int();
649 b_expr
= std::to_string(shift_amount
);
650 firrtl_width
= a_width
+ shift_amount
;
653 // Convert from FIRRTL left shift semantics.
654 b_expr
= gen_dshl(b_expr
, b_width
);
655 firrtl_width
= a_width
+ (1 << b_width
) - 1;
658 else if ((cell
->type
== ID($shr
)) | (cell
->type
== ID($sshr
))) {
659 // We don't need to extract a specific range of bits.
660 extract_y_bits
= false;
661 // Is the shift amount constant?
662 auto b_sig
= cell
->getPort(ID::B
);
663 if (b_sig
.is_fully_const()) {
665 int shift_amount
= b_sig
.as_int();
666 b_expr
= std::to_string(shift_amount
);
667 firrtl_width
= max(1, a_width
- shift_amount
);
670 firrtl_width
= a_width
;
672 // We'll need to do some special fixups if the source (and thus result) is signed.
673 if (firrtl_is_signed
) {
674 // If this is a "logical" shift right, pretend the source is unsigned.
675 if (cell
->type
== ID($shr
)) {
676 a_expr
= "asUInt(" + a_expr
+ ")";
680 else if ((cell
->type
== ID($logic_and
))) {
682 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
683 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
687 else if ((cell
->type
== ID($logic_or
))) {
689 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
690 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
694 else if ((cell
->type
== ID($pow
))) {
695 if (a_sig
.is_fully_const() && a_sig
.as_int() == 2) {
696 // We'll convert this to a shift. To simplify things, change the a_expr to "1"
697 // so we can use b_expr directly as a shift amount.
698 // Only support 2 ** N (i.e., shift left)
699 // FIRRTL will widen the result (y) by the amount of the shift.
700 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
701 a_expr
= firrtl_is_signed
? "SInt(1)" : "UInt(1)";
702 extract_y_bits
= true;
703 // Is the shift amount constant?
704 auto b_sig
= cell
->getPort(ID::B
);
705 if (b_sig
.is_fully_const()) {
707 int shiftAmount
= b_sig
.as_int();
708 if (shiftAmount
< 0) {
709 log_error("Negative power exponent - %d: %s.%s\n", shiftAmount
, log_id(module
), log_id(cell
));
711 b_expr
= std::to_string(shiftAmount
);
712 firrtl_width
= a_width
+ shiftAmount
;
715 // Convert from FIRRTL left shift semantics.
716 b_expr
= gen_dshl(b_expr
, b_width
);
717 firrtl_width
= a_width
+ (1 << b_width
) - 1;
720 log_error("Non power 2: %s.%s\n", log_id(module
), log_id(cell
));
724 if (!cell
->parameters
.at(ID::B_SIGNED
).as_bool()) {
725 b_expr
= "asUInt(" + b_expr
+ ")";
729 // Deal with $xnor == ~^ (not xor)
730 if (primop
== "xnor") {
731 expr
= stringf("not(xor(%s, %s))", a_expr
.c_str(), b_expr
.c_str());
733 expr
= stringf("%s(%s, %s)", primop
.c_str(), a_expr
.c_str(), b_expr
.c_str());
736 // Deal with FIRRTL's "shift widens" semantics, or the need to widen the FIRRTL result.
737 // If the operation is signed, the FIRRTL width will be 1 one bit larger.
738 if (extract_y_bits
) {
739 expr
= stringf("bits(%s, %d, 0)", expr
.c_str(), y_width
- 1);
740 } else if (firrtl_is_signed
&& (firrtl_width
+ 1) < y_width
) {
741 expr
= stringf("pad(%s, %d)", expr
.c_str(), y_width
);
744 if ((firrtl_is_signed
&& !always_uint
))
745 expr
= stringf("asUInt(%s)", expr
.c_str());
747 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
748 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
753 if (cell
->type
.in(ID($mux
)))
755 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
756 string a_expr
= make_expr(cell
->getPort(ID::A
));
757 string b_expr
= make_expr(cell
->getPort(ID::B
));
758 string s_expr
= make_expr(cell
->getPort(ID::S
));
759 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), width
, cellFileinfo
.c_str()));
761 string expr
= stringf("mux(%s, %s, %s)", s_expr
.c_str(), b_expr
.c_str(), a_expr
.c_str());
763 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
764 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
769 if (cell
->type
.in(ID($mem
)))
771 string mem_id
= make_id(cell
->name
);
772 int abits
= cell
->parameters
.at(ID::ABITS
).as_int();
773 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
774 int size
= cell
->parameters
.at(ID::SIZE
).as_int();
775 memory
m(cell
, mem_id
, abits
, size
, width
);
776 int rd_ports
= cell
->parameters
.at(ID::RD_PORTS
).as_int();
777 int wr_ports
= cell
->parameters
.at(ID::WR_PORTS
).as_int();
779 Const initdata
= cell
->parameters
.at(ID::INIT
);
780 for (State bit
: initdata
.bits
)
781 if (bit
!= State::Sx
)
782 log_error("Memory with initialization data: %s.%s\n", log_id(module
), log_id(cell
));
784 Const rd_clk_enable
= cell
->parameters
.at(ID::RD_CLK_ENABLE
);
785 Const wr_clk_enable
= cell
->parameters
.at(ID::WR_CLK_ENABLE
);
786 Const wr_clk_polarity
= cell
->parameters
.at(ID::WR_CLK_POLARITY
);
788 int offset
= cell
->parameters
.at(ID::OFFSET
).as_int();
790 log_error("Memory with nonzero offset: %s.%s\n", log_id(module
), log_id(cell
));
792 for (int i
= 0; i
< rd_ports
; i
++)
794 if (rd_clk_enable
[i
] != State::S0
)
795 log_error("Clocked read port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
797 SigSpec addr_sig
= cell
->getPort(ID::RD_ADDR
).extract(i
*abits
, abits
);
798 SigSpec data_sig
= cell
->getPort(ID::RD_DATA
).extract(i
*width
, width
);
799 string addr_expr
= make_expr(addr_sig
);
800 string
name(stringf("%s.r%d", m
.name
.c_str(), i
));
801 bool clk_enable
= false;
802 bool clk_parity
= true;
803 bool transparency
= false;
804 SigSpec ena_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
805 SigSpec clk_sig
= RTLIL::SigSpec(RTLIL::State::S0
, 1);
806 read_port
rp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, ena_sig
, addr_sig
);
807 m
.add_memory_read_port(rp
);
808 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
809 register_reverse_wire_map(stringf("%s.data", name
.c_str()), data_sig
);
812 for (int i
= 0; i
< wr_ports
; i
++)
814 if (wr_clk_enable
[i
] != State::S1
)
815 log_error("Unclocked write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
817 if (wr_clk_polarity
[i
] != State::S1
)
818 log_error("Negedge write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
820 string
name(stringf("%s.w%d", m
.name
.c_str(), i
));
821 bool clk_enable
= true;
822 bool clk_parity
= true;
823 bool transparency
= false;
824 SigSpec addr_sig
=cell
->getPort(ID::WR_ADDR
).extract(i
*abits
, abits
);
825 string addr_expr
= make_expr(addr_sig
);
826 SigSpec data_sig
=cell
->getPort(ID::WR_DATA
).extract(i
*width
, width
);
827 string data_expr
= make_expr(data_sig
);
828 SigSpec clk_sig
= cell
->getPort(ID::WR_CLK
).extract(i
);
829 string clk_expr
= make_expr(clk_sig
);
831 SigSpec wen_sig
= cell
->getPort(ID::WR_EN
).extract(i
*width
, width
);
832 string wen_expr
= make_expr(wen_sig
[0]);
834 for (int i
= 1; i
< GetSize(wen_sig
); i
++)
835 if (wen_sig
[0] != wen_sig
[i
])
836 log_error("Complex write enable on port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
838 SigSpec mask_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
839 write_port
wp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, wen_sig
[0], addr_sig
, mask_sig
);
840 m
.add_memory_write_port(wp
);
841 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), name
.c_str(), data_expr
.c_str()));
842 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
848 if (cell
->type
.in(ID($memwr
), ID($memrd
), ID($meminit
)))
850 std::string cell_type
= fid(cell
->type
);
851 std::string mem_id
= make_id(cell
->parameters
[ID::MEMID
].decode_string());
852 int abits
= cell
->parameters
.at(ID::ABITS
).as_int();
853 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
854 memory
*mp
= nullptr;
855 if (cell
->type
== ID($meminit
) ) {
856 log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module
), log_id(cell
), mem_id
.c_str());
858 // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
859 auto addrSig
= cell
->getPort(ID::ADDR
);
860 auto dataSig
= cell
->getPort(ID::DATA
);
861 auto enableSig
= cell
->getPort(ID::EN
);
862 auto clockSig
= cell
->getPort(ID::CLK
);
863 Const clk_enable
= cell
->parameters
.at(ID::CLK_ENABLE
);
864 Const clk_polarity
= cell
->parameters
.at(ID::CLK_POLARITY
);
866 // Do we already have an entry for this memory?
867 if (memories
.count(mem_id
) == 0) {
868 memory
m(cell
, mem_id
, abits
, 0, width
);
871 mp
= &memories
.at(mem_id
);
873 bool transparency
= false;
874 string data_expr
= make_expr(dataSig
);
875 if (cell
->type
.in(ID($memwr
))) {
876 portNum
= (int) mp
->write_ports
.size();
877 write_port
wp(stringf("%s.w%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
, dataSig
);
878 mp
->add_memory_write_port(wp
);
879 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), wp
.name
.c_str(), data_expr
.c_str()));
880 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
881 } else if (cell
->type
.in(ID($memrd
))) {
882 portNum
= (int) mp
->read_ports
.size();
883 read_port
rp(stringf("%s.r%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
);
884 mp
->add_memory_read_port(rp
);
885 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
886 register_reverse_wire_map(stringf("%s.data", rp
.name
.c_str()), dataSig
);
892 if (cell
->type
.in(ID($dff
)))
894 bool clkpol
= cell
->parameters
.at(ID::CLK_POLARITY
).as_bool();
896 log_error("Negative edge clock on FF %s.%s.\n", log_id(module
), log_id(cell
));
898 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
899 string expr
= make_expr(cell
->getPort(ID::D
));
900 string clk_expr
= "asClock(" + make_expr(cell
->getPort(ID::CLK
)) + ")";
902 wire_decls
.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id
.c_str(), width
, clk_expr
.c_str(), cellFileinfo
.c_str()));
904 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
905 register_reverse_wire_map(y_id
, cell
->getPort(ID::Q
));
910 // This may be a parameterized module - paramod.
911 if (cell
->type
.begins_with("$paramod"))
913 process_instance(cell
, wire_exprs
);
916 if (cell
->type
== ID($shiftx
)) {
917 // assign y = a[b +: y_width];
918 // We'll extract the correct bits as part of the primop.
920 string a_expr
= make_expr(cell
->getPort(ID::A
));
921 // Get the initial bit selector
922 string b_expr
= make_expr(cell
->getPort(ID::B
));
923 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
925 if (cell
->getParam(ID::B_SIGNED
).as_bool()) {
926 // Use validif to constrain the selection (test the sign bit)
927 auto b_string
= b_expr
.c_str();
928 int b_sign
= cell
->parameters
.at(ID::B_WIDTH
).as_int() - 1;
929 b_expr
= stringf("validif(not(bits(%s, %d, %d)), %s)", b_string
, b_sign
, b_sign
, b_string
);
931 string expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_expr
.c_str());
933 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
934 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
937 if (cell
->type
== ID($shift
)) {
938 // assign y = a >> b;
939 // where b may be negative
941 string a_expr
= make_expr(cell
->getPort(ID::A
));
942 string b_expr
= make_expr(cell
->getPort(ID::B
));
943 auto b_string
= b_expr
.c_str();
945 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
947 if (cell
->getParam(ID::B_SIGNED
).as_bool()) {
948 // We generate a left or right shift based on the sign of b.
949 std::string dshl
= stringf("bits(dshl(%s, %s), 0, %d)", a_expr
.c_str(), gen_dshl(b_expr
, b_width
).c_str(), y_width
);
950 std::string dshr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
951 expr
= stringf("mux(%s < 0, %s, %s)",
957 expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
959 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
960 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
963 if (cell
->type
== ID($pos
)) {
966 string a_expr
= make_expr(cell
->getPort(ID::A
));
967 // Verilog appears to treat the result as signed, so if the result is wider than "A",
969 if (a_width
< y_width
) {
970 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
972 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
973 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), a_expr
.c_str()));
974 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
977 log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell
->type
), log_id(module
), log_id(cell
));
980 for (auto conn
: module
->connections())
982 string y_id
= next_id();
983 int y_width
= GetSize(conn
.first
);
984 string expr
= make_expr(conn
.second
);
986 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
987 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
988 register_reverse_wire_map(y_id
, conn
.first
);
991 for (auto wire
: module
->wires())
994 std::string wireFileinfo
= getFileinfo(wire
);
996 if (wire
->port_input
)
1000 bool is_valid
= false;
1001 bool make_unconn_id
= false;
1003 while (cursor
< wire
->width
)
1005 int chunk_width
= 1;
1008 SigBit
start_bit(wire
, cursor
);
1010 if (reverse_wire_map
.count(start_bit
))
1012 pair
<string
, int> start_map
= reverse_wire_map
.at(start_bit
);
1014 while (cursor
+chunk_width
< wire
->width
)
1016 SigBit
stop_bit(wire
, cursor
+chunk_width
);
1018 if (reverse_wire_map
.count(stop_bit
) == 0)
1021 pair
<string
, int> stop_map
= reverse_wire_map
.at(stop_bit
);
1022 stop_map
.second
-= chunk_width
;
1024 if (start_map
!= stop_map
)
1030 new_expr
= stringf("bits(%s, %d, %d)", start_map
.first
.c_str(),
1031 start_map
.second
+ chunk_width
- 1, start_map
.second
);
1036 if (unconn_id
.empty()) {
1037 unconn_id
= next_id();
1038 make_unconn_id
= true;
1040 new_expr
= unconn_id
;
1046 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
1048 cursor
+= chunk_width
;
1052 if (make_unconn_id
) {
1053 wire_decls
.push_back(stringf(" wire %s: UInt<1> %s\n", unconn_id
.c_str(), wireFileinfo
.c_str()));
1054 // `invalid` is a firrtl construction for simulation so we will not
1055 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1056 // a specific line of verilog code.
1057 wire_decls
.push_back(stringf(" %s is invalid\n", unconn_id
.c_str()));
1059 wire_exprs
.push_back(stringf(" %s <= %s %s\n", make_id(wire
->name
), expr
.c_str(), wireFileinfo
.c_str()));
1061 if (make_unconn_id
) {
1064 // `invalid` is a firrtl construction for simulation so we will not
1065 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1066 // a specific line of verilog code.
1067 wire_decls
.push_back(stringf(" %s is invalid\n", make_id(wire
->name
)));
1071 for (auto str
: port_decls
)
1076 for (auto str
: wire_decls
)
1081 // If we have any memory definitions, output them.
1082 for (auto kv
: memories
) {
1083 memory
&m
= kv
.second
;
1084 f
<< stringf(" mem %s:\n", m
.name
.c_str());
1085 f
<< stringf(" data-type => UInt<%d>\n", m
.width
);
1086 f
<< stringf(" depth => %d\n", m
.size
);
1087 for (int i
= 0; i
< (int) m
.read_ports
.size(); i
+= 1) {
1088 f
<< stringf(" reader => r%d\n", i
);
1090 for (int i
= 0; i
< (int) m
.write_ports
.size(); i
+= 1) {
1091 f
<< stringf(" writer => w%d\n", i
);
1093 f
<< stringf(" read-latency => %d\n", m
.read_latency
);
1094 f
<< stringf(" write-latency => %d\n", m
.write_latency
);
1095 f
<< stringf(" read-under-write => undefined\n");
1099 for (auto str
: cell_exprs
)
1104 for (auto str
: wire_exprs
)
1112 // Blackboxes should be emitted as `extmodule`s in firrtl. Only ports are
1113 // emitted in such a case.
1114 if (module
->get_blackbox_attribute())
1121 struct FirrtlBackend
: public Backend
{
1122 FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
1123 void help() YS_OVERRIDE
1125 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1127 log(" write_firrtl [options] [filename]\n");
1129 log("Write a FIRRTL netlist of the current design.\n");
1130 log("The following commands are executed by this command:\n");
1134 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1136 size_t argidx
= args
.size(); // We aren't expecting any arguments.
1138 // If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
1139 if (filename
== "") {
1140 if (argidx
> 0 && args
[argidx
- 1][0] != '-') {
1141 // extra_args and friends need to see this argument.
1143 filename
= args
[argidx
];
1146 extra_args(f
, filename
, args
, argidx
);
1148 if (!design
->full_selection())
1149 log_cmd_error("This command only operates on fully selected designs!\n");
1151 log_header(design
, "Executing FIRRTL backend.\n");
1154 Pass::call(design
, stringf("pmuxtree"));
1159 // Get the top module, or a reasonable facsimile - we need something for the circuit name.
1160 Module
*top
= design
->top_module();
1161 Module
*last
= nullptr;
1162 // Generate module and wire names.
1163 for (auto module
: design
->modules()) {
1164 make_id(module
->name
);
1166 if (top
== nullptr && module
->get_bool_attribute(ID::top
)) {
1169 for (auto wire
: module
->wires())
1171 make_id(wire
->name
);
1177 std::string circuitFileinfo
= getFileinfo(top
);
1178 *f
<< stringf("circuit %s: %s\n", make_id(top
->name
), circuitFileinfo
.c_str());
1180 for (auto module
: design
->modules())
1182 FirrtlWorker
worker(module
, *f
, design
);
1191 PRIVATE_NAMESPACE_END