Refactor fileinfo emission characters to single location
[yosys.git] / backends / firrtl / firrtl.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
26 #include <algorithm>
27 #include <string>
28 #include <vector>
29 #include <cmath>
30
31 USING_YOSYS_NAMESPACE
32 PRIVATE_NAMESPACE_BEGIN
33
34 pool<string> used_names;
35 dict<IdString, string> namecache;
36 int autoid_counter;
37
38 typedef unsigned FDirection;
39 static const FDirection FD_NODIRECTION = 0x0;
40 static const FDirection FD_IN = 0x1;
41 static const FDirection FD_OUT = 0x2;
42 static const FDirection FD_INOUT = 0x3;
43 static const int FIRRTL_MAX_DSH_WIDTH_ERROR = 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
44
45 // Shamelessly copied from ilang_backend.cc. Something better is surely possible here.
46 void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true)
47 {
48 if (width < 0)
49 width = data.bits.size() - offset;
50 if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
51 if (width == 32 && autoint) {
52 int32_t val = 0;
53 for (int i = 0; i < width; i++) {
54 log_assert(offset+i < (int)data.bits.size());
55 switch (data.bits[offset+i]) {
56 case RTLIL::S0: break;
57 case RTLIL::S1: val |= 1 << i; break;
58 default: val = -1; break;
59 }
60 }
61 if (val >= 0) {
62 f << stringf("%d", val);
63 return;
64 }
65 }
66 f << stringf("%d'", width);
67 for (int i = offset+width-1; i >= offset; i--) {
68 log_assert(i < (int)data.bits.size());
69 switch (data.bits[i]) {
70 case RTLIL::S0: f << stringf("0"); break;
71 case RTLIL::S1: f << stringf("1"); break;
72 case RTLIL::Sx: f << stringf("x"); break;
73 case RTLIL::Sz: f << stringf("z"); break;
74 case RTLIL::Sa: f << stringf("-"); break;
75 case RTLIL::Sm: f << stringf("m"); break;
76 }
77 }
78 } else {
79 f << stringf("\"");
80 std::string str = data.decode_string();
81 for (size_t i = 0; i < str.size(); i++) {
82 if (str[i] == '\n')
83 f << stringf("\\n");
84 else if (str[i] == '\t')
85 f << stringf("\\t");
86 else if (str[i] < 32)
87 f << stringf("\\%03o", str[i]);
88 else if (str[i] == '"')
89 f << stringf("\\\"");
90 else if (str[i] == '\\')
91 f << stringf("\\\\");
92 else
93 f << str[i];
94 }
95 f << stringf("\"");
96 }
97 }
98
99 std::string getFileinfo(dict<RTLIL::IdString, RTLIL::Const> attributes)
100 {
101 std::ostringstream fileinfo;
102 for (auto &it : attributes) {
103 if (it.first == "\\src") {
104 fileinfo << "@[";
105 dump_const(fileinfo, it.second);
106 fileinfo << "]";
107 }
108 }
109 return fileinfo.str();
110 }
111
112 // Get a port direction with respect to a specific module.
113 FDirection getPortFDirection(IdString id, Module *module)
114 {
115 Wire *wire = module->wires_.at(id);
116 FDirection direction = FD_NODIRECTION;
117 if (wire && wire->port_id)
118 {
119 if (wire->port_input)
120 direction |= FD_IN;
121 if (wire->port_output)
122 direction |= FD_OUT;
123 }
124 return direction;
125 }
126
127 string next_id()
128 {
129 string new_id;
130
131 while (1) {
132 new_id = stringf("_%d", autoid_counter++);
133 if (used_names.count(new_id) == 0) break;
134 }
135
136 used_names.insert(new_id);
137 return new_id;
138 }
139
140 const char *make_id(IdString id)
141 {
142 if (namecache.count(id) != 0)
143 return namecache.at(id).c_str();
144
145 string new_id = log_id(id);
146
147 for (int i = 0; i < GetSize(new_id); i++)
148 {
149 char &ch = new_id[i];
150 if ('a' <= ch && ch <= 'z') continue;
151 if ('A' <= ch && ch <= 'Z') continue;
152 if ('0' <= ch && ch <= '9' && i != 0) continue;
153 if ('_' == ch) continue;
154 ch = '_';
155 }
156
157 while (used_names.count(new_id) != 0)
158 new_id += '_';
159
160 namecache[id] = new_id;
161 used_names.insert(new_id);
162 return namecache.at(id).c_str();
163 }
164
165 struct FirrtlWorker
166 {
167 Module *module;
168 std::ostream &f;
169
170 dict<SigBit, pair<string, int>> reverse_wire_map;
171 string unconn_id;
172 RTLIL::Design *design;
173 std::string indent;
174
175 // Define read/write ports and memories.
176 // We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
177 // For the moment, we don't handle $readmemh or $readmemb.
178 // These will be part of a subsequent PR.
179 struct read_port {
180 string name;
181 bool clk_enable;
182 bool clk_parity;
183 bool transparent;
184 RTLIL::SigSpec clk;
185 RTLIL::SigSpec ena;
186 RTLIL::SigSpec addr;
187 read_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr) : name(name), clk_enable(clk_enable), clk_parity(clk_parity), transparent(transparent), clk(clk), ena(ena), addr(addr) {
188 // Current (3/13/2019) conventions:
189 // generate a constant 0 for clock and a constant 1 for enable if they are undefined.
190 if (!clk.is_fully_def())
191 this->clk = SigSpec(State::S0);
192 if (!ena.is_fully_def())
193 this->ena = SigSpec(State::S1);
194 }
195 string gen_read(const char * indent) {
196 string addr_expr = make_expr(addr);
197 string ena_expr = make_expr(ena);
198 string clk_expr = make_expr(clk);
199 string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
200 string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
201 string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
202 return addr_str + ena_str + clk_str;
203 }
204 };
205 struct write_port : read_port {
206 RTLIL::SigSpec mask;
207 write_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr, RTLIL::SigSpec mask) : read_port(name, clk_enable, clk_parity, transparent, clk, ena, addr), mask(mask) {
208 if (!clk.is_fully_def())
209 this->clk = SigSpec(RTLIL::Const(0));
210 if (!ena.is_fully_def())
211 this->ena = SigSpec(RTLIL::Const(0));
212 if (!mask.is_fully_def())
213 this->ena = SigSpec(RTLIL::Const(1));
214 }
215 string gen_read(const char * /* indent */) {
216 log_error("gen_read called on write_port: %s\n", name.c_str());
217 return stringf("gen_read called on write_port: %s\n", name.c_str());
218 }
219 string gen_write(const char * indent) {
220 string addr_expr = make_expr(addr);
221 string ena_expr = make_expr(ena);
222 string clk_expr = make_expr(clk);
223 string mask_expr = make_expr(mask);
224 string mask_str = stringf("%s%s.mask <= %s\n", indent, name.c_str(), mask_expr.c_str());
225 string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
226 string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
227 string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
228 return addr_str + ena_str + clk_str + mask_str;
229 }
230 };
231 /* Memories defined within this module. */
232 struct memory {
233 Cell *pCell; // for error reporting
234 string name; // memory name
235 int abits; // number of address bits
236 int size; // size (in units) of the memory
237 int width; // size (in bits) of each element
238 int read_latency;
239 int write_latency;
240 vector<read_port> read_ports;
241 vector<write_port> write_ports;
242 std::string init_file;
243 std::string init_file_srcFileSpec;
244 string srcLine;
245 memory(Cell *pCell, string name, int abits, int size, int width) : pCell(pCell), name(name), abits(abits), size(size), width(width), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
246 // Provide defaults for abits or size if one (but not the other) is specified.
247 if (this->abits == 0 && this->size != 0) {
248 this->abits = ceil_log2(this->size);
249 } else if (this->abits != 0 && this->size == 0) {
250 this->size = 1 << this->abits;
251 }
252 // Sanity-check this construction.
253 if (this->name == "") {
254 log_error("Nameless memory%s\n", this->atLine());
255 }
256 if (this->abits == 0 && this->size == 0) {
257 log_error("Memory %s has zero address bits and size%s\n", this->name.c_str(), this->atLine());
258 }
259 if (this->width == 0) {
260 log_error("Memory %s has zero width%s\n", this->name.c_str(), this->atLine());
261 }
262 }
263 // We need a default constructor for the dict insert.
264 memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
265
266 const char *atLine() {
267 if (srcLine == "") {
268 if (pCell) {
269 auto p = pCell->attributes.find("\\src");
270 srcLine = " at " + p->second.decode_string();
271 }
272 }
273 return srcLine.c_str();
274 }
275 void add_memory_read_port(read_port &rp) {
276 read_ports.push_back(rp);
277 }
278 void add_memory_write_port(write_port &wp) {
279 write_ports.push_back(wp);
280 }
281 void add_memory_file(std::string init_file, std::string init_file_srcFileSpec) {
282 this->init_file = init_file;
283 this->init_file_srcFileSpec = init_file_srcFileSpec;
284 }
285
286 };
287 dict<string, memory> memories;
288
289 void register_memory(memory &m)
290 {
291 memories[m.name] = m;
292 }
293
294 void register_reverse_wire_map(string id, SigSpec sig)
295 {
296 for (int i = 0; i < GetSize(sig); i++)
297 reverse_wire_map[sig[i]] = make_pair(id, i);
298 }
299
300 FirrtlWorker(Module *module, std::ostream &f, RTLIL::Design *theDesign) : module(module), f(f), design(theDesign), indent(" ")
301 {
302 }
303
304 static string make_expr(const SigSpec &sig)
305 {
306 string expr;
307
308 for (auto chunk : sig.chunks())
309 {
310 string new_expr;
311
312 if (chunk.wire == nullptr)
313 {
314 std::vector<RTLIL::State> bits = chunk.data;
315 new_expr = stringf("UInt<%d>(\"h", GetSize(bits));
316
317 while (GetSize(bits) % 4 != 0)
318 bits.push_back(State::S0);
319
320 for (int i = GetSize(bits)-4; i >= 0; i -= 4)
321 {
322 int val = 0;
323 if (bits[i+0] == State::S1) val += 1;
324 if (bits[i+1] == State::S1) val += 2;
325 if (bits[i+2] == State::S1) val += 4;
326 if (bits[i+3] == State::S1) val += 8;
327 new_expr.push_back(val < 10 ? '0' + val : 'a' + val - 10);
328 }
329
330 new_expr += "\")";
331 }
332 else if (chunk.offset == 0 && chunk.width == chunk.wire->width)
333 {
334 new_expr = make_id(chunk.wire->name);
335 }
336 else
337 {
338 string wire_id = make_id(chunk.wire->name);
339 new_expr = stringf("bits(%s, %d, %d)", wire_id.c_str(), chunk.offset + chunk.width - 1, chunk.offset);
340 }
341
342 if (expr.empty())
343 expr = new_expr;
344 else
345 expr = "cat(" + new_expr + ", " + expr + ")";
346 }
347
348 return expr;
349 }
350
351 std::string fid(RTLIL::IdString internal_id)
352 {
353 return make_id(internal_id);
354 }
355
356 std::string cellname(RTLIL::Cell *cell)
357 {
358 return fid(cell->name).c_str();
359 }
360
361 void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
362 {
363 std::string cell_type = fid(cell->type);
364 std::string instanceOf;
365 // If this is a parameterized module, its parent module is encoded in the cell type
366 if (cell->type.begins_with("$paramod"))
367 {
368 std::string::iterator it;
369 for (it = cell_type.begin(); it < cell_type.end(); it++)
370 {
371 switch (*it) {
372 case '\\': /* FALL_THROUGH */
373 case '=': /* FALL_THROUGH */
374 case '\'': /* FALL_THROUGH */
375 case '$': instanceOf.append("_"); break;
376 default: instanceOf.append(1, *it); break;
377 }
378 }
379 }
380 else
381 {
382 instanceOf = cell_type;
383 }
384
385 std::string cell_name = cellname(cell);
386 std::string cell_name_comment;
387 if (cell_name != fid(cell->name))
388 cell_name_comment = " /* " + fid(cell->name) + " */ ";
389 else
390 cell_name_comment = "";
391 // Find the module corresponding to this instance.
392 auto instModule = design->module(cell->type);
393 // If there is no instance for this, just return.
394 if (instModule == NULL)
395 {
396 log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str());
397 return;
398 }
399 auto cellFileinfo = getFileinfo(cell->attributes);
400 wire_exprs.push_back(stringf("%s" "inst %s%s of %s %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceOf.c_str(), cellFileinfo.c_str()));
401
402 for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
403 if (it->second.size() > 0) {
404 const SigSpec &secondSig = it->second;
405 const std::string firstName = cell_name + "." + make_id(it->first);
406 const std::string secondExpr = make_expr(secondSig);
407 // Find the direction for this port.
408 FDirection dir = getPortFDirection(it->first, instModule);
409 std::string sourceExpr, sinkExpr;
410 const SigSpec *sinkSig = nullptr;
411 switch (dir) {
412 case FD_INOUT:
413 log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second));
414 /* FALLTHRU */
415 case FD_OUT:
416 sourceExpr = firstName;
417 sinkExpr = secondExpr;
418 sinkSig = &secondSig;
419 break;
420 case FD_NODIRECTION:
421 log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second));
422 /* FALLTHRU */
423 case FD_IN:
424 sourceExpr = secondExpr;
425 sinkExpr = firstName;
426 break;
427 default:
428 log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
429 break;
430 }
431 // Check for subfield assignment.
432 std::string bitsString = "bits(";
433 if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) {
434 if (sinkSig == nullptr)
435 log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str());
436 // Don't generate the assignment here.
437 // Add the source and sink to the "reverse_wire_map" and we'll output the assignment
438 // as part of the coalesced subfield assignments for this wire.
439 register_reverse_wire_map(sourceExpr, *sinkSig);
440 } else {
441 wire_exprs.push_back(stringf("\n%s%s <= %s %s", indent.c_str(), sinkExpr.c_str(), sourceExpr.c_str(), cellFileinfo.c_str()));
442 }
443 }
444 }
445 wire_exprs.push_back(stringf("\n"));
446
447 }
448
449 // Given an expression for a shift amount, and a maximum width,
450 // generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
451 std::string gen_dshl(const string b_expr, const int b_width)
452 {
453 string result = b_expr;
454 if (b_width >= FIRRTL_MAX_DSH_WIDTH_ERROR) {
455 int max_shift_width_bits = FIRRTL_MAX_DSH_WIDTH_ERROR - 1;
456 string max_shift_string = stringf("UInt<%d>(%d)", max_shift_width_bits, (1<<max_shift_width_bits) - 1);
457 // Deal with the difference in semantics between FIRRTL and verilog
458 result = stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr.c_str(), max_shift_string.c_str(), max_shift_string.c_str(), b_expr.c_str(), max_shift_width_bits - 1);
459 }
460 return result;
461 }
462
463 void run()
464 {
465 auto moduleFileinfo = getFileinfo(module->attributes);
466 f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
467 vector<string> port_decls, wire_decls, cell_exprs, wire_exprs;
468
469 for (auto wire : module->wires())
470 {
471 const auto wireName = make_id(wire->name);
472 auto wireFileinfo = getFileinfo(wire->attributes);
473
474 // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
475 if (wire->attributes.count("\\init")) {
476 log_warning("Initial value (%s) for (%s.%s) not supported\n",
477 wire->attributes.at("\\init").as_string().c_str(),
478 log_id(module), log_id(wire));
479 }
480 if (wire->port_id)
481 {
482 if (wire->port_input && wire->port_output)
483 log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
484 port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
485 wireName, wire->width, wireFileinfo.c_str()));
486 }
487 else
488 {
489 wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", wireName, wire->width, wireFileinfo.c_str()));
490 }
491 }
492
493 for (auto cell : module->cells())
494 {
495 static Const ndef(0, 0);
496
497 // Is this cell is a module instance?
498 if (cell->type[0] != '$')
499 {
500 process_instance(cell, wire_exprs);
501 continue;
502 }
503 // Not a module instance. Set up cell properties
504 bool extract_y_bits = false; // Assume no extraction of final bits will be required.
505 int a_width = cell->parameters.at("\\A_WIDTH", ndef).as_int(); // The width of "A"
506 int b_width = cell->parameters.at("\\B_WIDTH", ndef).as_int(); // The width of "A"
507 const int y_width = cell->parameters.at("\\Y_WIDTH", ndef).as_int(); // The width of the result
508 const bool a_signed = cell->parameters.at("\\A_SIGNED", ndef).as_bool();
509 const bool b_signed = cell->parameters.at("\\B_SIGNED", ndef).as_bool();
510 bool firrtl_is_signed = a_signed; // The result is signed (subsequent code may change this).
511 int firrtl_width = 0;
512 string primop;
513 bool always_uint = false;
514 string y_id = make_id(cell->name);
515
516 if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
517 {
518 string a_expr = make_expr(cell->getPort("\\A"));
519 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
520
521 if (a_signed) {
522 a_expr = "asSInt(" + a_expr + ")";
523 }
524
525 // Don't use the results of logical operations (a single bit) to control padding
526 if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) {
527 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
528 }
529
530 // Assume the FIRRTL width is a single bit.
531 firrtl_width = 1;
532 if (cell->type == "$not") primop = "not";
533 else if (cell->type == "$neg") {
534 primop = "neg";
535 firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
536 firrtl_width = a_width;
537 } else if (cell->type == "$logic_not") {
538 primop = "eq";
539 a_expr = stringf("%s, UInt(0)", a_expr.c_str());
540 }
541 else if (cell->type == "$reduce_and") primop = "andr";
542 else if (cell->type == "$reduce_or") primop = "orr";
543 else if (cell->type == "$reduce_xor") primop = "xorr";
544 else if (cell->type == "$reduce_xnor") {
545 primop = "not";
546 a_expr = stringf("xorr(%s)", a_expr.c_str());
547 }
548 else if (cell->type == "$reduce_bool") {
549 primop = "neq";
550 // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
551 a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
552 }
553
554 string expr = stringf("%s(%s)", primop.c_str(), a_expr.c_str());
555
556 if ((firrtl_is_signed && !always_uint))
557 expr = stringf("asUInt(%s)", expr.c_str());
558
559 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
560 register_reverse_wire_map(y_id, cell->getPort("\\Y"));
561
562 continue;
563 }
564 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx",
565 "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
566 "$logic_and", "$logic_or", "$pow"))
567 {
568 string a_expr = make_expr(cell->getPort("\\A"));
569 string b_expr = make_expr(cell->getPort("\\B"));
570 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
571
572 if (a_signed) {
573 a_expr = "asSInt(" + a_expr + ")";
574 // Expand the "A" operand to the result width
575 if (a_width < y_width) {
576 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
577 a_width = y_width;
578 }
579 }
580 // Shift amount is always unsigned, and needn't be padded to result width,
581 // otherwise, we need to cast the b_expr appropriately
582 if (b_signed && !cell->type.in("$shr", "$sshr", "$shl", "$sshl", "$pow")) {
583 b_expr = "asSInt(" + b_expr + ")";
584 // Expand the "B" operand to the result width
585 if (b_width < y_width) {
586 b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
587 b_width = y_width;
588 }
589 }
590
591 // For the arithmetic ops, expand operand widths to result widths befor performing the operation.
592 // This corresponds (according to iverilog) to what verilog compilers implement.
593 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or"))
594 {
595 if (a_width < y_width) {
596 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
597 a_width = y_width;
598 }
599 if (b_width < y_width) {
600 b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
601 b_width = y_width;
602 }
603 }
604 // Assume the FIRRTL width is the width of "A"
605 firrtl_width = a_width;
606 auto a_sig = cell->getPort("\\A");
607
608 if (cell->type == "$add") {
609 primop = "add";
610 firrtl_is_signed = a_signed | b_signed;
611 firrtl_width = max(a_width, b_width);
612 } else if (cell->type == "$sub") {
613 primop = "sub";
614 firrtl_is_signed = true;
615 int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
616 int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
617 firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
618 } else if (cell->type == "$mul") {
619 primop = "mul";
620 firrtl_is_signed = a_signed | b_signed;
621 firrtl_width = a_width + b_width;
622 } else if (cell->type == "$div") {
623 primop = "div";
624 firrtl_is_signed = a_signed | b_signed;
625 firrtl_width = a_width;
626 } else if (cell->type == "$mod") {
627 primop = "rem";
628 firrtl_width = min(a_width, b_width);
629 } else if (cell->type == "$and") {
630 primop = "and";
631 always_uint = true;
632 firrtl_width = max(a_width, b_width);
633 }
634 else if (cell->type == "$or" ) {
635 primop = "or";
636 always_uint = true;
637 firrtl_width = max(a_width, b_width);
638 }
639 else if (cell->type == "$xor") {
640 primop = "xor";
641 always_uint = true;
642 firrtl_width = max(a_width, b_width);
643 }
644 else if (cell->type == "$xnor") {
645 primop = "xnor";
646 always_uint = true;
647 firrtl_width = max(a_width, b_width);
648 }
649 else if ((cell->type == "$eq") | (cell->type == "$eqx")) {
650 primop = "eq";
651 always_uint = true;
652 firrtl_width = 1;
653 }
654 else if ((cell->type == "$ne") | (cell->type == "$nex")) {
655 primop = "neq";
656 always_uint = true;
657 firrtl_width = 1;
658 }
659 else if (cell->type == "$gt") {
660 primop = "gt";
661 always_uint = true;
662 firrtl_width = 1;
663 }
664 else if (cell->type == "$ge") {
665 primop = "geq";
666 always_uint = true;
667 firrtl_width = 1;
668 }
669 else if (cell->type == "$lt") {
670 primop = "lt";
671 always_uint = true;
672 firrtl_width = 1;
673 }
674 else if (cell->type == "$le") {
675 primop = "leq";
676 always_uint = true;
677 firrtl_width = 1;
678 }
679 else if ((cell->type == "$shl") | (cell->type == "$sshl")) {
680 // FIRRTL will widen the result (y) by the amount of the shift.
681 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
682 extract_y_bits = true;
683 // Is the shift amount constant?
684 auto b_sig = cell->getPort("\\B");
685 if (b_sig.is_fully_const()) {
686 primop = "shl";
687 int shift_amount = b_sig.as_int();
688 b_expr = std::to_string(shift_amount);
689 firrtl_width = a_width + shift_amount;
690 } else {
691 primop = "dshl";
692 // Convert from FIRRTL left shift semantics.
693 b_expr = gen_dshl(b_expr, b_width);
694 firrtl_width = a_width + (1 << b_width) - 1;
695 }
696 }
697 else if ((cell->type == "$shr") | (cell->type == "$sshr")) {
698 // We don't need to extract a specific range of bits.
699 extract_y_bits = false;
700 // Is the shift amount constant?
701 auto b_sig = cell->getPort("\\B");
702 if (b_sig.is_fully_const()) {
703 primop = "shr";
704 int shift_amount = b_sig.as_int();
705 b_expr = std::to_string(shift_amount);
706 firrtl_width = max(1, a_width - shift_amount);
707 } else {
708 primop = "dshr";
709 firrtl_width = a_width;
710 }
711 // We'll need to do some special fixups if the source (and thus result) is signed.
712 if (firrtl_is_signed) {
713 // If this is a "logical" shift right, pretend the source is unsigned.
714 if (cell->type == "$shr") {
715 a_expr = "asUInt(" + a_expr + ")";
716 }
717 }
718 }
719 else if ((cell->type == "$logic_and")) {
720 primop = "and";
721 a_expr = "neq(" + a_expr + ", UInt(0))";
722 b_expr = "neq(" + b_expr + ", UInt(0))";
723 always_uint = true;
724 firrtl_width = 1;
725 }
726 else if ((cell->type == "$logic_or")) {
727 primop = "or";
728 a_expr = "neq(" + a_expr + ", UInt(0))";
729 b_expr = "neq(" + b_expr + ", UInt(0))";
730 always_uint = true;
731 firrtl_width = 1;
732 }
733 else if ((cell->type == "$pow")) {
734 if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
735 // We'll convert this to a shift. To simplify things, change the a_expr to "1"
736 // so we can use b_expr directly as a shift amount.
737 // Only support 2 ** N (i.e., shift left)
738 // FIRRTL will widen the result (y) by the amount of the shift.
739 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
740 a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)";
741 extract_y_bits = true;
742 // Is the shift amount constant?
743 auto b_sig = cell->getPort("\\B");
744 if (b_sig.is_fully_const()) {
745 primop = "shl";
746 int shiftAmount = b_sig.as_int();
747 if (shiftAmount < 0) {
748 log_error("Negative power exponent - %d: %s.%s\n", shiftAmount, log_id(module), log_id(cell));
749 }
750 b_expr = std::to_string(shiftAmount);
751 firrtl_width = a_width + shiftAmount;
752 } else {
753 primop = "dshl";
754 // Convert from FIRRTL left shift semantics.
755 b_expr = gen_dshl(b_expr, b_width);
756 firrtl_width = a_width + (1 << b_width) - 1;
757 }
758 } else {
759 log_error("Non power 2: %s.%s\n", log_id(module), log_id(cell));
760 }
761 }
762
763 if (!cell->parameters.at("\\B_SIGNED").as_bool()) {
764 b_expr = "asUInt(" + b_expr + ")";
765 }
766
767 string expr;
768 // Deal with $xnor == ~^ (not xor)
769 if (primop == "xnor") {
770 expr = stringf("not(xor(%s, %s))", a_expr.c_str(), b_expr.c_str());
771 } else {
772 expr = stringf("%s(%s, %s)", primop.c_str(), a_expr.c_str(), b_expr.c_str());
773 }
774
775 // Deal with FIRRTL's "shift widens" semantics, or the need to widen the FIRRTL result.
776 // If the operation is signed, the FIRRTL width will be 1 one bit larger.
777 if (extract_y_bits) {
778 expr = stringf("bits(%s, %d, 0)", expr.c_str(), y_width - 1);
779 } else if (firrtl_is_signed && (firrtl_width + 1) < y_width) {
780 expr = stringf("pad(%s, %d)", expr.c_str(), y_width);
781 }
782
783 if ((firrtl_is_signed && !always_uint))
784 expr = stringf("asUInt(%s)", expr.c_str());
785
786 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
787 register_reverse_wire_map(y_id, cell->getPort("\\Y"));
788
789 continue;
790 }
791
792 if (cell->type.in("$mux"))
793 {
794 int width = cell->parameters.at("\\WIDTH").as_int();
795 string a_expr = make_expr(cell->getPort("\\A"));
796 string b_expr = make_expr(cell->getPort("\\B"));
797 string s_expr = make_expr(cell->getPort("\\S"));
798 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), width));
799
800 string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
801
802 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
803 register_reverse_wire_map(y_id, cell->getPort("\\Y"));
804
805 continue;
806 }
807
808 if (cell->type.in("$mem"))
809 {
810 string mem_id = make_id(cell->name);
811 int abits = cell->parameters.at("\\ABITS").as_int();
812 int width = cell->parameters.at("\\WIDTH").as_int();
813 int size = cell->parameters.at("\\SIZE").as_int();
814 memory m(cell, mem_id, abits, size, width);
815 int rd_ports = cell->parameters.at("\\RD_PORTS").as_int();
816 int wr_ports = cell->parameters.at("\\WR_PORTS").as_int();
817
818 Const initdata = cell->parameters.at("\\INIT");
819 for (State bit : initdata.bits)
820 if (bit != State::Sx)
821 log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell));
822
823 Const rd_clk_enable = cell->parameters.at("\\RD_CLK_ENABLE");
824 Const wr_clk_enable = cell->parameters.at("\\WR_CLK_ENABLE");
825 Const wr_clk_polarity = cell->parameters.at("\\WR_CLK_POLARITY");
826
827 int offset = cell->parameters.at("\\OFFSET").as_int();
828 if (offset != 0)
829 log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
830
831 for (int i = 0; i < rd_ports; i++)
832 {
833 if (rd_clk_enable[i] != State::S0)
834 log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
835
836 SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(i*abits, abits);
837 SigSpec data_sig = cell->getPort("\\RD_DATA").extract(i*width, width);
838 string addr_expr = make_expr(addr_sig);
839 string name(stringf("%s.r%d", m.name.c_str(), i));
840 bool clk_enable = false;
841 bool clk_parity = true;
842 bool transparency = false;
843 SigSpec ena_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
844 SigSpec clk_sig = RTLIL::SigSpec(RTLIL::State::S0, 1);
845 read_port rp(name, clk_enable, clk_parity, transparency, clk_sig, ena_sig, addr_sig);
846 m.add_memory_read_port(rp);
847 cell_exprs.push_back(rp.gen_read(indent.c_str()));
848 register_reverse_wire_map(stringf("%s.data", name.c_str()), data_sig);
849 }
850
851 for (int i = 0; i < wr_ports; i++)
852 {
853 if (wr_clk_enable[i] != State::S1)
854 log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
855
856 if (wr_clk_polarity[i] != State::S1)
857 log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
858
859 string name(stringf("%s.w%d", m.name.c_str(), i));
860 bool clk_enable = true;
861 bool clk_parity = true;
862 bool transparency = false;
863 SigSpec addr_sig =cell->getPort("\\WR_ADDR").extract(i*abits, abits);
864 string addr_expr = make_expr(addr_sig);
865 SigSpec data_sig =cell->getPort("\\WR_DATA").extract(i*width, width);
866 string data_expr = make_expr(data_sig);
867 SigSpec clk_sig = cell->getPort("\\WR_CLK").extract(i);
868 string clk_expr = make_expr(clk_sig);
869
870 SigSpec wen_sig = cell->getPort("\\WR_EN").extract(i*width, width);
871 string wen_expr = make_expr(wen_sig[0]);
872
873 for (int i = 1; i < GetSize(wen_sig); i++)
874 if (wen_sig[0] != wen_sig[i])
875 log_error("Complex write enable on port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
876
877 SigSpec mask_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
878 write_port wp(name, clk_enable, clk_parity, transparency, clk_sig, wen_sig[0], addr_sig, mask_sig);
879 m.add_memory_write_port(wp);
880 cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), name.c_str(), data_expr.c_str()));
881 cell_exprs.push_back(wp.gen_write(indent.c_str()));
882 }
883 register_memory(m);
884 continue;
885 }
886
887 if (cell->type.in("$memwr", "$memrd", "$meminit"))
888 {
889 std::string cell_type = fid(cell->type);
890 std::string mem_id = make_id(cell->parameters["\\MEMID"].decode_string());
891 int abits = cell->parameters.at("\\ABITS").as_int();
892 int width = cell->parameters.at("\\WIDTH").as_int();
893 memory *mp = nullptr;
894 if (cell->type == "$meminit" ) {
895 log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
896 } else {
897 // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
898 auto addrSig = cell->getPort("\\ADDR");
899 auto dataSig = cell->getPort("\\DATA");
900 auto enableSig = cell->getPort("\\EN");
901 auto clockSig = cell->getPort("\\CLK");
902 Const clk_enable = cell->parameters.at("\\CLK_ENABLE");
903 Const clk_polarity = cell->parameters.at("\\CLK_POLARITY");
904
905 // Do we already have an entry for this memory?
906 if (memories.count(mem_id) == 0) {
907 memory m(cell, mem_id, abits, 0, width);
908 register_memory(m);
909 }
910 mp = &memories.at(mem_id);
911 int portNum = 0;
912 bool transparency = false;
913 string data_expr = make_expr(dataSig);
914 if (cell->type.in("$memwr")) {
915 portNum = (int) mp->write_ports.size();
916 write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
917 mp->add_memory_write_port(wp);
918 cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
919 cell_exprs.push_back(wp.gen_write(indent.c_str()));
920 } else if (cell->type.in("$memrd")) {
921 portNum = (int) mp->read_ports.size();
922 read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
923 mp->add_memory_read_port(rp);
924 cell_exprs.push_back(rp.gen_read(indent.c_str()));
925 register_reverse_wire_map(stringf("%s.data", rp.name.c_str()), dataSig);
926 }
927 }
928 continue;
929 }
930
931 if (cell->type.in("$dff"))
932 {
933 bool clkpol = cell->parameters.at("\\CLK_POLARITY").as_bool();
934 if (clkpol == false)
935 log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell));
936
937 int width = cell->parameters.at("\\WIDTH").as_int();
938 string expr = make_expr(cell->getPort("\\D"));
939 string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")";
940
941 wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str()));
942
943 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
944 register_reverse_wire_map(y_id, cell->getPort("\\Q"));
945
946 continue;
947 }
948
949 // This may be a parameterized module - paramod.
950 if (cell->type.begins_with("$paramod"))
951 {
952 process_instance(cell, wire_exprs);
953 continue;
954 }
955 if (cell->type == "$shiftx") {
956 // assign y = a[b +: y_width];
957 // We'll extract the correct bits as part of the primop.
958
959 string a_expr = make_expr(cell->getPort("\\A"));
960 // Get the initial bit selector
961 string b_expr = make_expr(cell->getPort("\\B"));
962 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
963
964 if (cell->getParam("\\B_SIGNED").as_bool()) {
965 // Use validif to constrain the selection (test the sign bit)
966 auto b_string = b_expr.c_str();
967 int b_sign = cell->parameters.at("\\B_WIDTH").as_int() - 1;
968 b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string);
969 }
970 string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
971
972 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
973 register_reverse_wire_map(y_id, cell->getPort("\\Y"));
974 continue;
975 }
976 if (cell->type == "$shift") {
977 // assign y = a >> b;
978 // where b may be negative
979
980 string a_expr = make_expr(cell->getPort("\\A"));
981 string b_expr = make_expr(cell->getPort("\\B"));
982 auto b_string = b_expr.c_str();
983 string expr;
984 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
985
986 if (cell->getParam("\\B_SIGNED").as_bool()) {
987 // We generate a left or right shift based on the sign of b.
988 std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width);
989 std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
990 expr = stringf("mux(%s < 0, %s, %s)",
991 b_string,
992 dshl.c_str(),
993 dshr.c_str()
994 );
995 } else {
996 expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
997 }
998 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
999 register_reverse_wire_map(y_id, cell->getPort("\\Y"));
1000 continue;
1001 }
1002 if (cell->type == "$pos") {
1003 // assign y = a;
1004 // printCell(cell);
1005 string a_expr = make_expr(cell->getPort("\\A"));
1006 // Verilog appears to treat the result as signed, so if the result is wider than "A",
1007 // we need to pad.
1008 if (a_width < y_width) {
1009 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
1010 }
1011 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
1012 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), a_expr.c_str()));
1013 register_reverse_wire_map(y_id, cell->getPort("\\Y"));
1014 continue;
1015 }
1016 log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
1017 }
1018
1019 for (auto conn : module->connections())
1020 {
1021 string y_id = next_id();
1022 int y_width = GetSize(conn.first);
1023 string expr = make_expr(conn.second);
1024
1025 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
1026 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
1027 register_reverse_wire_map(y_id, conn.first);
1028 }
1029
1030 for (auto wire : module->wires())
1031 {
1032 string expr;
1033
1034 if (wire->port_input)
1035 continue;
1036
1037 int cursor = 0;
1038 bool is_valid = false;
1039 bool make_unconn_id = false;
1040
1041 while (cursor < wire->width)
1042 {
1043 int chunk_width = 1;
1044 string new_expr;
1045
1046 SigBit start_bit(wire, cursor);
1047
1048 if (reverse_wire_map.count(start_bit))
1049 {
1050 pair<string, int> start_map = reverse_wire_map.at(start_bit);
1051
1052 while (cursor+chunk_width < wire->width)
1053 {
1054 SigBit stop_bit(wire, cursor+chunk_width);
1055
1056 if (reverse_wire_map.count(stop_bit) == 0)
1057 break;
1058
1059 pair<string, int> stop_map = reverse_wire_map.at(stop_bit);
1060 stop_map.second -= chunk_width;
1061
1062 if (start_map != stop_map)
1063 break;
1064
1065 chunk_width++;
1066 }
1067
1068 new_expr = stringf("bits(%s, %d, %d)", start_map.first.c_str(),
1069 start_map.second + chunk_width - 1, start_map.second);
1070 is_valid = true;
1071 }
1072 else
1073 {
1074 if (unconn_id.empty()) {
1075 unconn_id = next_id();
1076 make_unconn_id = true;
1077 }
1078 new_expr = unconn_id;
1079 }
1080
1081 if (expr.empty())
1082 expr = new_expr;
1083 else
1084 expr = "cat(" + new_expr + ", " + expr + ")";
1085
1086 cursor += chunk_width;
1087 }
1088
1089 if (is_valid) {
1090 if (make_unconn_id) {
1091 wire_decls.push_back(stringf(" wire %s: UInt<1>\n", unconn_id.c_str()));
1092 wire_decls.push_back(stringf(" %s is invalid\n", unconn_id.c_str()));
1093 }
1094 wire_exprs.push_back(stringf(" %s <= %s\n", make_id(wire->name), expr.c_str()));
1095 } else {
1096 if (make_unconn_id) {
1097 unconn_id.clear();
1098 }
1099 wire_decls.push_back(stringf(" %s is invalid\n", make_id(wire->name)));
1100 }
1101 }
1102
1103 for (auto str : port_decls)
1104 f << str;
1105
1106 f << stringf("\n");
1107
1108 for (auto str : wire_decls)
1109 f << str;
1110
1111 f << stringf("\n");
1112
1113 // If we have any memory definitions, output them.
1114 for (auto kv : memories) {
1115 memory &m = kv.second;
1116 f << stringf(" mem %s:\n", m.name.c_str());
1117 f << stringf(" data-type => UInt<%d>\n", m.width);
1118 f << stringf(" depth => %d\n", m.size);
1119 for (int i = 0; i < (int) m.read_ports.size(); i += 1) {
1120 f << stringf(" reader => r%d\n", i);
1121 }
1122 for (int i = 0; i < (int) m.write_ports.size(); i += 1) {
1123 f << stringf(" writer => w%d\n", i);
1124 }
1125 f << stringf(" read-latency => %d\n", m.read_latency);
1126 f << stringf(" write-latency => %d\n", m.write_latency);
1127 f << stringf(" read-under-write => undefined\n");
1128 }
1129 f << stringf("\n");
1130
1131 for (auto str : cell_exprs)
1132 f << str;
1133
1134 f << stringf("\n");
1135
1136 for (auto str : wire_exprs)
1137 f << str;
1138 }
1139 };
1140
1141 struct FirrtlBackend : public Backend {
1142 FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
1143 void help() YS_OVERRIDE
1144 {
1145 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1146 log("\n");
1147 log(" write_firrtl [options] [filename]\n");
1148 log("\n");
1149 log("Write a FIRRTL netlist of the current design.\n");
1150 log("The following commands are executed by this command:\n");
1151 log(" pmuxtree\n");
1152 log("\n");
1153 }
1154 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1155 {
1156 size_t argidx = args.size(); // We aren't expecting any arguments.
1157
1158 // If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
1159 if (filename == "") {
1160 if (argidx > 0 && args[argidx - 1][0] != '-') {
1161 // extra_args and friends need to see this argument.
1162 argidx -= 1;
1163 filename = args[argidx];
1164 }
1165 }
1166 extra_args(f, filename, args, argidx);
1167
1168 if (!design->full_selection())
1169 log_cmd_error("This command only operates on fully selected designs!\n");
1170
1171 log_header(design, "Executing FIRRTL backend.\n");
1172 log_push();
1173
1174 Pass::call(design, stringf("pmuxtree"));
1175
1176 namecache.clear();
1177 autoid_counter = 0;
1178
1179 // Get the top module, or a reasonable facsimile - we need something for the circuit name.
1180 Module *top = design->top_module();
1181 Module *last = nullptr;
1182 // Generate module and wire names.
1183 for (auto module : design->modules()) {
1184 make_id(module->name);
1185 last = module;
1186 if (top == nullptr && module->get_bool_attribute("\\top")) {
1187 top = module;
1188 }
1189 for (auto wire : module->wires())
1190 if (wire->port_id)
1191 make_id(wire->name);
1192 }
1193
1194 if (top == nullptr)
1195 top = last;
1196
1197 auto circuitFileinfo = getFileinfo(top->attributes);
1198 *f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo.c_str());
1199
1200 for (auto module : design->modules())
1201 {
1202 FirrtlWorker worker(module, *f, design);
1203 worker.run();
1204 }
1205
1206 namecache.clear();
1207 autoid_counter = 0;
1208 }
1209 } FirrtlBackend;
1210
1211 PRIVATE_NAMESPACE_END