2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
33 PRIVATE_NAMESPACE_BEGIN
35 pool
<string
> used_names
;
36 dict
<IdString
, string
> namecache
;
39 typedef unsigned FDirection
;
40 static const FDirection FD_NODIRECTION
= 0x0;
41 static const FDirection FD_IN
= 0x1;
42 static const FDirection FD_OUT
= 0x2;
43 static const FDirection FD_INOUT
= 0x3;
44 static const int FIRRTL_MAX_DSH_WIDTH_ERROR
= 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
46 // Get a port direction with respect to a specific module.
47 FDirection
getPortFDirection(IdString id
, Module
*module
)
49 Wire
*wire
= module
->wires_
.at(id
);
50 FDirection direction
= FD_NODIRECTION
;
51 if (wire
&& wire
->port_id
)
55 if (wire
->port_output
)
66 new_id
= stringf("_%d", autoid_counter
++);
67 if (used_names
.count(new_id
) == 0) break;
70 used_names
.insert(new_id
);
74 const char *make_id(IdString id
)
76 if (namecache
.count(id
) != 0)
77 return namecache
.at(id
).c_str();
79 string new_id
= log_id(id
);
81 for (int i
= 0; i
< GetSize(new_id
); i
++)
84 if ('a' <= ch
&& ch
<= 'z') continue;
85 if ('A' <= ch
&& ch
<= 'Z') continue;
86 if ('0' <= ch
&& ch
<= '9' && i
!= 0) continue;
87 if ('_' == ch
) continue;
91 while (used_names
.count(new_id
) != 0)
94 namecache
[id
] = new_id
;
95 used_names
.insert(new_id
);
96 return namecache
.at(id
).c_str();
104 dict
<SigBit
, pair
<string
, int>> reverse_wire_map
;
106 RTLIL::Design
*design
;
109 // Define read/write ports and memories.
110 // We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
111 // For the moment, we don't handle $readmemh or $readmemb.
112 // These will be part of a subsequent PR.
121 read_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
) : name(name
), clk_enable(clk_enable
), clk_parity(clk_parity
), transparent(transparent
), clk(clk
), ena(ena
), addr(addr
) {
122 // Current (3/13/2019) conventions:
123 // generate a constant 0 for clock and a constant 1 for enable if they are undefined.
124 if (!clk
.is_fully_def())
125 this->clk
= SigSpec(RTLIL::Const(0, 1));
126 if (!ena
.is_fully_def())
127 this->ena
= SigSpec(RTLIL::Const(1, 1));
129 string
gen_read(const char * indent
) {
130 string addr_expr
= make_expr(addr
);
131 string ena_expr
= make_expr(ena
);
132 string clk_expr
= make_expr(clk
);
133 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
134 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
135 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
136 return addr_str
+ ena_str
+ clk_str
;
139 struct write_port
: read_port
{
141 write_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
, RTLIL::SigSpec mask
) : read_port(name
, clk_enable
, clk_parity
, transparent
, clk
, ena
, addr
), mask(mask
) {
142 if (!clk
.is_fully_def())
143 this->clk
= SigSpec(RTLIL::Const(0));
144 if (!ena
.is_fully_def())
145 this->ena
= SigSpec(RTLIL::Const(0));
146 if (!mask
.is_fully_def())
147 this->ena
= SigSpec(RTLIL::Const(1));
149 string
gen_read(const char * /* indent */) {
150 log_error("gen_read called on write_port: %s\n", name
.c_str());
151 return stringf("gen_read called on write_port: %s\n", name
.c_str());
153 string
gen_write(const char * indent
) {
154 string addr_expr
= make_expr(addr
);
155 string ena_expr
= make_expr(ena
);
156 string clk_expr
= make_expr(clk
);
157 string mask_expr
= make_expr(mask
);
158 string mask_str
= stringf("%s%s.mask <= %s\n", indent
, name
.c_str(), mask_expr
.c_str());
159 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
160 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
161 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
162 return addr_str
+ ena_str
+ clk_str
+ mask_str
;
165 /* Memories defined within this module. */
167 Cell
*pCell
; // for error reporting
168 string name
; // memory name
169 int abits
; // number of address bits
170 int size
; // size (in units) of the memory
171 int width
; // size (in bits) of each element
174 vector
<read_port
> read_ports
;
175 vector
<write_port
> write_ports
;
176 std::string init_file
;
177 std::string init_file_srcFileSpec
;
179 memory(Cell
*pCell
, string name
, int abits
, int size
, int width
) : pCell(pCell
), name(name
), abits(abits
), size(size
), width(width
), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
180 // Provide defaults for abits or size if one (but not the other) is specified.
181 if (this->abits
== 0 && this->size
!= 0) {
182 this->abits
= ceil_log2(this->size
);
183 } else if (this->abits
!= 0 && this->size
== 0) {
184 this->size
= 1 << this->abits
;
186 // Sanity-check this construction.
187 if (this->name
== "") {
188 log_error("Nameless memory%s\n", this->atLine());
190 if (this->abits
== 0 && this->size
== 0) {
191 log_error("Memory %s has zero address bits and size%s\n", this->name
.c_str(), this->atLine());
193 if (this->width
== 0) {
194 log_error("Memory %s has zero width%s\n", this->name
.c_str(), this->atLine());
197 // We need a default constructor for the dict insert.
198 memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
200 const char *atLine() {
203 auto p
= pCell
->attributes
.find("\\src");
204 srcLine
= " at " + p
->second
.decode_string();
207 return srcLine
.c_str();
209 void add_memory_read_port(read_port
&rp
) {
210 read_ports
.push_back(rp
);
212 void add_memory_write_port(write_port
&wp
) {
213 write_ports
.push_back(wp
);
215 void add_memory_file(std::string init_file
, std::string init_file_srcFileSpec
) {
216 this->init_file
= init_file
;
217 this->init_file_srcFileSpec
= init_file_srcFileSpec
;
221 dict
<string
, memory
> memories
;
223 void register_memory(memory
&m
)
225 memories
[m
.name
] = m
;
228 void register_reverse_wire_map(string id
, SigSpec sig
)
230 for (int i
= 0; i
< GetSize(sig
); i
++)
231 reverse_wire_map
[sig
[i
]] = make_pair(id
, i
);
234 FirrtlWorker(Module
*module
, std::ostream
&f
, RTLIL::Design
*theDesign
) : module(module
), f(f
), design(theDesign
), indent(" ")
238 static string
make_expr(const SigSpec
&sig
)
242 for (auto chunk
: sig
.chunks())
246 if (chunk
.wire
== nullptr)
248 std::vector
<RTLIL::State
> bits
= chunk
.data
;
249 new_expr
= stringf("UInt<%d>(\"h", GetSize(bits
));
251 while (GetSize(bits
) % 4 != 0)
252 bits
.push_back(State::S0
);
254 for (int i
= GetSize(bits
)-4; i
>= 0; i
-= 4)
257 if (bits
[i
+0] == State::S1
) val
+= 1;
258 if (bits
[i
+1] == State::S1
) val
+= 2;
259 if (bits
[i
+2] == State::S1
) val
+= 4;
260 if (bits
[i
+3] == State::S1
) val
+= 8;
261 new_expr
.push_back(val
< 10 ? '0' + val
: 'a' + val
- 10);
266 else if (chunk
.offset
== 0 && chunk
.width
== chunk
.wire
->width
)
268 new_expr
= make_id(chunk
.wire
->name
);
272 string wire_id
= make_id(chunk
.wire
->name
);
273 new_expr
= stringf("bits(%s, %d, %d)", wire_id
.c_str(), chunk
.offset
+ chunk
.width
- 1, chunk
.offset
);
279 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
285 std::string
fid(RTLIL::IdString internal_id
)
287 return make_id(internal_id
);
290 std::string
cellname(RTLIL::Cell
*cell
)
292 return fid(cell
->name
).c_str();
295 void process_instance(RTLIL::Cell
*cell
, vector
<string
> &wire_exprs
)
297 std::string cell_type
= fid(cell
->type
);
298 std::string instanceOf
;
299 // If this is a parameterized module, its parent module is encoded in the cell type
300 if (cell
->type
.substr(0, 8) == "$paramod")
302 std::string::iterator it
;
303 for (it
= cell_type
.begin(); it
< cell_type
.end(); it
++)
306 case '\\': /* FALL_THROUGH */
307 case '=': /* FALL_THROUGH */
308 case '\'': /* FALL_THROUGH */
309 case '$': instanceOf
.append("_"); break;
310 default: instanceOf
.append(1, *it
); break;
316 instanceOf
= cell_type
;
319 std::string cell_name
= cellname(cell
);
320 std::string cell_name_comment
;
321 if (cell_name
!= fid(cell
->name
))
322 cell_name_comment
= " /* " + fid(cell
->name
) + " */ ";
324 cell_name_comment
= "";
325 // Find the module corresponding to this instance.
326 auto instModule
= design
->module(cell
->type
);
327 // If there is no instance for this, just return.
328 if (instModule
== NULL
)
330 log_warning("No instance for %s.%s\n", cell_type
.c_str(), cell_name
.c_str());
333 wire_exprs
.push_back(stringf("%s" "inst %s%s of %s", indent
.c_str(), cell_name
.c_str(), cell_name_comment
.c_str(), instanceOf
.c_str()));
335 for (auto it
= cell
->connections().begin(); it
!= cell
->connections().end(); ++it
) {
336 if (it
->second
.size() > 0) {
337 const SigSpec
&secondSig
= it
->second
;
338 const std::string firstName
= cell_name
+ "." + make_id(it
->first
);
339 const std::string secondExpr
= make_expr(secondSig
);
340 // Find the direction for this port.
341 FDirection dir
= getPortFDirection(it
->first
, instModule
);
342 std::string sourceExpr
, sinkExpr
;
343 const SigSpec
*sinkSig
= nullptr;
346 log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type
.c_str(), log_signal(it
->second
));
349 sourceExpr
= firstName
;
350 sinkExpr
= secondExpr
;
351 sinkSig
= &secondSig
;
354 log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type
.c_str(), log_signal(it
->second
));
357 sourceExpr
= secondExpr
;
358 sinkExpr
= firstName
;
361 log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type
.c_str(), log_signal(it
->second
), dir
);
364 // Check for subfield assignment.
365 std::string bitsString
= "bits(";
366 if (sinkExpr
.substr(0, bitsString
.length()) == bitsString
) {
367 if (sinkSig
== nullptr)
368 log_error("Unknown subfield %s.%s\n", cell_type
.c_str(), sinkExpr
.c_str());
369 // Don't generate the assignment here.
370 // Add the source and sink to the "reverse_wire_map" and we'll output the assignment
371 // as part of the coalesced subfield assignments for this wire.
372 register_reverse_wire_map(sourceExpr
, *sinkSig
);
374 wire_exprs
.push_back(stringf("\n%s%s <= %s", indent
.c_str(), sinkExpr
.c_str(), sourceExpr
.c_str()));
378 wire_exprs
.push_back(stringf("\n"));
382 // Given an expression for a shift amount, and a maximum width,
383 // generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
384 std::string
gen_dshl(const string b_expr
, const int b_padded_width
)
386 string result
= b_expr
;
387 if (b_padded_width
>= FIRRTL_MAX_DSH_WIDTH_ERROR
) {
388 int max_shift_width_bits
= FIRRTL_MAX_DSH_WIDTH_ERROR
- 1;
389 string max_shift_string
= stringf("UInt<%d>(%d)", max_shift_width_bits
, (1<<max_shift_width_bits
) - 1);
390 // Deal with the difference in semantics between FIRRTL and verilog
391 result
= stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr
.c_str(), max_shift_string
.c_str(), max_shift_string
.c_str(), b_expr
.c_str(), max_shift_width_bits
- 1);
398 f
<< stringf(" module %s:\n", make_id(module
->name
));
399 vector
<string
> port_decls
, wire_decls
, cell_exprs
, wire_exprs
;
401 for (auto wire
: module
->wires())
403 const auto wireName
= make_id(wire
->name
);
404 // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
405 if (wire
->attributes
.count("\\init")) {
406 log_warning("Initial value (%s) for (%s.%s) not supported\n",
407 wire
->attributes
.at("\\init").as_string().c_str(),
408 log_id(module
), log_id(wire
));
412 if (wire
->port_input
&& wire
->port_output
)
413 log_error("Module port %s.%s is inout!\n", log_id(module
), log_id(wire
));
414 port_decls
.push_back(stringf(" %s %s: UInt<%d>\n", wire
->port_input
? "input" : "output",
415 wireName
, wire
->width
));
419 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", wireName
, wire
->width
));
423 for (auto cell
: module
->cells())
425 bool extract_y_bits
= false; // Assume no extraction of final bits will be required.
426 // Is this cell is a module instance?
427 if (cell
->type
[0] != '$')
429 process_instance(cell
, wire_exprs
);
432 if (cell
->type
.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
434 string y_id
= make_id(cell
->name
);
435 bool is_signed
= cell
->parameters
.at("\\A_SIGNED").as_bool();
436 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
437 string a_expr
= make_expr(cell
->getPort("\\A"));
438 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
440 if (cell
->parameters
.at("\\A_SIGNED").as_bool()) {
441 a_expr
= "asSInt(" + a_expr
+ ")";
444 // Don't use the results of logical operations (a single bit) to control padding
445 if (!(cell
->type
.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width
== 1) ) {
446 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
450 bool always_uint
= false;
451 if (cell
->type
== "$not") primop
= "not";
452 else if (cell
->type
== "$neg") primop
= "neg";
453 else if (cell
->type
== "$logic_not") {
455 a_expr
= stringf("%s, UInt(0)", a_expr
.c_str());
457 else if (cell
->type
== "$reduce_and") primop
= "andr";
458 else if (cell
->type
== "$reduce_or") primop
= "orr";
459 else if (cell
->type
== "$reduce_xor") primop
= "xorr";
460 else if (cell
->type
== "$reduce_xnor") {
462 a_expr
= stringf("xorr(%s)", a_expr
.c_str());
464 else if (cell
->type
== "$reduce_bool") {
466 // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
467 bool a_signed
= cell
->parameters
.at("\\A_SIGNED").as_bool();
468 int a_width
= cell
->parameters
.at("\\A_WIDTH").as_int();
469 a_expr
= stringf("%s, %cInt<%d>(0)", a_expr
.c_str(), a_signed
? 'S' : 'U', a_width
);
472 string expr
= stringf("%s(%s)", primop
.c_str(), a_expr
.c_str());
474 if ((is_signed
&& !always_uint
))
475 expr
= stringf("asUInt(%s)", expr
.c_str());
477 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
478 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
482 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$and", "$or", "$eq", "$eqx",
483 "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
484 "$logic_and", "$logic_or"))
486 string y_id
= make_id(cell
->name
);
487 bool is_signed
= cell
->parameters
.at("\\A_SIGNED").as_bool();
488 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
489 string a_expr
= make_expr(cell
->getPort("\\A"));
490 string b_expr
= make_expr(cell
->getPort("\\B"));
491 int b_padded_width
= cell
->parameters
.at("\\B_WIDTH").as_int();
492 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
494 if (cell
->parameters
.at("\\A_SIGNED").as_bool()) {
495 a_expr
= "asSInt(" + a_expr
+ ")";
497 // Shift amount is always unsigned, and needn't be padded to result width.
498 if (!cell
->type
.in("$shr", "$sshr", "$shl", "$sshl")) {
499 if (cell
->parameters
.at("\\B_SIGNED").as_bool()) {
500 b_expr
= "asSInt(" + b_expr
+ ")";
502 if (b_padded_width
< y_width
) {
503 auto b_sig
= cell
->getPort("\\B");
504 b_padded_width
= y_width
;
508 auto a_sig
= cell
->getPort("\\A");
510 if (cell
->parameters
.at("\\A_SIGNED").as_bool() & (cell
->type
== "$shr")) {
511 a_expr
= "asUInt(" + a_expr
+ ")";
515 bool always_uint
= false;
516 if (cell
->type
== "$add") primop
= "add";
517 else if (cell
->type
== "$sub") primop
= "sub";
518 else if (cell
->type
== "$mul") primop
= "mul";
519 else if (cell
->type
== "$div") primop
= "div";
520 else if (cell
->type
== "$mod") primop
= "rem";
521 else if (cell
->type
== "$and") {
525 else if (cell
->type
== "$or" ) {
529 else if (cell
->type
== "$xor") {
533 else if ((cell
->type
== "$eq") | (cell
->type
== "$eqx")) {
537 else if ((cell
->type
== "$ne") | (cell
->type
== "$nex")) {
541 else if (cell
->type
== "$gt") {
545 else if (cell
->type
== "$ge") {
549 else if (cell
->type
== "$lt") {
553 else if (cell
->type
== "$le") {
557 else if ((cell
->type
== "$shl") | (cell
->type
== "$sshl")) {
558 // FIRRTL will widen the result (y) by the amount of the shift.
559 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
560 extract_y_bits
= true;
561 // Is the shift amount constant?
562 auto b_sig
= cell
->getPort("\\B");
563 if (b_sig
.is_fully_const()) {
567 // Convert from FIRRTL left shift semantics.
568 b_expr
= gen_dshl(b_expr
, b_padded_width
);
571 else if ((cell
->type
== "$shr") | (cell
->type
== "$sshr")) {
572 // We don't need to extract a specific range of bits.
573 extract_y_bits
= false;
574 // Is the shift amount constant?
575 auto b_sig
= cell
->getPort("\\B");
576 if (b_sig
.is_fully_const()) {
582 else if ((cell
->type
== "$logic_and")) {
584 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
585 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
588 else if ((cell
->type
== "$logic_or")) {
590 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
591 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
595 if (!cell
->parameters
.at("\\B_SIGNED").as_bool()) {
596 b_expr
= "asUInt(" + b_expr
+ ")";
599 string expr
= stringf("%s(%s, %s)", primop
.c_str(), a_expr
.c_str(), b_expr
.c_str());
601 // Deal with FIRRTL's "shift widens" semantics
602 if (extract_y_bits
) {
603 expr
= stringf("bits(%s, %d, 0)", expr
.c_str(), y_width
- 1);
606 if ((is_signed
&& !always_uint
) || cell
->type
.in("$sub"))
607 expr
= stringf("asUInt(%s)", expr
.c_str());
609 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
610 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
615 if (cell
->type
.in("$mux"))
617 string y_id
= make_id(cell
->name
);
618 int width
= cell
->parameters
.at("\\WIDTH").as_int();
619 string a_expr
= make_expr(cell
->getPort("\\A"));
620 string b_expr
= make_expr(cell
->getPort("\\B"));
621 string s_expr
= make_expr(cell
->getPort("\\S"));
622 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), width
));
624 string expr
= stringf("mux(%s, %s, %s)", s_expr
.c_str(), b_expr
.c_str(), a_expr
.c_str());
626 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
627 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
632 if (cell
->type
.in("$mem"))
634 string mem_id
= make_id(cell
->name
);
635 int abits
= cell
->parameters
.at("\\ABITS").as_int();
636 int width
= cell
->parameters
.at("\\WIDTH").as_int();
637 int size
= cell
->parameters
.at("\\SIZE").as_int();
638 memory
m(cell
, mem_id
, abits
, size
, width
);
639 int rd_ports
= cell
->parameters
.at("\\RD_PORTS").as_int();
640 int wr_ports
= cell
->parameters
.at("\\WR_PORTS").as_int();
642 Const initdata
= cell
->parameters
.at("\\INIT");
643 for (State bit
: initdata
.bits
)
644 if (bit
!= State::Sx
)
645 log_error("Memory with initialization data: %s.%s\n", log_id(module
), log_id(cell
));
647 Const rd_clk_enable
= cell
->parameters
.at("\\RD_CLK_ENABLE");
648 Const wr_clk_enable
= cell
->parameters
.at("\\WR_CLK_ENABLE");
649 Const wr_clk_polarity
= cell
->parameters
.at("\\WR_CLK_POLARITY");
651 int offset
= cell
->parameters
.at("\\OFFSET").as_int();
653 log_error("Memory with nonzero offset: %s.%s\n", log_id(module
), log_id(cell
));
655 for (int i
= 0; i
< rd_ports
; i
++)
657 if (rd_clk_enable
[i
] != State::S0
)
658 log_error("Clocked read port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
660 SigSpec addr_sig
= cell
->getPort("\\RD_ADDR").extract(i
*abits
, abits
);
661 SigSpec data_sig
= cell
->getPort("\\RD_DATA").extract(i
*width
, width
);
662 string addr_expr
= make_expr(addr_sig
);
663 string
name(stringf("%s.r%d", m
.name
.c_str(), i
));
664 bool clk_enable
= false;
665 bool clk_parity
= true;
666 bool transparency
= false;
667 SigSpec ena_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
668 SigSpec clk_sig
= RTLIL::SigSpec(RTLIL::State::S0
, 1);
669 read_port
rp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, ena_sig
, addr_sig
);
670 m
.add_memory_read_port(rp
);
671 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
672 register_reverse_wire_map(stringf("%s.data", name
.c_str()), data_sig
);
675 for (int i
= 0; i
< wr_ports
; i
++)
677 if (wr_clk_enable
[i
] != State::S1
)
678 log_error("Unclocked write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
680 if (wr_clk_polarity
[i
] != State::S1
)
681 log_error("Negedge write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
683 string
name(stringf("%s.w%d", m
.name
.c_str(), i
));
684 bool clk_enable
= true;
685 bool clk_parity
= true;
686 bool transparency
= false;
687 SigSpec addr_sig
=cell
->getPort("\\WR_ADDR").extract(i
*abits
, abits
);
688 string addr_expr
= make_expr(addr_sig
);
689 SigSpec data_sig
=cell
->getPort("\\WR_DATA").extract(i
*width
, width
);
690 string data_expr
= make_expr(data_sig
);
691 SigSpec clk_sig
= cell
->getPort("\\WR_CLK").extract(i
);
692 string clk_expr
= make_expr(clk_sig
);
694 SigSpec wen_sig
= cell
->getPort("\\WR_EN").extract(i
*width
, width
);
695 string wen_expr
= make_expr(wen_sig
[0]);
697 for (int i
= 1; i
< GetSize(wen_sig
); i
++)
698 if (wen_sig
[0] != wen_sig
[i
])
699 log_error("Complex write enable on port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
701 SigSpec mask_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
702 write_port
wp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, wen_sig
[0], addr_sig
, mask_sig
);
703 m
.add_memory_write_port(wp
);
704 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), name
.c_str(), data_expr
.c_str()));
705 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
711 if (cell
->type
.in("$memwr", "$memrd", "$meminit"))
713 std::string cell_type
= fid(cell
->type
);
714 std::string mem_id
= make_id(cell
->parameters
["\\MEMID"].decode_string());
715 int abits
= cell
->parameters
.at("\\ABITS").as_int();
716 int width
= cell
->parameters
.at("\\WIDTH").as_int();
717 memory
*mp
= nullptr;
718 if (cell
->type
== "$meminit" ) {
719 log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module
), log_id(cell
), mem_id
.c_str());
721 // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
722 auto addrSig
= cell
->getPort("\\ADDR");
723 auto dataSig
= cell
->getPort("\\DATA");
724 auto enableSig
= cell
->getPort("\\EN");
725 auto clockSig
= cell
->getPort("\\CLK");
726 Const clk_enable
= cell
->parameters
.at("\\CLK_ENABLE");
727 Const clk_polarity
= cell
->parameters
.at("\\CLK_POLARITY");
729 // Do we already have an entry for this memory?
730 if (memories
.count(mem_id
) == 0) {
731 memory
m(cell
, mem_id
, abits
, 0, width
);
734 mp
= &memories
.at(mem_id
);
736 bool transparency
= false;
737 string data_expr
= make_expr(dataSig
);
738 if (cell
->type
.in("$memwr")) {
739 portNum
= (int) mp
->write_ports
.size();
740 write_port
wp(stringf("%s.w%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
, dataSig
);
741 mp
->add_memory_write_port(wp
);
742 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), wp
.name
.c_str(), data_expr
.c_str()));
743 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
744 } else if (cell
->type
.in("$memrd")) {
745 portNum
= (int) mp
->read_ports
.size();
746 read_port
rp(stringf("%s.r%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
);
747 mp
->add_memory_read_port(rp
);
748 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
749 register_reverse_wire_map(stringf("%s.data", rp
.name
.c_str()), dataSig
);
755 if (cell
->type
.in("$dff"))
757 bool clkpol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool();
759 log_error("Negative edge clock on FF %s.%s.\n", log_id(module
), log_id(cell
));
761 string q_id
= make_id(cell
->name
);
762 int width
= cell
->parameters
.at("\\WIDTH").as_int();
763 string expr
= make_expr(cell
->getPort("\\D"));
764 string clk_expr
= "asClock(" + make_expr(cell
->getPort("\\CLK")) + ")";
766 wire_decls
.push_back(stringf(" reg %s: UInt<%d>, %s\n", q_id
.c_str(), width
, clk_expr
.c_str()));
768 cell_exprs
.push_back(stringf(" %s <= %s\n", q_id
.c_str(), expr
.c_str()));
769 register_reverse_wire_map(q_id
, cell
->getPort("\\Q"));
774 // This may be a parameterized module - paramod.
775 if (cell
->type
.substr(0, 8) == "$paramod")
777 process_instance(cell
, wire_exprs
);
780 if (cell
->type
== "$shiftx") {
781 // assign y = a[b +: y_width];
782 // We'll extract the correct bits as part of the primop.
784 string y_id
= make_id(cell
->name
);
785 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
786 string a_expr
= make_expr(cell
->getPort("\\A"));
787 // Get the initial bit selector
788 string b_expr
= make_expr(cell
->getPort("\\B"));
789 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
791 if (cell
->getParam("\\B_SIGNED").as_bool()) {
792 // Use validif to constrain the selection (test the sign bit)
793 auto b_string
= b_expr
.c_str();
794 int b_sign
= cell
->parameters
.at("\\B_WIDTH").as_int() - 1;
795 b_expr
= stringf("validif(not(bits(%s, %d, %d)), %s)", b_string
, b_sign
, b_sign
, b_string
);
797 string expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_expr
.c_str());
799 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
800 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
803 if (cell
->type
== "$shift") {
804 // assign y = a >> b;
805 // where b may be negative
807 string y_id
= make_id(cell
->name
);
808 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
809 string a_expr
= make_expr(cell
->getPort("\\A"));
810 string b_expr
= make_expr(cell
->getPort("\\B"));
811 auto b_string
= b_expr
.c_str();
812 int b_padded_width
= cell
->parameters
.at("\\B_WIDTH").as_int();
814 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
816 if (cell
->getParam("\\B_SIGNED").as_bool()) {
817 // We generate a left or right shift based on the sign of b.
818 std::string dshl
= stringf("bits(dshl(%s, %s), 0, %d)", a_expr
.c_str(), gen_dshl(b_expr
, b_padded_width
).c_str(), y_width
);
819 std::string dshr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
820 expr
= stringf("mux(%s < 0, %s, %s)",
826 expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
828 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
829 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
832 log_warning("Cell type not supported: %s (%s.%s)\n", log_id(cell
->type
), log_id(module
), log_id(cell
));
835 for (auto conn
: module
->connections())
837 string y_id
= next_id();
838 int y_width
= GetSize(conn
.first
);
839 string expr
= make_expr(conn
.second
);
841 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
842 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
843 register_reverse_wire_map(y_id
, conn
.first
);
846 for (auto wire
: module
->wires())
850 if (wire
->port_input
)
854 bool is_valid
= false;
855 bool make_unconn_id
= false;
857 while (cursor
< wire
->width
)
862 SigBit
start_bit(wire
, cursor
);
864 if (reverse_wire_map
.count(start_bit
))
866 pair
<string
, int> start_map
= reverse_wire_map
.at(start_bit
);
868 while (cursor
+chunk_width
< wire
->width
)
870 SigBit
stop_bit(wire
, cursor
+chunk_width
);
872 if (reverse_wire_map
.count(stop_bit
) == 0)
875 pair
<string
, int> stop_map
= reverse_wire_map
.at(stop_bit
);
876 stop_map
.second
-= chunk_width
;
878 if (start_map
!= stop_map
)
884 new_expr
= stringf("bits(%s, %d, %d)", start_map
.first
.c_str(),
885 start_map
.second
+ chunk_width
- 1, start_map
.second
);
890 if (unconn_id
.empty()) {
891 unconn_id
= next_id();
892 make_unconn_id
= true;
894 new_expr
= unconn_id
;
900 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
902 cursor
+= chunk_width
;
906 if (make_unconn_id
) {
907 wire_decls
.push_back(stringf(" wire %s: UInt<1>\n", unconn_id
.c_str()));
908 wire_decls
.push_back(stringf(" %s is invalid\n", unconn_id
.c_str()));
910 wire_exprs
.push_back(stringf(" %s <= %s\n", make_id(wire
->name
), expr
.c_str()));
912 if (make_unconn_id
) {
915 wire_decls
.push_back(stringf(" %s is invalid\n", make_id(wire
->name
)));
919 for (auto str
: port_decls
)
924 for (auto str
: wire_decls
)
929 // If we have any memory definitions, output them.
930 for (auto kv
: memories
) {
931 memory
&m
= kv
.second
;
932 f
<< stringf(" mem %s:\n", m
.name
.c_str());
933 f
<< stringf(" data-type => UInt<%d>\n", m
.width
);
934 f
<< stringf(" depth => %d\n", m
.size
);
935 for (int i
= 0; i
< (int) m
.read_ports
.size(); i
+= 1) {
936 f
<< stringf(" reader => r%d\n", i
);
938 for (int i
= 0; i
< (int) m
.write_ports
.size(); i
+= 1) {
939 f
<< stringf(" writer => w%d\n", i
);
941 f
<< stringf(" read-latency => %d\n", m
.read_latency
);
942 f
<< stringf(" write-latency => %d\n", m
.write_latency
);
943 f
<< stringf(" read-under-write => undefined\n");
947 for (auto str
: cell_exprs
)
952 for (auto str
: wire_exprs
)
957 struct FirrtlBackend
: public Backend
{
958 FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
959 void help() YS_OVERRIDE
961 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
963 log(" write_firrtl [options] [filename]\n");
965 log("Write a FIRRTL netlist of the current design.\n");
966 log("The following commands are executed by this command:\n");
970 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
972 size_t argidx
= args
.size(); // We aren't expecting any arguments.
974 // If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
975 if (filename
== "") {
976 if (argidx
> 0 && args
[argidx
- 1][0] != '-') {
977 // extra_args and friends need to see this argument.
979 filename
= args
[argidx
];
982 extra_args(f
, filename
, args
, argidx
);
984 if (!design
->full_selection())
985 log_cmd_error("This command only operates on fully selected designs!\n");
987 log_header(design
, "Executing FIRRTL backend.\n");
990 Pass::call(design
, stringf("pmuxtree"));
995 // Get the top module, or a reasonable facsimile - we need something for the circuit name.
996 Module
*top
= design
->top_module();
997 Module
*last
= nullptr;
998 // Generate module and wire names.
999 for (auto module
: design
->modules()) {
1000 make_id(module
->name
);
1002 if (top
== nullptr && module
->get_bool_attribute("\\top")) {
1005 for (auto wire
: module
->wires())
1007 make_id(wire
->name
);
1013 *f
<< stringf("circuit %s:\n", make_id(top
->name
));
1015 for (auto module
: design
->modules())
1017 FirrtlWorker
worker(module
, *f
, design
);
1026 PRIVATE_NAMESPACE_END