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Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
[yosys.git] / backends / firrtl / firrtl.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
26 #include "backends/ilang/ilang_backend.h"
27 #include <algorithm>
28 #include <string>
29 #include <vector>
30 #include <cmath>
31
32 USING_YOSYS_NAMESPACE
33 PRIVATE_NAMESPACE_BEGIN
34
35 pool<string> used_names;
36 dict<IdString, string> namecache;
37 int autoid_counter;
38
39 typedef unsigned FDirection;
40 static const FDirection FD_NODIRECTION = 0x0;
41 static const FDirection FD_IN = 0x1;
42 static const FDirection FD_OUT = 0x2;
43 static const FDirection FD_INOUT = 0x3;
44 static const int FIRRTL_MAX_DSH_WIDTH_ERROR = 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
45
46 std::string getFileinfo(const RTLIL::AttrObject *design_entity)
47 {
48 std::string src(design_entity->get_src_attribute());
49 std::string fileinfo_str = src.empty() ? "" : "@[" + src + "]";
50 return fileinfo_str;
51 }
52
53 // Get a port direction with respect to a specific module.
54 FDirection getPortFDirection(IdString id, Module *module)
55 {
56 Wire *wire = module->wires_.at(id);
57 FDirection direction = FD_NODIRECTION;
58 if (wire && wire->port_id)
59 {
60 if (wire->port_input)
61 direction |= FD_IN;
62 if (wire->port_output)
63 direction |= FD_OUT;
64 }
65 return direction;
66 }
67
68 string next_id()
69 {
70 string new_id;
71
72 while (1) {
73 new_id = stringf("_%d", autoid_counter++);
74 if (used_names.count(new_id) == 0) break;
75 }
76
77 used_names.insert(new_id);
78 return new_id;
79 }
80
81 const char *make_id(IdString id)
82 {
83 if (namecache.count(id) != 0)
84 return namecache.at(id).c_str();
85
86 string new_id = log_id(id);
87
88 for (int i = 0; i < GetSize(new_id); i++)
89 {
90 char &ch = new_id[i];
91 if ('a' <= ch && ch <= 'z') continue;
92 if ('A' <= ch && ch <= 'Z') continue;
93 if ('0' <= ch && ch <= '9' && i != 0) continue;
94 if ('_' == ch) continue;
95 ch = '_';
96 }
97
98 while (used_names.count(new_id) != 0)
99 new_id += '_';
100
101 namecache[id] = new_id;
102 used_names.insert(new_id);
103 return namecache.at(id).c_str();
104 }
105
106 struct FirrtlWorker
107 {
108 Module *module;
109 std::ostream &f;
110
111 dict<SigBit, pair<string, int>> reverse_wire_map;
112 string unconn_id;
113 RTLIL::Design *design;
114 std::string indent;
115
116 // Define read/write ports and memories.
117 // We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
118 // For the moment, we don't handle $readmemh or $readmemb.
119 // These will be part of a subsequent PR.
120 struct read_port {
121 string name;
122 bool clk_enable;
123 bool clk_parity;
124 bool transparent;
125 RTLIL::SigSpec clk;
126 RTLIL::SigSpec ena;
127 RTLIL::SigSpec addr;
128 read_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr) : name(name), clk_enable(clk_enable), clk_parity(clk_parity), transparent(transparent), clk(clk), ena(ena), addr(addr) {
129 // Current (3/13/2019) conventions:
130 // generate a constant 0 for clock and a constant 1 for enable if they are undefined.
131 if (!clk.is_fully_def())
132 this->clk = SigSpec(State::S0);
133 if (!ena.is_fully_def())
134 this->ena = SigSpec(State::S1);
135 }
136 string gen_read(const char * indent) {
137 string addr_expr = make_expr(addr);
138 string ena_expr = make_expr(ena);
139 string clk_expr = make_expr(clk);
140 string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
141 string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
142 string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
143 return addr_str + ena_str + clk_str;
144 }
145 };
146 struct write_port : read_port {
147 RTLIL::SigSpec mask;
148 write_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr, RTLIL::SigSpec mask) : read_port(name, clk_enable, clk_parity, transparent, clk, ena, addr), mask(mask) {
149 if (!clk.is_fully_def())
150 this->clk = SigSpec(RTLIL::Const(0));
151 if (!ena.is_fully_def())
152 this->ena = SigSpec(RTLIL::Const(0));
153 if (!mask.is_fully_def())
154 this->ena = SigSpec(RTLIL::Const(1));
155 }
156 string gen_read(const char * /* indent */) {
157 log_error("gen_read called on write_port: %s\n", name.c_str());
158 return stringf("gen_read called on write_port: %s\n", name.c_str());
159 }
160 string gen_write(const char * indent) {
161 string addr_expr = make_expr(addr);
162 string ena_expr = make_expr(ena);
163 string clk_expr = make_expr(clk);
164 string mask_expr = make_expr(mask);
165 string mask_str = stringf("%s%s.mask <= %s\n", indent, name.c_str(), mask_expr.c_str());
166 string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
167 string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
168 string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
169 return addr_str + ena_str + clk_str + mask_str;
170 }
171 };
172 /* Memories defined within this module. */
173 struct memory {
174 Cell *pCell; // for error reporting
175 string name; // memory name
176 int abits; // number of address bits
177 int size; // size (in units) of the memory
178 int width; // size (in bits) of each element
179 int read_latency;
180 int write_latency;
181 vector<read_port> read_ports;
182 vector<write_port> write_ports;
183 std::string init_file;
184 std::string init_file_srcFileSpec;
185 string srcLine;
186 memory(Cell *pCell, string name, int abits, int size, int width) : pCell(pCell), name(name), abits(abits), size(size), width(width), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
187 // Provide defaults for abits or size if one (but not the other) is specified.
188 if (this->abits == 0 && this->size != 0) {
189 this->abits = ceil_log2(this->size);
190 } else if (this->abits != 0 && this->size == 0) {
191 this->size = 1 << this->abits;
192 }
193 // Sanity-check this construction.
194 if (this->name == "") {
195 log_error("Nameless memory%s\n", this->atLine());
196 }
197 if (this->abits == 0 && this->size == 0) {
198 log_error("Memory %s has zero address bits and size%s\n", this->name.c_str(), this->atLine());
199 }
200 if (this->width == 0) {
201 log_error("Memory %s has zero width%s\n", this->name.c_str(), this->atLine());
202 }
203 }
204
205 // We need a default constructor for the dict insert.
206 memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
207
208 const char *atLine() {
209 if (srcLine == "") {
210 if (pCell) {
211 auto p = pCell->attributes.find(ID::src);
212 srcLine = " at " + p->second.decode_string();
213 }
214 }
215 return srcLine.c_str();
216 }
217 void add_memory_read_port(read_port &rp) {
218 read_ports.push_back(rp);
219 }
220 void add_memory_write_port(write_port &wp) {
221 write_ports.push_back(wp);
222 }
223 void add_memory_file(std::string init_file, std::string init_file_srcFileSpec) {
224 this->init_file = init_file;
225 this->init_file_srcFileSpec = init_file_srcFileSpec;
226 }
227
228 };
229 dict<string, memory> memories;
230
231 void register_memory(memory &m)
232 {
233 memories[m.name] = m;
234 }
235
236 void register_reverse_wire_map(string id, SigSpec sig)
237 {
238 for (int i = 0; i < GetSize(sig); i++)
239 reverse_wire_map[sig[i]] = make_pair(id, i);
240 }
241
242 FirrtlWorker(Module *module, std::ostream &f, RTLIL::Design *theDesign) : module(module), f(f), design(theDesign), indent(" ")
243 {
244 }
245
246 static string make_expr(const SigSpec &sig)
247 {
248 string expr;
249
250 for (auto chunk : sig.chunks())
251 {
252 string new_expr;
253
254 if (chunk.wire == nullptr)
255 {
256 std::vector<RTLIL::State> bits = chunk.data;
257 new_expr = stringf("UInt<%d>(\"h", GetSize(bits));
258
259 while (GetSize(bits) % 4 != 0)
260 bits.push_back(State::S0);
261
262 for (int i = GetSize(bits)-4; i >= 0; i -= 4)
263 {
264 int val = 0;
265 if (bits[i+0] == State::S1) val += 1;
266 if (bits[i+1] == State::S1) val += 2;
267 if (bits[i+2] == State::S1) val += 4;
268 if (bits[i+3] == State::S1) val += 8;
269 new_expr.push_back(val < 10 ? '0' + val : 'a' + val - 10);
270 }
271
272 new_expr += "\")";
273 }
274 else if (chunk.offset == 0 && chunk.width == chunk.wire->width)
275 {
276 new_expr = make_id(chunk.wire->name);
277 }
278 else
279 {
280 string wire_id = make_id(chunk.wire->name);
281 new_expr = stringf("bits(%s, %d, %d)", wire_id.c_str(), chunk.offset + chunk.width - 1, chunk.offset);
282 }
283
284 if (expr.empty())
285 expr = new_expr;
286 else
287 expr = "cat(" + new_expr + ", " + expr + ")";
288 }
289
290 return expr;
291 }
292
293 std::string fid(RTLIL::IdString internal_id)
294 {
295 return make_id(internal_id);
296 }
297
298 std::string cellname(RTLIL::Cell *cell)
299 {
300 return fid(cell->name).c_str();
301 }
302
303 void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
304 {
305 std::string cell_type = fid(cell->type);
306 std::string instanceOf;
307 // If this is a parameterized module, its parent module is encoded in the cell type
308 if (cell->type.begins_with("$paramod"))
309 {
310 std::string::iterator it;
311 for (it = cell_type.begin(); it < cell_type.end(); it++)
312 {
313 switch (*it) {
314 case '\\': /* FALL_THROUGH */
315 case '=': /* FALL_THROUGH */
316 case '\'': /* FALL_THROUGH */
317 case '$': instanceOf.append("_"); break;
318 default: instanceOf.append(1, *it); break;
319 }
320 }
321 }
322 else
323 {
324 instanceOf = cell_type;
325 }
326
327 std::string cell_name = cellname(cell);
328 std::string cell_name_comment;
329 if (cell_name != fid(cell->name))
330 cell_name_comment = " /* " + fid(cell->name) + " */ ";
331 else
332 cell_name_comment = "";
333 // Find the module corresponding to this instance.
334 auto instModule = design->module(cell->type);
335 // If there is no instance for this, just return.
336 if (instModule == NULL)
337 {
338 log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str());
339 return;
340 }
341 std::string cellFileinfo = getFileinfo(cell);
342 wire_exprs.push_back(stringf("%s" "inst %s%s of %s %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceOf.c_str(), cellFileinfo.c_str()));
343
344 for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
345 if (it->second.size() > 0) {
346 const SigSpec &secondSig = it->second;
347 const std::string firstName = cell_name + "." + make_id(it->first);
348 const std::string secondExpr = make_expr(secondSig);
349 // Find the direction for this port.
350 FDirection dir = getPortFDirection(it->first, instModule);
351 std::string sourceExpr, sinkExpr;
352 const SigSpec *sinkSig = nullptr;
353 switch (dir) {
354 case FD_INOUT:
355 log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second));
356 /* FALLTHRU */
357 case FD_OUT:
358 sourceExpr = firstName;
359 sinkExpr = secondExpr;
360 sinkSig = &secondSig;
361 break;
362 case FD_NODIRECTION:
363 log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second));
364 /* FALLTHRU */
365 case FD_IN:
366 sourceExpr = secondExpr;
367 sinkExpr = firstName;
368 break;
369 default:
370 log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
371 break;
372 }
373 // Check for subfield assignment.
374 std::string bitsString = "bits(";
375 if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) {
376 if (sinkSig == nullptr)
377 log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str());
378 // Don't generate the assignment here.
379 // Add the source and sink to the "reverse_wire_map" and we'll output the assignment
380 // as part of the coalesced subfield assignments for this wire.
381 register_reverse_wire_map(sourceExpr, *sinkSig);
382 } else {
383 wire_exprs.push_back(stringf("\n%s%s <= %s %s", indent.c_str(), sinkExpr.c_str(), sourceExpr.c_str(), cellFileinfo.c_str()));
384 }
385 }
386 }
387 wire_exprs.push_back(stringf("\n"));
388
389 }
390
391 // Given an expression for a shift amount, and a maximum width,
392 // generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
393 std::string gen_dshl(const string b_expr, const int b_width)
394 {
395 string result = b_expr;
396 if (b_width >= FIRRTL_MAX_DSH_WIDTH_ERROR) {
397 int max_shift_width_bits = FIRRTL_MAX_DSH_WIDTH_ERROR - 1;
398 string max_shift_string = stringf("UInt<%d>(%d)", max_shift_width_bits, (1<<max_shift_width_bits) - 1);
399 // Deal with the difference in semantics between FIRRTL and verilog
400 result = stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr.c_str(), max_shift_string.c_str(), max_shift_string.c_str(), b_expr.c_str(), max_shift_width_bits - 1);
401 }
402 return result;
403 }
404
405 void run()
406 {
407 std::string moduleFileinfo = getFileinfo(module);
408 f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
409 vector<string> port_decls, wire_decls, cell_exprs, wire_exprs;
410
411 for (auto wire : module->wires())
412 {
413 const auto wireName = make_id(wire->name);
414 std::string wireFileinfo = getFileinfo(wire);
415
416 // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
417 if (wire->attributes.count(ID::init)) {
418 log_warning("Initial value (%s) for (%s.%s) not supported\n",
419 wire->attributes.at(ID::init).as_string().c_str(),
420 log_id(module), log_id(wire));
421 }
422 if (wire->port_id)
423 {
424 if (wire->port_input && wire->port_output)
425 log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
426 port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
427 wireName, wire->width, wireFileinfo.c_str()));
428 }
429 else
430 {
431 wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", wireName, wire->width, wireFileinfo.c_str()));
432 }
433 }
434
435 for (auto cell : module->cells())
436 {
437 static Const ndef(0, 0);
438
439 // Is this cell is a module instance?
440 if (cell->type[0] != '$')
441 {
442 process_instance(cell, wire_exprs);
443 continue;
444 }
445 // Not a module instance. Set up cell properties
446 bool extract_y_bits = false; // Assume no extraction of final bits will be required.
447 int a_width = cell->parameters.at(ID::A_WIDTH, ndef).as_int(); // The width of "A"
448 int b_width = cell->parameters.at(ID::B_WIDTH, ndef).as_int(); // The width of "A"
449 const int y_width = cell->parameters.at(ID::Y_WIDTH, ndef).as_int(); // The width of the result
450 const bool a_signed = cell->parameters.at(ID::A_SIGNED, ndef).as_bool();
451 const bool b_signed = cell->parameters.at(ID::B_SIGNED, ndef).as_bool();
452 bool firrtl_is_signed = a_signed; // The result is signed (subsequent code may change this).
453 int firrtl_width = 0;
454 string primop;
455 bool always_uint = false;
456 string y_id = make_id(cell->name);
457 std::string cellFileinfo = getFileinfo(cell);
458
459 if (cell->type.in(ID($not), ID($logic_not), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
460 {
461 string a_expr = make_expr(cell->getPort(ID::A));
462 wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
463
464 if (a_signed) {
465 a_expr = "asSInt(" + a_expr + ")";
466 }
467
468 // Don't use the results of logical operations (a single bit) to control padding
469 if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) {
470 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
471 }
472
473 // Assume the FIRRTL width is a single bit.
474 firrtl_width = 1;
475 if (cell->type == ID($not)) primop = "not";
476 else if (cell->type == ID($neg)) {
477 primop = "neg";
478 firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
479 firrtl_width = a_width;
480 } else if (cell->type == ID($logic_not)) {
481 primop = "eq";
482 a_expr = stringf("%s, UInt(0)", a_expr.c_str());
483 }
484 else if (cell->type == ID($reduce_and)) primop = "andr";
485 else if (cell->type == ID($reduce_or)) primop = "orr";
486 else if (cell->type == ID($reduce_xor)) primop = "xorr";
487 else if (cell->type == ID($reduce_xnor)) {
488 primop = "not";
489 a_expr = stringf("xorr(%s)", a_expr.c_str());
490 }
491 else if (cell->type == ID($reduce_bool)) {
492 primop = "neq";
493 // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
494 a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
495 }
496
497 string expr = stringf("%s(%s)", primop.c_str(), a_expr.c_str());
498
499 if ((firrtl_is_signed && !always_uint))
500 expr = stringf("asUInt(%s)", expr.c_str());
501
502 cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
503 register_reverse_wire_map(y_id, cell->getPort(ID::Y));
504
505 continue;
506 }
507 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx),
508 ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
509 ID($logic_and), ID($logic_or), ID($pow)))
510 {
511 string a_expr = make_expr(cell->getPort(ID::A));
512 string b_expr = make_expr(cell->getPort(ID::B));
513 std::string cellFileinfo = getFileinfo(cell);
514 wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
515
516 if (a_signed) {
517 a_expr = "asSInt(" + a_expr + ")";
518 // Expand the "A" operand to the result width
519 if (a_width < y_width) {
520 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
521 a_width = y_width;
522 }
523 }
524 // Shift amount is always unsigned, and needn't be padded to result width,
525 // otherwise, we need to cast the b_expr appropriately
526 if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) {
527 b_expr = "asSInt(" + b_expr + ")";
528 // Expand the "B" operand to the result width
529 if (b_width < y_width) {
530 b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
531 b_width = y_width;
532 }
533 }
534
535 // For the arithmetic ops, expand operand widths to result widths befor performing the operation.
536 // This corresponds (according to iverilog) to what verilog compilers implement.
537 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or)))
538 {
539 if (a_width < y_width) {
540 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
541 a_width = y_width;
542 }
543 if (b_width < y_width) {
544 b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
545 b_width = y_width;
546 }
547 }
548 // Assume the FIRRTL width is the width of "A"
549 firrtl_width = a_width;
550 auto a_sig = cell->getPort(ID::A);
551
552 if (cell->type == ID($add)) {
553 primop = "add";
554 firrtl_is_signed = a_signed | b_signed;
555 firrtl_width = max(a_width, b_width);
556 } else if (cell->type == ID($sub)) {
557 primop = "sub";
558 firrtl_is_signed = true;
559 int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
560 int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
561 firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
562 } else if (cell->type == ID($mul)) {
563 primop = "mul";
564 firrtl_is_signed = a_signed | b_signed;
565 firrtl_width = a_width + b_width;
566 } else if (cell->type == ID($div)) {
567 primop = "div";
568 firrtl_is_signed = a_signed | b_signed;
569 firrtl_width = a_width;
570 } else if (cell->type == ID($mod)) {
571 primop = "rem";
572 firrtl_width = min(a_width, b_width);
573 } else if (cell->type == ID($and)) {
574 primop = "and";
575 always_uint = true;
576 firrtl_width = max(a_width, b_width);
577 }
578 else if (cell->type == ID($or) ) {
579 primop = "or";
580 always_uint = true;
581 firrtl_width = max(a_width, b_width);
582 }
583 else if (cell->type == ID($xor)) {
584 primop = "xor";
585 always_uint = true;
586 firrtl_width = max(a_width, b_width);
587 }
588 else if (cell->type == ID($xnor)) {
589 primop = "xnor";
590 always_uint = true;
591 firrtl_width = max(a_width, b_width);
592 }
593 else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) {
594 primop = "eq";
595 always_uint = true;
596 firrtl_width = 1;
597 }
598 else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
599 primop = "neq";
600 always_uint = true;
601 firrtl_width = 1;
602 }
603 else if (cell->type == ID($gt)) {
604 primop = "gt";
605 always_uint = true;
606 firrtl_width = 1;
607 }
608 else if (cell->type == ID($ge)) {
609 primop = "geq";
610 always_uint = true;
611 firrtl_width = 1;
612 }
613 else if (cell->type == ID($lt)) {
614 primop = "lt";
615 always_uint = true;
616 firrtl_width = 1;
617 }
618 else if (cell->type == ID($le)) {
619 primop = "leq";
620 always_uint = true;
621 firrtl_width = 1;
622 }
623 else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) {
624 // FIRRTL will widen the result (y) by the amount of the shift.
625 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
626 extract_y_bits = true;
627 // Is the shift amount constant?
628 auto b_sig = cell->getPort(ID::B);
629 if (b_sig.is_fully_const()) {
630 primop = "shl";
631 int shift_amount = b_sig.as_int();
632 b_expr = std::to_string(shift_amount);
633 firrtl_width = a_width + shift_amount;
634 } else {
635 primop = "dshl";
636 // Convert from FIRRTL left shift semantics.
637 b_expr = gen_dshl(b_expr, b_width);
638 firrtl_width = a_width + (1 << b_width) - 1;
639 }
640 }
641 else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) {
642 // We don't need to extract a specific range of bits.
643 extract_y_bits = false;
644 // Is the shift amount constant?
645 auto b_sig = cell->getPort(ID::B);
646 if (b_sig.is_fully_const()) {
647 primop = "shr";
648 int shift_amount = b_sig.as_int();
649 b_expr = std::to_string(shift_amount);
650 firrtl_width = max(1, a_width - shift_amount);
651 } else {
652 primop = "dshr";
653 firrtl_width = a_width;
654 }
655 // We'll need to do some special fixups if the source (and thus result) is signed.
656 if (firrtl_is_signed) {
657 // If this is a "logical" shift right, pretend the source is unsigned.
658 if (cell->type == ID($shr)) {
659 a_expr = "asUInt(" + a_expr + ")";
660 }
661 }
662 }
663 else if ((cell->type == ID($logic_and))) {
664 primop = "and";
665 a_expr = "neq(" + a_expr + ", UInt(0))";
666 b_expr = "neq(" + b_expr + ", UInt(0))";
667 always_uint = true;
668 firrtl_width = 1;
669 }
670 else if ((cell->type == ID($logic_or))) {
671 primop = "or";
672 a_expr = "neq(" + a_expr + ", UInt(0))";
673 b_expr = "neq(" + b_expr + ", UInt(0))";
674 always_uint = true;
675 firrtl_width = 1;
676 }
677 else if ((cell->type == ID($pow))) {
678 if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
679 // We'll convert this to a shift. To simplify things, change the a_expr to "1"
680 // so we can use b_expr directly as a shift amount.
681 // Only support 2 ** N (i.e., shift left)
682 // FIRRTL will widen the result (y) by the amount of the shift.
683 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
684 a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)";
685 extract_y_bits = true;
686 // Is the shift amount constant?
687 auto b_sig = cell->getPort(ID::B);
688 if (b_sig.is_fully_const()) {
689 primop = "shl";
690 int shiftAmount = b_sig.as_int();
691 if (shiftAmount < 0) {
692 log_error("Negative power exponent - %d: %s.%s\n", shiftAmount, log_id(module), log_id(cell));
693 }
694 b_expr = std::to_string(shiftAmount);
695 firrtl_width = a_width + shiftAmount;
696 } else {
697 primop = "dshl";
698 // Convert from FIRRTL left shift semantics.
699 b_expr = gen_dshl(b_expr, b_width);
700 firrtl_width = a_width + (1 << b_width) - 1;
701 }
702 } else {
703 log_error("Non power 2: %s.%s\n", log_id(module), log_id(cell));
704 }
705 }
706
707 if (!cell->parameters.at(ID::B_SIGNED).as_bool()) {
708 b_expr = "asUInt(" + b_expr + ")";
709 }
710
711 string expr;
712 // Deal with $xnor == ~^ (not xor)
713 if (primop == "xnor") {
714 expr = stringf("not(xor(%s, %s))", a_expr.c_str(), b_expr.c_str());
715 } else {
716 expr = stringf("%s(%s, %s)", primop.c_str(), a_expr.c_str(), b_expr.c_str());
717 }
718
719 // Deal with FIRRTL's "shift widens" semantics, or the need to widen the FIRRTL result.
720 // If the operation is signed, the FIRRTL width will be 1 one bit larger.
721 if (extract_y_bits) {
722 expr = stringf("bits(%s, %d, 0)", expr.c_str(), y_width - 1);
723 } else if (firrtl_is_signed && (firrtl_width + 1) < y_width) {
724 expr = stringf("pad(%s, %d)", expr.c_str(), y_width);
725 }
726
727 if ((firrtl_is_signed && !always_uint))
728 expr = stringf("asUInt(%s)", expr.c_str());
729
730 cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
731 register_reverse_wire_map(y_id, cell->getPort(ID::Y));
732
733 continue;
734 }
735
736 if (cell->type.in(ID($mux)))
737 {
738 int width = cell->parameters.at(ID::WIDTH).as_int();
739 string a_expr = make_expr(cell->getPort(ID::A));
740 string b_expr = make_expr(cell->getPort(ID::B));
741 string s_expr = make_expr(cell->getPort(ID::S));
742 wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), width, cellFileinfo.c_str()));
743
744 string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
745
746 cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
747 register_reverse_wire_map(y_id, cell->getPort(ID::Y));
748
749 continue;
750 }
751
752 if (cell->type.in(ID($mem)))
753 {
754 string mem_id = make_id(cell->name);
755 int abits = cell->parameters.at(ID::ABITS).as_int();
756 int width = cell->parameters.at(ID::WIDTH).as_int();
757 int size = cell->parameters.at(ID::SIZE).as_int();
758 memory m(cell, mem_id, abits, size, width);
759 int rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
760 int wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
761
762 Const initdata = cell->parameters.at(ID::INIT);
763 for (State bit : initdata.bits)
764 if (bit != State::Sx)
765 log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell));
766
767 Const rd_clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE);
768 Const wr_clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE);
769 Const wr_clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY);
770
771 int offset = cell->parameters.at(ID::OFFSET).as_int();
772 if (offset != 0)
773 log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
774
775 for (int i = 0; i < rd_ports; i++)
776 {
777 if (rd_clk_enable[i] != State::S0)
778 log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
779
780 SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
781 SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(i*width, width);
782 string addr_expr = make_expr(addr_sig);
783 string name(stringf("%s.r%d", m.name.c_str(), i));
784 bool clk_enable = false;
785 bool clk_parity = true;
786 bool transparency = false;
787 SigSpec ena_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
788 SigSpec clk_sig = RTLIL::SigSpec(RTLIL::State::S0, 1);
789 read_port rp(name, clk_enable, clk_parity, transparency, clk_sig, ena_sig, addr_sig);
790 m.add_memory_read_port(rp);
791 cell_exprs.push_back(rp.gen_read(indent.c_str()));
792 register_reverse_wire_map(stringf("%s.data", name.c_str()), data_sig);
793 }
794
795 for (int i = 0; i < wr_ports; i++)
796 {
797 if (wr_clk_enable[i] != State::S1)
798 log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
799
800 if (wr_clk_polarity[i] != State::S1)
801 log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
802
803 string name(stringf("%s.w%d", m.name.c_str(), i));
804 bool clk_enable = true;
805 bool clk_parity = true;
806 bool transparency = false;
807 SigSpec addr_sig =cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
808 string addr_expr = make_expr(addr_sig);
809 SigSpec data_sig =cell->getPort(ID::WR_DATA).extract(i*width, width);
810 string data_expr = make_expr(data_sig);
811 SigSpec clk_sig = cell->getPort(ID::WR_CLK).extract(i);
812 string clk_expr = make_expr(clk_sig);
813
814 SigSpec wen_sig = cell->getPort(ID::WR_EN).extract(i*width, width);
815 string wen_expr = make_expr(wen_sig[0]);
816
817 for (int i = 1; i < GetSize(wen_sig); i++)
818 if (wen_sig[0] != wen_sig[i])
819 log_error("Complex write enable on port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
820
821 SigSpec mask_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
822 write_port wp(name, clk_enable, clk_parity, transparency, clk_sig, wen_sig[0], addr_sig, mask_sig);
823 m.add_memory_write_port(wp);
824 cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), name.c_str(), data_expr.c_str()));
825 cell_exprs.push_back(wp.gen_write(indent.c_str()));
826 }
827 register_memory(m);
828 continue;
829 }
830
831 if (cell->type.in(ID($memwr), ID($memrd), ID($meminit)))
832 {
833 std::string cell_type = fid(cell->type);
834 std::string mem_id = make_id(cell->parameters[ID::MEMID].decode_string());
835 int abits = cell->parameters.at(ID::ABITS).as_int();
836 int width = cell->parameters.at(ID::WIDTH).as_int();
837 memory *mp = nullptr;
838 if (cell->type == ID($meminit) ) {
839 log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
840 } else {
841 // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
842 auto addrSig = cell->getPort(ID::ADDR);
843 auto dataSig = cell->getPort(ID::DATA);
844 auto enableSig = cell->getPort(ID::EN);
845 auto clockSig = cell->getPort(ID::CLK);
846 Const clk_enable = cell->parameters.at(ID::CLK_ENABLE);
847 Const clk_polarity = cell->parameters.at(ID::CLK_POLARITY);
848
849 // Do we already have an entry for this memory?
850 if (memories.count(mem_id) == 0) {
851 memory m(cell, mem_id, abits, 0, width);
852 register_memory(m);
853 }
854 mp = &memories.at(mem_id);
855 int portNum = 0;
856 bool transparency = false;
857 string data_expr = make_expr(dataSig);
858 if (cell->type.in(ID($memwr))) {
859 portNum = (int) mp->write_ports.size();
860 write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
861 mp->add_memory_write_port(wp);
862 cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
863 cell_exprs.push_back(wp.gen_write(indent.c_str()));
864 } else if (cell->type.in(ID($memrd))) {
865 portNum = (int) mp->read_ports.size();
866 read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
867 mp->add_memory_read_port(rp);
868 cell_exprs.push_back(rp.gen_read(indent.c_str()));
869 register_reverse_wire_map(stringf("%s.data", rp.name.c_str()), dataSig);
870 }
871 }
872 continue;
873 }
874
875 if (cell->type.in(ID($dff)))
876 {
877 bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool();
878 if (clkpol == false)
879 log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell));
880
881 int width = cell->parameters.at(ID::WIDTH).as_int();
882 string expr = make_expr(cell->getPort(ID::D));
883 string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
884
885 wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id.c_str(), width, clk_expr.c_str(), cellFileinfo.c_str()));
886
887 cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
888 register_reverse_wire_map(y_id, cell->getPort(ID::Q));
889
890 continue;
891 }
892
893 // This may be a parameterized module - paramod.
894 if (cell->type.begins_with("$paramod"))
895 {
896 process_instance(cell, wire_exprs);
897 continue;
898 }
899 if (cell->type == ID($shiftx)) {
900 // assign y = a[b +: y_width];
901 // We'll extract the correct bits as part of the primop.
902
903 string a_expr = make_expr(cell->getPort(ID::A));
904 // Get the initial bit selector
905 string b_expr = make_expr(cell->getPort(ID::B));
906 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
907
908 if (cell->getParam(ID::B_SIGNED).as_bool()) {
909 // Use validif to constrain the selection (test the sign bit)
910 auto b_string = b_expr.c_str();
911 int b_sign = cell->parameters.at(ID::B_WIDTH).as_int() - 1;
912 b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string);
913 }
914 string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
915
916 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
917 register_reverse_wire_map(y_id, cell->getPort(ID::Y));
918 continue;
919 }
920 if (cell->type == ID($shift)) {
921 // assign y = a >> b;
922 // where b may be negative
923
924 string a_expr = make_expr(cell->getPort(ID::A));
925 string b_expr = make_expr(cell->getPort(ID::B));
926 auto b_string = b_expr.c_str();
927 string expr;
928 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
929
930 if (cell->getParam(ID::B_SIGNED).as_bool()) {
931 // We generate a left or right shift based on the sign of b.
932 std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width);
933 std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
934 expr = stringf("mux(%s < 0, %s, %s)",
935 b_string,
936 dshl.c_str(),
937 dshr.c_str()
938 );
939 } else {
940 expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
941 }
942 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
943 register_reverse_wire_map(y_id, cell->getPort(ID::Y));
944 continue;
945 }
946 if (cell->type == ID($pos)) {
947 // assign y = a;
948 // printCell(cell);
949 string a_expr = make_expr(cell->getPort(ID::A));
950 // Verilog appears to treat the result as signed, so if the result is wider than "A",
951 // we need to pad.
952 if (a_width < y_width) {
953 a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
954 }
955 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
956 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), a_expr.c_str()));
957 register_reverse_wire_map(y_id, cell->getPort(ID::Y));
958 continue;
959 }
960 log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
961 }
962
963 for (auto conn : module->connections())
964 {
965 string y_id = next_id();
966 int y_width = GetSize(conn.first);
967 string expr = make_expr(conn.second);
968
969 wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
970 cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
971 register_reverse_wire_map(y_id, conn.first);
972 }
973
974 for (auto wire : module->wires())
975 {
976 string expr;
977 std::string wireFileinfo = getFileinfo(wire);
978
979 if (wire->port_input)
980 continue;
981
982 int cursor = 0;
983 bool is_valid = false;
984 bool make_unconn_id = false;
985
986 while (cursor < wire->width)
987 {
988 int chunk_width = 1;
989 string new_expr;
990
991 SigBit start_bit(wire, cursor);
992
993 if (reverse_wire_map.count(start_bit))
994 {
995 pair<string, int> start_map = reverse_wire_map.at(start_bit);
996
997 while (cursor+chunk_width < wire->width)
998 {
999 SigBit stop_bit(wire, cursor+chunk_width);
1000
1001 if (reverse_wire_map.count(stop_bit) == 0)
1002 break;
1003
1004 pair<string, int> stop_map = reverse_wire_map.at(stop_bit);
1005 stop_map.second -= chunk_width;
1006
1007 if (start_map != stop_map)
1008 break;
1009
1010 chunk_width++;
1011 }
1012
1013 new_expr = stringf("bits(%s, %d, %d)", start_map.first.c_str(),
1014 start_map.second + chunk_width - 1, start_map.second);
1015 is_valid = true;
1016 }
1017 else
1018 {
1019 if (unconn_id.empty()) {
1020 unconn_id = next_id();
1021 make_unconn_id = true;
1022 }
1023 new_expr = unconn_id;
1024 }
1025
1026 if (expr.empty())
1027 expr = new_expr;
1028 else
1029 expr = "cat(" + new_expr + ", " + expr + ")";
1030
1031 cursor += chunk_width;
1032 }
1033
1034 if (is_valid) {
1035 if (make_unconn_id) {
1036 wire_decls.push_back(stringf(" wire %s: UInt<1> %s\n", unconn_id.c_str(), wireFileinfo.c_str()));
1037 // `invalid` is a firrtl construction for simulation so we will not
1038 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1039 // a specific line of verilog code.
1040 wire_decls.push_back(stringf(" %s is invalid\n", unconn_id.c_str()));
1041 }
1042 wire_exprs.push_back(stringf(" %s <= %s %s\n", make_id(wire->name), expr.c_str(), wireFileinfo.c_str()));
1043 } else {
1044 if (make_unconn_id) {
1045 unconn_id.clear();
1046 }
1047 // `invalid` is a firrtl construction for simulation so we will not
1048 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1049 // a specific line of verilog code.
1050 wire_decls.push_back(stringf(" %s is invalid\n", make_id(wire->name)));
1051 }
1052 }
1053
1054 for (auto str : port_decls)
1055 f << str;
1056
1057 f << stringf("\n");
1058
1059 for (auto str : wire_decls)
1060 f << str;
1061
1062 f << stringf("\n");
1063
1064 // If we have any memory definitions, output them.
1065 for (auto kv : memories) {
1066 memory &m = kv.second;
1067 f << stringf(" mem %s:\n", m.name.c_str());
1068 f << stringf(" data-type => UInt<%d>\n", m.width);
1069 f << stringf(" depth => %d\n", m.size);
1070 for (int i = 0; i < (int) m.read_ports.size(); i += 1) {
1071 f << stringf(" reader => r%d\n", i);
1072 }
1073 for (int i = 0; i < (int) m.write_ports.size(); i += 1) {
1074 f << stringf(" writer => w%d\n", i);
1075 }
1076 f << stringf(" read-latency => %d\n", m.read_latency);
1077 f << stringf(" write-latency => %d\n", m.write_latency);
1078 f << stringf(" read-under-write => undefined\n");
1079 }
1080 f << stringf("\n");
1081
1082 for (auto str : cell_exprs)
1083 f << str;
1084
1085 f << stringf("\n");
1086
1087 for (auto str : wire_exprs)
1088 f << str;
1089 }
1090 };
1091
1092 struct FirrtlBackend : public Backend {
1093 FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
1094 void help() YS_OVERRIDE
1095 {
1096 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1097 log("\n");
1098 log(" write_firrtl [options] [filename]\n");
1099 log("\n");
1100 log("Write a FIRRTL netlist of the current design.\n");
1101 log("The following commands are executed by this command:\n");
1102 log(" pmuxtree\n");
1103 log("\n");
1104 }
1105 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1106 {
1107 size_t argidx = args.size(); // We aren't expecting any arguments.
1108
1109 // If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
1110 if (filename == "") {
1111 if (argidx > 0 && args[argidx - 1][0] != '-') {
1112 // extra_args and friends need to see this argument.
1113 argidx -= 1;
1114 filename = args[argidx];
1115 }
1116 }
1117 extra_args(f, filename, args, argidx);
1118
1119 if (!design->full_selection())
1120 log_cmd_error("This command only operates on fully selected designs!\n");
1121
1122 log_header(design, "Executing FIRRTL backend.\n");
1123 log_push();
1124
1125 Pass::call(design, stringf("pmuxtree"));
1126
1127 namecache.clear();
1128 autoid_counter = 0;
1129
1130 // Get the top module, or a reasonable facsimile - we need something for the circuit name.
1131 Module *top = design->top_module();
1132 Module *last = nullptr;
1133 // Generate module and wire names.
1134 for (auto module : design->modules()) {
1135 make_id(module->name);
1136 last = module;
1137 if (top == nullptr && module->get_bool_attribute(ID::top)) {
1138 top = module;
1139 }
1140 for (auto wire : module->wires())
1141 if (wire->port_id)
1142 make_id(wire->name);
1143 }
1144
1145 if (top == nullptr)
1146 top = last;
1147
1148 std::string circuitFileinfo = getFileinfo(top);
1149 *f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo.c_str());
1150
1151 for (auto module : design->modules())
1152 {
1153 FirrtlWorker worker(module, *f, design);
1154 worker.run();
1155 }
1156
1157 namecache.clear();
1158 autoid_counter = 0;
1159 }
1160 } FirrtlBackend;
1161
1162 PRIVATE_NAMESPACE_END