2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
33 PRIVATE_NAMESPACE_BEGIN
35 pool
<string
> used_names
;
36 dict
<IdString
, string
> namecache
;
39 typedef unsigned FDirection
;
40 static const FDirection FD_NODIRECTION
= 0x0;
41 static const FDirection FD_IN
= 0x1;
42 static const FDirection FD_OUT
= 0x2;
43 static const FDirection FD_INOUT
= 0x3;
44 static const int FIRRTL_MAX_DSH_WIDTH_ERROR
= 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
46 // Get a port direction with respect to a specific module.
47 FDirection
getPortFDirection(IdString id
, Module
*module
)
49 Wire
*wire
= module
->wires_
.at(id
);
50 FDirection direction
= FD_NODIRECTION
;
51 if (wire
&& wire
->port_id
)
55 if (wire
->port_output
)
66 new_id
= stringf("_%d", autoid_counter
++);
67 if (used_names
.count(new_id
) == 0) break;
70 used_names
.insert(new_id
);
74 const char *make_id(IdString id
)
76 if (namecache
.count(id
) != 0)
77 return namecache
.at(id
).c_str();
79 string new_id
= log_id(id
);
81 for (int i
= 0; i
< GetSize(new_id
); i
++)
84 if ('a' <= ch
&& ch
<= 'z') continue;
85 if ('A' <= ch
&& ch
<= 'Z') continue;
86 if ('0' <= ch
&& ch
<= '9' && i
!= 0) continue;
87 if ('_' == ch
) continue;
91 while (used_names
.count(new_id
) != 0)
94 namecache
[id
] = new_id
;
95 used_names
.insert(new_id
);
96 return namecache
.at(id
).c_str();
104 dict
<SigBit
, pair
<string
, int>> reverse_wire_map
;
106 RTLIL::Design
*design
;
109 void register_reverse_wire_map(string id
, SigSpec sig
)
111 for (int i
= 0; i
< GetSize(sig
); i
++)
112 reverse_wire_map
[sig
[i
]] = make_pair(id
, i
);
115 FirrtlWorker(Module
*module
, std::ostream
&f
, RTLIL::Design
*theDesign
) : module(module
), f(f
), design(theDesign
), indent(" ")
119 string
make_expr(const SigSpec
&sig
)
123 for (auto chunk
: sig
.chunks())
127 if (chunk
.wire
== nullptr)
129 std::vector
<RTLIL::State
> bits
= chunk
.data
;
130 new_expr
= stringf("UInt<%d>(\"h", GetSize(bits
));
132 while (GetSize(bits
) % 4 != 0)
133 bits
.push_back(State::S0
);
135 for (int i
= GetSize(bits
)-4; i
>= 0; i
-= 4)
138 if (bits
[i
+0] == State::S1
) val
+= 1;
139 if (bits
[i
+1] == State::S1
) val
+= 2;
140 if (bits
[i
+2] == State::S1
) val
+= 4;
141 if (bits
[i
+3] == State::S1
) val
+= 8;
142 new_expr
.push_back(val
< 10 ? '0' + val
: 'a' + val
- 10);
147 else if (chunk
.offset
== 0 && chunk
.width
== chunk
.wire
->width
)
149 new_expr
= make_id(chunk
.wire
->name
);
153 string wire_id
= make_id(chunk
.wire
->name
);
154 new_expr
= stringf("bits(%s, %d, %d)", wire_id
.c_str(), chunk
.offset
+ chunk
.width
- 1, chunk
.offset
);
160 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
166 std::string
fid(RTLIL::IdString internal_id
)
168 return make_id(internal_id
);
171 std::string
cellname(RTLIL::Cell
*cell
)
173 return fid(cell
->name
).c_str();
176 void process_instance(RTLIL::Cell
*cell
, vector
<string
> &wire_exprs
)
178 std::string cell_type
= fid(cell
->type
);
179 std::string instanceOf
;
180 // If this is a parameterized module, its parent module is encoded in the cell type
181 if (cell
->type
.substr(0, 8) == "$paramod")
183 std::string::iterator it
;
184 for (it
= cell_type
.begin(); it
< cell_type
.end(); it
++)
187 case '\\': /* FALL_THROUGH */
188 case '=': /* FALL_THROUGH */
189 case '\'': /* FALL_THROUGH */
190 case '$': instanceOf
.append("_"); break;
191 default: instanceOf
.append(1, *it
); break;
197 instanceOf
= cell_type
;
200 std::string cell_name
= cellname(cell
);
201 std::string cell_name_comment
;
202 if (cell_name
!= fid(cell
->name
))
203 cell_name_comment
= " /* " + fid(cell
->name
) + " */ ";
205 cell_name_comment
= "";
206 // Find the module corresponding to this instance.
207 auto instModule
= design
->module(cell
->type
);
208 // If there is no instance for this, just return.
209 if (instModule
== NULL
)
211 log_warning("No instance for %s.%s\n", cell_type
.c_str(), cell_name
.c_str());
214 wire_exprs
.push_back(stringf("%s" "inst %s%s of %s", indent
.c_str(), cell_name
.c_str(), cell_name_comment
.c_str(), instanceOf
.c_str()));
216 for (auto it
= cell
->connections().begin(); it
!= cell
->connections().end(); ++it
) {
217 if (it
->second
.size() > 0) {
218 const SigSpec
&secondSig
= it
->second
;
219 const std::string firstName
= cell_name
+ "." + make_id(it
->first
);
220 const std::string secondExpr
= make_expr(secondSig
);
221 // Find the direction for this port.
222 FDirection dir
= getPortFDirection(it
->first
, instModule
);
223 std::string sourceExpr
, sinkExpr
;
224 const SigSpec
*sinkSig
= nullptr;
227 log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type
.c_str(), log_signal(it
->second
));
229 sourceExpr
= firstName
;
230 sinkExpr
= secondExpr
;
231 sinkSig
= &secondSig
;
234 log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type
.c_str(), log_signal(it
->second
));
237 sourceExpr
= secondExpr
;
238 sinkExpr
= firstName
;
241 log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type
.c_str(), log_signal(it
->second
), dir
);
244 // Check for subfield assignment.
245 std::string bitsString
= "bits(";
246 if (sinkExpr
.substr(0, bitsString
.length()) == bitsString
) {
247 if (sinkSig
== nullptr)
248 log_error("Unknown subfield %s.%s\n", cell_type
.c_str(), sinkExpr
.c_str());
249 // Don't generate the assignment here.
250 // Add the source and sink to the "reverse_wire_map" and we'll output the assignment
251 // as part of the coalesced subfield assignments for this wire.
252 register_reverse_wire_map(sourceExpr
, *sinkSig
);
254 wire_exprs
.push_back(stringf("\n%s%s <= %s", indent
.c_str(), sinkExpr
.c_str(), sourceExpr
.c_str()));
258 wire_exprs
.push_back(stringf("\n"));
262 // Given an expression for a shift amount, and a maximum width,
263 // generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
264 std::string
gen_dshl(const string b_expr
, const int b_padded_width
)
266 string result
= b_expr
;
267 if (b_padded_width
>= FIRRTL_MAX_DSH_WIDTH_ERROR
) {
268 int max_shift_width_bits
= FIRRTL_MAX_DSH_WIDTH_ERROR
- 1;
269 string max_shift_string
= stringf("UInt<%d>(%d)", max_shift_width_bits
, (1<<max_shift_width_bits
) - 1);
270 // Deal with the difference in semantics between FIRRTL and verilog
271 result
= stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr
.c_str(), max_shift_string
.c_str(), max_shift_string
.c_str(), b_expr
.c_str(), max_shift_width_bits
- 1);
278 f
<< stringf(" module %s:\n", make_id(module
->name
));
279 vector
<string
> port_decls
, wire_decls
, cell_exprs
, wire_exprs
;
281 for (auto wire
: module
->wires())
283 const auto wireName
= make_id(wire
->name
);
284 // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
285 if (wire
->attributes
.count("\\init")) {
286 log_warning("Initial value (%s) for (%s.%s) not supported\n",
287 wire
->attributes
.at("\\init").as_string().c_str(),
288 log_id(module
), log_id(wire
));
292 if (wire
->port_input
&& wire
->port_output
)
293 log_error("Module port %s.%s is inout!\n", log_id(module
), log_id(wire
));
294 port_decls
.push_back(stringf(" %s %s: UInt<%d>\n", wire
->port_input
? "input" : "output",
295 wireName
, wire
->width
));
299 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", wireName
, wire
->width
));
303 for (auto cell
: module
->cells())
305 bool extract_y_bits
= false; // Assume no extraction of final bits will be required.
306 // Is this cell is a module instance?
307 if (cell
->type
[0] != '$')
309 process_instance(cell
, wire_exprs
);
312 if (cell
->type
.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
314 string y_id
= make_id(cell
->name
);
315 bool is_signed
= cell
->parameters
.at("\\A_SIGNED").as_bool();
316 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
317 string a_expr
= make_expr(cell
->getPort("\\A"));
318 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
320 if (cell
->parameters
.at("\\A_SIGNED").as_bool()) {
321 a_expr
= "asSInt(" + a_expr
+ ")";
324 // Don't use the results of logical operations (a single bit) to control padding
325 if (!(cell
->type
.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width
== 1) ) {
326 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
330 bool always_uint
= false;
331 if (cell
->type
== "$not") primop
= "not";
332 else if (cell
->type
== "$neg") primop
= "neg";
333 else if (cell
->type
== "$logic_not") {
335 a_expr
= stringf("%s, UInt(0)", a_expr
.c_str());
337 else if (cell
->type
== "$reduce_and") primop
= "andr";
338 else if (cell
->type
== "$reduce_or") primop
= "orr";
339 else if (cell
->type
== "$reduce_xor") primop
= "xorr";
340 else if (cell
->type
== "$reduce_xnor") {
342 a_expr
= stringf("xorr(%s)", a_expr
.c_str());
344 else if (cell
->type
== "$reduce_bool") {
346 // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
347 bool a_signed
= cell
->parameters
.at("\\A_SIGNED").as_bool();
348 int a_width
= cell
->parameters
.at("\\A_WIDTH").as_int();
349 a_expr
= stringf("%s, %cInt<%d>(0)", a_expr
.c_str(), a_signed
? 'S' : 'U', a_width
);
352 string expr
= stringf("%s(%s)", primop
.c_str(), a_expr
.c_str());
354 if ((is_signed
&& !always_uint
))
355 expr
= stringf("asUInt(%s)", expr
.c_str());
357 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
358 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
362 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$and", "$or", "$eq", "$eqx",
363 "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
364 "$logic_and", "$logic_or"))
366 string y_id
= make_id(cell
->name
);
367 bool is_signed
= cell
->parameters
.at("\\A_SIGNED").as_bool();
368 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
369 string a_expr
= make_expr(cell
->getPort("\\A"));
370 string b_expr
= make_expr(cell
->getPort("\\B"));
371 int b_padded_width
= cell
->parameters
.at("\\B_WIDTH").as_int();
372 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
374 if (cell
->parameters
.at("\\A_SIGNED").as_bool()) {
375 a_expr
= "asSInt(" + a_expr
+ ")";
377 // Shift amount is always unsigned, and needn't be padded to result width.
378 if (!cell
->type
.in("$shr", "$sshr", "$shl", "$sshl")) {
379 if (cell
->parameters
.at("\\B_SIGNED").as_bool()) {
380 b_expr
= "asSInt(" + b_expr
+ ")";
382 if (b_padded_width
< y_width
) {
383 auto b_sig
= cell
->getPort("\\B");
384 b_padded_width
= y_width
;
388 auto a_sig
= cell
->getPort("\\A");
390 if (cell
->parameters
.at("\\A_SIGNED").as_bool() & (cell
->type
== "$shr")) {
391 a_expr
= "asUInt(" + a_expr
+ ")";
395 bool always_uint
= false;
396 if (cell
->type
== "$add") primop
= "add";
397 else if (cell
->type
== "$sub") primop
= "sub";
398 else if (cell
->type
== "$mul") primop
= "mul";
399 else if (cell
->type
== "$div") primop
= "div";
400 else if (cell
->type
== "$mod") primop
= "rem";
401 else if (cell
->type
== "$and") {
405 else if (cell
->type
== "$or" ) {
409 else if (cell
->type
== "$xor") {
413 else if ((cell
->type
== "$eq") | (cell
->type
== "$eqx")) {
417 else if ((cell
->type
== "$ne") | (cell
->type
== "$nex")) {
421 else if (cell
->type
== "$gt") {
425 else if (cell
->type
== "$ge") {
429 else if (cell
->type
== "$lt") {
433 else if (cell
->type
== "$le") {
437 else if ((cell
->type
== "$shl") | (cell
->type
== "$sshl")) {
438 // FIRRTL will widen the result (y) by the amount of the shift.
439 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
440 extract_y_bits
= true;
441 // Is the shift amount constant?
442 auto b_sig
= cell
->getPort("\\B");
443 if (b_sig
.is_fully_const()) {
447 // Convert from FIRRTL left shift semantics.
448 b_expr
= gen_dshl(b_expr
, b_padded_width
);
451 else if ((cell
->type
== "$shr") | (cell
->type
== "$sshr")) {
452 // We don't need to extract a specific range of bits.
453 extract_y_bits
= false;
454 // Is the shift amount constant?
455 auto b_sig
= cell
->getPort("\\B");
456 if (b_sig
.is_fully_const()) {
462 else if ((cell
->type
== "$logic_and")) {
464 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
465 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
468 else if ((cell
->type
== "$logic_or")) {
470 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
471 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
475 if (!cell
->parameters
.at("\\B_SIGNED").as_bool()) {
476 b_expr
= "asUInt(" + b_expr
+ ")";
479 string expr
= stringf("%s(%s, %s)", primop
.c_str(), a_expr
.c_str(), b_expr
.c_str());
481 // Deal with FIRRTL's "shift widens" semantics
482 if (extract_y_bits
) {
483 expr
= stringf("bits(%s, %d, 0)", expr
.c_str(), y_width
- 1);
486 if ((is_signed
&& !always_uint
) || cell
->type
.in("$sub"))
487 expr
= stringf("asUInt(%s)", expr
.c_str());
489 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
490 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
495 if (cell
->type
.in("$mux"))
497 string y_id
= make_id(cell
->name
);
498 int width
= cell
->parameters
.at("\\WIDTH").as_int();
499 string a_expr
= make_expr(cell
->getPort("\\A"));
500 string b_expr
= make_expr(cell
->getPort("\\B"));
501 string s_expr
= make_expr(cell
->getPort("\\S"));
502 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), width
));
504 string expr
= stringf("mux(%s, %s, %s)", s_expr
.c_str(), b_expr
.c_str(), a_expr
.c_str());
506 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
507 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
512 if (cell
->type
.in("$mem"))
514 string mem_id
= make_id(cell
->name
);
515 int abits
= cell
->parameters
.at("\\ABITS").as_int();
516 int width
= cell
->parameters
.at("\\WIDTH").as_int();
517 int size
= cell
->parameters
.at("\\SIZE").as_int();
518 int rd_ports
= cell
->parameters
.at("\\RD_PORTS").as_int();
519 int wr_ports
= cell
->parameters
.at("\\WR_PORTS").as_int();
521 Const initdata
= cell
->parameters
.at("\\INIT");
522 for (State bit
: initdata
.bits
)
523 if (bit
!= State::Sx
)
524 log_error("Memory with initialization data: %s.%s\n", log_id(module
), log_id(cell
));
526 Const rd_clk_enable
= cell
->parameters
.at("\\RD_CLK_ENABLE");
527 Const wr_clk_enable
= cell
->parameters
.at("\\WR_CLK_ENABLE");
528 Const wr_clk_polarity
= cell
->parameters
.at("\\WR_CLK_POLARITY");
530 int offset
= cell
->parameters
.at("\\OFFSET").as_int();
532 log_error("Memory with nonzero offset: %s.%s\n", log_id(module
), log_id(cell
));
534 cell_exprs
.push_back(stringf(" mem %s:\n", mem_id
.c_str()));
535 cell_exprs
.push_back(stringf(" data-type => UInt<%d>\n", width
));
536 cell_exprs
.push_back(stringf(" depth => %d\n", size
));
538 for (int i
= 0; i
< rd_ports
; i
++)
539 cell_exprs
.push_back(stringf(" reader => r%d\n", i
));
541 for (int i
= 0; i
< wr_ports
; i
++)
542 cell_exprs
.push_back(stringf(" writer => w%d\n", i
));
544 cell_exprs
.push_back(stringf(" read-latency => 0\n"));
545 cell_exprs
.push_back(stringf(" write-latency => 1\n"));
546 cell_exprs
.push_back(stringf(" read-under-write => undefined\n"));
548 for (int i
= 0; i
< rd_ports
; i
++)
550 if (rd_clk_enable
[i
] != State::S0
)
551 log_error("Clocked read port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
553 SigSpec data_sig
= cell
->getPort("\\RD_DATA").extract(i
*width
, width
);
554 string addr_expr
= make_expr(cell
->getPort("\\RD_ADDR").extract(i
*abits
, abits
));
556 cell_exprs
.push_back(stringf(" %s.r%d.addr <= %s\n", mem_id
.c_str(), i
, addr_expr
.c_str()));
557 cell_exprs
.push_back(stringf(" %s.r%d.en <= UInt<1>(1)\n", mem_id
.c_str(), i
));
558 cell_exprs
.push_back(stringf(" %s.r%d.clk <= asClock(UInt<1>(0))\n", mem_id
.c_str(), i
));
560 register_reverse_wire_map(stringf("%s.r%d.data", mem_id
.c_str(), i
), data_sig
);
563 for (int i
= 0; i
< wr_ports
; i
++)
565 if (wr_clk_enable
[i
] != State::S1
)
566 log_error("Unclocked write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
568 if (wr_clk_polarity
[i
] != State::S1
)
569 log_error("Negedge write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
571 string addr_expr
= make_expr(cell
->getPort("\\WR_ADDR").extract(i
*abits
, abits
));
572 string data_expr
= make_expr(cell
->getPort("\\WR_DATA").extract(i
*width
, width
));
573 string clk_expr
= make_expr(cell
->getPort("\\WR_CLK").extract(i
));
575 SigSpec wen_sig
= cell
->getPort("\\WR_EN").extract(i
*width
, width
);
576 string wen_expr
= make_expr(wen_sig
[0]);
578 for (int i
= 1; i
< GetSize(wen_sig
); i
++)
579 if (wen_sig
[0] != wen_sig
[i
])
580 log_error("Complex write enable on port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
582 cell_exprs
.push_back(stringf(" %s.w%d.addr <= %s\n", mem_id
.c_str(), i
, addr_expr
.c_str()));
583 cell_exprs
.push_back(stringf(" %s.w%d.data <= %s\n", mem_id
.c_str(), i
, data_expr
.c_str()));
584 cell_exprs
.push_back(stringf(" %s.w%d.en <= %s\n", mem_id
.c_str(), i
, wen_expr
.c_str()));
585 cell_exprs
.push_back(stringf(" %s.w%d.mask <= UInt<1>(1)\n", mem_id
.c_str(), i
));
586 cell_exprs
.push_back(stringf(" %s.w%d.clk <= asClock(%s)\n", mem_id
.c_str(), i
, clk_expr
.c_str()));
592 if (cell
->type
.in("$dff"))
594 bool clkpol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool();
596 log_error("Negative edge clock on FF %s.%s.\n", log_id(module
), log_id(cell
));
598 string q_id
= make_id(cell
->name
);
599 int width
= cell
->parameters
.at("\\WIDTH").as_int();
600 string expr
= make_expr(cell
->getPort("\\D"));
601 string clk_expr
= "asClock(" + make_expr(cell
->getPort("\\CLK")) + ")";
603 wire_decls
.push_back(stringf(" reg %s: UInt<%d>, %s\n", q_id
.c_str(), width
, clk_expr
.c_str()));
605 cell_exprs
.push_back(stringf(" %s <= %s\n", q_id
.c_str(), expr
.c_str()));
606 register_reverse_wire_map(q_id
, cell
->getPort("\\Q"));
611 // This may be a parameterized module - paramod.
612 if (cell
->type
.substr(0, 8) == "$paramod")
614 process_instance(cell
, wire_exprs
);
617 if (cell
->type
== "$shiftx") {
618 // assign y = a[b +: y_width];
619 // We'll extract the correct bits as part of the primop.
621 string y_id
= make_id(cell
->name
);
622 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
623 string a_expr
= make_expr(cell
->getPort("\\A"));
624 // Get the initial bit selector
625 string b_expr
= make_expr(cell
->getPort("\\B"));
626 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
628 if (cell
->getParam("\\B_SIGNED").as_bool()) {
629 // Use validif to constrain the selection (test the sign bit)
630 auto b_string
= b_expr
.c_str();
631 int b_sign
= cell
->parameters
.at("\\B_WIDTH").as_int() - 1;
632 b_expr
= stringf("validif(not(bits(%s, %d, %d)), %s)", b_string
, b_sign
, b_sign
, b_string
);
634 string expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_expr
.c_str());
636 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
637 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
640 if (cell
->type
== "$shift") {
641 // assign y = a >> b;
642 // where b may be negative
644 string y_id
= make_id(cell
->name
);
645 int y_width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
646 string a_expr
= make_expr(cell
->getPort("\\A"));
647 string b_expr
= make_expr(cell
->getPort("\\B"));
648 auto b_string
= b_expr
.c_str();
649 int b_padded_width
= cell
->parameters
.at("\\B_WIDTH").as_int();
651 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
653 if (cell
->getParam("\\B_SIGNED").as_bool()) {
654 // We generate a left or right shift based on the sign of b.
655 std::string dshl
= stringf("bits(dshl(%s, %s), 0, %d)", a_expr
.c_str(), gen_dshl(b_expr
, b_padded_width
).c_str(), y_width
);
656 std::string dshr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
657 expr
= stringf("mux(%s < 0, %s, %s)",
663 expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
665 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
666 register_reverse_wire_map(y_id
, cell
->getPort("\\Y"));
669 log_warning("Cell type not supported: %s (%s.%s)\n", log_id(cell
->type
), log_id(module
), log_id(cell
));
672 for (auto conn
: module
->connections())
674 string y_id
= next_id();
675 int y_width
= GetSize(conn
.first
);
676 string expr
= make_expr(conn
.second
);
678 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
679 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
680 register_reverse_wire_map(y_id
, conn
.first
);
683 for (auto wire
: module
->wires())
687 if (wire
->port_input
)
691 bool is_valid
= false;
692 bool make_unconn_id
= false;
694 while (cursor
< wire
->width
)
699 SigBit
start_bit(wire
, cursor
);
701 if (reverse_wire_map
.count(start_bit
))
703 pair
<string
, int> start_map
= reverse_wire_map
.at(start_bit
);
705 while (cursor
+chunk_width
< wire
->width
)
707 SigBit
stop_bit(wire
, cursor
+chunk_width
);
709 if (reverse_wire_map
.count(stop_bit
) == 0)
712 pair
<string
, int> stop_map
= reverse_wire_map
.at(stop_bit
);
713 stop_map
.second
-= chunk_width
;
715 if (start_map
!= stop_map
)
721 new_expr
= stringf("bits(%s, %d, %d)", start_map
.first
.c_str(),
722 start_map
.second
+ chunk_width
- 1, start_map
.second
);
727 if (unconn_id
.empty()) {
728 unconn_id
= next_id();
729 make_unconn_id
= true;
731 new_expr
= unconn_id
;
737 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
739 cursor
+= chunk_width
;
743 if (make_unconn_id
) {
744 wire_decls
.push_back(stringf(" wire %s: UInt<1>\n", unconn_id
.c_str()));
745 wire_decls
.push_back(stringf(" %s is invalid\n", unconn_id
.c_str()));
747 wire_exprs
.push_back(stringf(" %s <= %s\n", make_id(wire
->name
), expr
.c_str()));
749 if (make_unconn_id
) {
752 wire_decls
.push_back(stringf(" %s is invalid\n", make_id(wire
->name
)));
756 for (auto str
: port_decls
)
761 for (auto str
: wire_decls
)
766 for (auto str
: cell_exprs
)
771 for (auto str
: wire_exprs
)
776 struct FirrtlBackend
: public Backend
{
777 FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
778 void help() YS_OVERRIDE
780 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
782 log(" write_firrtl [options] [filename]\n");
784 log("Write a FIRRTL netlist of the current design.\n");
785 log("The following commands are executed by this command:\n");
789 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
791 size_t argidx
= args
.size(); // We aren't expecting any arguments.
793 // If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
794 if (filename
== "") {
795 if (argidx
> 0 && args
[argidx
- 1][0] != '-') {
796 // extra_args and friends need to see this argument.
798 filename
= args
[argidx
];
801 extra_args(f
, filename
, args
, argidx
);
803 if (!design
->full_selection())
804 log_cmd_error("This command only operates on fully selected designs!\n");
806 log_header(design
, "Executing FIRRTL backend.\n");
809 Pass::call(design
, stringf("pmuxtree"));
814 // Get the top module, or a reasonable facsimile - we need something for the circuit name.
815 Module
*top
= design
->top_module();
816 Module
*last
= nullptr;
817 // Generate module and wire names.
818 for (auto module
: design
->modules()) {
819 make_id(module
->name
);
821 if (top
== nullptr && module
->get_bool_attribute("\\top")) {
824 for (auto wire
: module
->wires())
832 *f
<< stringf("circuit %s:\n", make_id(top
->name
));
834 for (auto module
: design
->modules())
836 FirrtlWorker
worker(module
, *f
, design
);
845 PRIVATE_NAMESPACE_END