2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
32 PRIVATE_NAMESPACE_BEGIN
34 pool
<string
> used_names
;
35 dict
<IdString
, string
> namecache
;
38 typedef unsigned FDirection
;
39 static const FDirection FD_NODIRECTION
= 0x0;
40 static const FDirection FD_IN
= 0x1;
41 static const FDirection FD_OUT
= 0x2;
42 static const FDirection FD_INOUT
= 0x3;
43 static const int FIRRTL_MAX_DSH_WIDTH_ERROR
= 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
45 std::string
getFileinfo(const RTLIL::AttrObject
*design_entity
)
47 std::string
src(design_entity
->get_src_attribute());
48 std::string fileinfo_str
= src
.empty() ? "" : "@[" + src
+ "]";
52 // Get a port direction with respect to a specific module.
53 FDirection
getPortFDirection(IdString id
, Module
*module
)
55 Wire
*wire
= module
->wires_
.at(id
);
56 FDirection direction
= FD_NODIRECTION
;
57 if (wire
&& wire
->port_id
)
61 if (wire
->port_output
)
72 new_id
= stringf("_%d", autoid_counter
++);
73 if (used_names
.count(new_id
) == 0) break;
76 used_names
.insert(new_id
);
80 const char *make_id(IdString id
)
82 if (namecache
.count(id
) != 0)
83 return namecache
.at(id
).c_str();
85 string new_id
= log_id(id
);
87 for (int i
= 0; i
< GetSize(new_id
); i
++)
90 if ('a' <= ch
&& ch
<= 'z') continue;
91 if ('A' <= ch
&& ch
<= 'Z') continue;
92 if ('0' <= ch
&& ch
<= '9' && i
!= 0) continue;
93 if ('_' == ch
) continue;
97 while (used_names
.count(new_id
) != 0)
100 namecache
[id
] = new_id
;
101 used_names
.insert(new_id
);
102 return namecache
.at(id
).c_str();
110 dict
<SigBit
, pair
<string
, int>> reverse_wire_map
;
112 RTLIL::Design
*design
;
115 // Define read/write ports and memories.
116 // We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
117 // For the moment, we don't handle $readmemh or $readmemb.
118 // These will be part of a subsequent PR.
127 read_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
) : name(name
), clk_enable(clk_enable
), clk_parity(clk_parity
), transparent(transparent
), clk(clk
), ena(ena
), addr(addr
) {
128 // Current (3/13/2019) conventions:
129 // generate a constant 0 for clock and a constant 1 for enable if they are undefined.
130 if (!clk
.is_fully_def())
131 this->clk
= SigSpec(State::S0
);
132 if (!ena
.is_fully_def())
133 this->ena
= SigSpec(State::S1
);
135 string
gen_read(const char * indent
) {
136 string addr_expr
= make_expr(addr
);
137 string ena_expr
= make_expr(ena
);
138 string clk_expr
= make_expr(clk
);
139 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
140 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
141 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
142 return addr_str
+ ena_str
+ clk_str
;
145 struct write_port
: read_port
{
147 write_port(string name
, bool clk_enable
, bool clk_parity
, bool transparent
, RTLIL::SigSpec clk
, RTLIL::SigSpec ena
, RTLIL::SigSpec addr
, RTLIL::SigSpec mask
) : read_port(name
, clk_enable
, clk_parity
, transparent
, clk
, ena
, addr
), mask(mask
) {
148 if (!clk
.is_fully_def())
149 this->clk
= SigSpec(RTLIL::Const(0));
150 if (!ena
.is_fully_def())
151 this->ena
= SigSpec(RTLIL::Const(0));
152 if (!mask
.is_fully_def())
153 this->ena
= SigSpec(RTLIL::Const(1));
155 string
gen_read(const char * /* indent */) {
156 log_error("gen_read called on write_port: %s\n", name
.c_str());
157 return stringf("gen_read called on write_port: %s\n", name
.c_str());
159 string
gen_write(const char * indent
) {
160 string addr_expr
= make_expr(addr
);
161 string ena_expr
= make_expr(ena
);
162 string clk_expr
= make_expr(clk
);
163 string mask_expr
= make_expr(mask
);
164 string mask_str
= stringf("%s%s.mask <= %s\n", indent
, name
.c_str(), mask_expr
.c_str());
165 string addr_str
= stringf("%s%s.addr <= %s\n", indent
, name
.c_str(), addr_expr
.c_str());
166 string ena_str
= stringf("%s%s.en <= %s\n", indent
, name
.c_str(), ena_expr
.c_str());
167 string clk_str
= stringf("%s%s.clk <= asClock(%s)\n", indent
, name
.c_str(), clk_expr
.c_str());
168 return addr_str
+ ena_str
+ clk_str
+ mask_str
;
171 /* Memories defined within this module. */
173 Cell
*pCell
; // for error reporting
174 string name
; // memory name
175 int abits
; // number of address bits
176 int size
; // size (in units) of the memory
177 int width
; // size (in bits) of each element
180 vector
<read_port
> read_ports
;
181 vector
<write_port
> write_ports
;
182 std::string init_file
;
183 std::string init_file_srcFileSpec
;
185 memory(Cell
*pCell
, string name
, int abits
, int size
, int width
) : pCell(pCell
), name(name
), abits(abits
), size(size
), width(width
), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
186 // Provide defaults for abits or size if one (but not the other) is specified.
187 if (this->abits
== 0 && this->size
!= 0) {
188 this->abits
= ceil_log2(this->size
);
189 } else if (this->abits
!= 0 && this->size
== 0) {
190 this->size
= 1 << this->abits
;
192 // Sanity-check this construction.
193 if (this->name
== "") {
194 log_error("Nameless memory%s\n", this->atLine());
196 if (this->abits
== 0 && this->size
== 0) {
197 log_error("Memory %s has zero address bits and size%s\n", this->name
.c_str(), this->atLine());
199 if (this->width
== 0) {
200 log_error("Memory %s has zero width%s\n", this->name
.c_str(), this->atLine());
204 // We need a default constructor for the dict insert.
205 memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
207 const char *atLine() {
210 auto p
= pCell
->attributes
.find(ID::src
);
211 srcLine
= " at " + p
->second
.decode_string();
214 return srcLine
.c_str();
216 void add_memory_read_port(read_port
&rp
) {
217 read_ports
.push_back(rp
);
219 void add_memory_write_port(write_port
&wp
) {
220 write_ports
.push_back(wp
);
222 void add_memory_file(std::string init_file
, std::string init_file_srcFileSpec
) {
223 this->init_file
= init_file
;
224 this->init_file_srcFileSpec
= init_file_srcFileSpec
;
228 dict
<string
, memory
> memories
;
230 void register_memory(memory
&m
)
232 memories
[m
.name
] = m
;
235 void register_reverse_wire_map(string id
, SigSpec sig
)
237 for (int i
= 0; i
< GetSize(sig
); i
++)
238 reverse_wire_map
[sig
[i
]] = make_pair(id
, i
);
241 FirrtlWorker(Module
*module
, std::ostream
&f
, RTLIL::Design
*theDesign
) : module(module
), f(f
), design(theDesign
), indent(" ")
245 static string
make_expr(const SigSpec
&sig
)
249 for (auto chunk
: sig
.chunks())
253 if (chunk
.wire
== nullptr)
255 std::vector
<RTLIL::State
> bits
= chunk
.data
;
256 new_expr
= stringf("UInt<%d>(\"h", GetSize(bits
));
258 while (GetSize(bits
) % 4 != 0)
259 bits
.push_back(State::S0
);
261 for (int i
= GetSize(bits
)-4; i
>= 0; i
-= 4)
264 if (bits
[i
+0] == State::S1
) val
+= 1;
265 if (bits
[i
+1] == State::S1
) val
+= 2;
266 if (bits
[i
+2] == State::S1
) val
+= 4;
267 if (bits
[i
+3] == State::S1
) val
+= 8;
268 new_expr
.push_back(val
< 10 ? '0' + val
: 'a' + val
- 10);
273 else if (chunk
.offset
== 0 && chunk
.width
== chunk
.wire
->width
)
275 new_expr
= make_id(chunk
.wire
->name
);
279 string wire_id
= make_id(chunk
.wire
->name
);
280 new_expr
= stringf("bits(%s, %d, %d)", wire_id
.c_str(), chunk
.offset
+ chunk
.width
- 1, chunk
.offset
);
286 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
292 std::string
fid(RTLIL::IdString internal_id
)
294 return make_id(internal_id
);
297 std::string
cellname(RTLIL::Cell
*cell
)
299 return fid(cell
->name
).c_str();
302 void process_instance(RTLIL::Cell
*cell
, vector
<string
> &wire_exprs
)
304 std::string cell_type
= fid(cell
->type
);
305 std::string instanceOf
;
306 // If this is a parameterized module, its parent module is encoded in the cell type
307 if (cell
->type
.begins_with("$paramod"))
309 log_assert(cell
->has_attribute(ID::hdlname
));
310 instanceOf
= cell
->get_string_attribute(ID::hdlname
);
314 instanceOf
= cell_type
;
317 std::string cell_name
= cellname(cell
);
318 std::string cell_name_comment
;
319 if (cell_name
!= fid(cell
->name
))
320 cell_name_comment
= " /* " + fid(cell
->name
) + " */ ";
322 cell_name_comment
= "";
323 // Find the module corresponding to this instance.
324 auto instModule
= design
->module(cell
->type
);
325 // If there is no instance for this, just return.
326 if (instModule
== NULL
)
328 log_warning("No instance for %s.%s\n", cell_type
.c_str(), cell_name
.c_str());
331 std::string cellFileinfo
= getFileinfo(cell
);
332 wire_exprs
.push_back(stringf("%s" "inst %s%s of %s %s", indent
.c_str(), cell_name
.c_str(), cell_name_comment
.c_str(), instanceOf
.c_str(), cellFileinfo
.c_str()));
334 for (auto it
= cell
->connections().begin(); it
!= cell
->connections().end(); ++it
) {
335 if (it
->second
.size() > 0) {
336 const SigSpec
&secondSig
= it
->second
;
337 const std::string firstName
= cell_name
+ "." + make_id(it
->first
);
338 const std::string secondExpr
= make_expr(secondSig
);
339 // Find the direction for this port.
340 FDirection dir
= getPortFDirection(it
->first
, instModule
);
341 std::string sourceExpr
, sinkExpr
;
342 const SigSpec
*sinkSig
= nullptr;
345 log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type
.c_str(), log_signal(it
->second
));
348 sourceExpr
= firstName
;
349 sinkExpr
= secondExpr
;
350 sinkSig
= &secondSig
;
353 log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type
.c_str(), log_signal(it
->second
));
356 sourceExpr
= secondExpr
;
357 sinkExpr
= firstName
;
360 log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type
.c_str(), log_signal(it
->second
), dir
);
363 // Check for subfield assignment.
364 std::string bitsString
= "bits(";
365 if (sinkExpr
.compare(0, bitsString
.length(), bitsString
) == 0) {
366 if (sinkSig
== nullptr)
367 log_error("Unknown subfield %s.%s\n", cell_type
.c_str(), sinkExpr
.c_str());
368 // Don't generate the assignment here.
369 // Add the source and sink to the "reverse_wire_map" and we'll output the assignment
370 // as part of the coalesced subfield assignments for this wire.
371 register_reverse_wire_map(sourceExpr
, *sinkSig
);
373 wire_exprs
.push_back(stringf("\n%s%s <= %s %s", indent
.c_str(), sinkExpr
.c_str(), sourceExpr
.c_str(), cellFileinfo
.c_str()));
377 wire_exprs
.push_back(stringf("\n"));
381 // Given an expression for a shift amount, and a maximum width,
382 // generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
383 std::string
gen_dshl(const string b_expr
, const int b_width
)
385 string result
= b_expr
;
386 if (b_width
>= FIRRTL_MAX_DSH_WIDTH_ERROR
) {
387 int max_shift_width_bits
= FIRRTL_MAX_DSH_WIDTH_ERROR
- 1;
388 string max_shift_string
= stringf("UInt<%d>(%d)", max_shift_width_bits
, (1<<max_shift_width_bits
) - 1);
389 // Deal with the difference in semantics between FIRRTL and verilog
390 result
= stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr
.c_str(), max_shift_string
.c_str(), max_shift_string
.c_str(), b_expr
.c_str(), max_shift_width_bits
- 1);
397 std::string moduleFileinfo
= getFileinfo(module
);
398 f
<< stringf(" module %s: %s\n", make_id(module
->name
), moduleFileinfo
.c_str());
399 vector
<string
> port_decls
, wire_decls
, cell_exprs
, wire_exprs
;
401 for (auto wire
: module
->wires())
403 const auto wireName
= make_id(wire
->name
);
404 std::string wireFileinfo
= getFileinfo(wire
);
406 // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
407 if (wire
->attributes
.count(ID::init
)) {
408 log_warning("Initial value (%s) for (%s.%s) not supported\n",
409 wire
->attributes
.at(ID::init
).as_string().c_str(),
410 log_id(module
), log_id(wire
));
414 if (wire
->port_input
&& wire
->port_output
)
415 log_error("Module port %s.%s is inout!\n", log_id(module
), log_id(wire
));
416 port_decls
.push_back(stringf(" %s %s: UInt<%d> %s\n", wire
->port_input
? "input" : "output",
417 wireName
, wire
->width
, wireFileinfo
.c_str()));
421 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", wireName
, wire
->width
, wireFileinfo
.c_str()));
425 for (auto cell
: module
->cells())
427 static Const
ndef(0, 0);
429 // Is this cell is a module instance?
430 if (cell
->type
[0] != '$')
432 process_instance(cell
, wire_exprs
);
435 // Not a module instance. Set up cell properties
436 bool extract_y_bits
= false; // Assume no extraction of final bits will be required.
437 int a_width
= cell
->parameters
.at(ID::A_WIDTH
, ndef
).as_int(); // The width of "A"
438 int b_width
= cell
->parameters
.at(ID::B_WIDTH
, ndef
).as_int(); // The width of "A"
439 const int y_width
= cell
->parameters
.at(ID::Y_WIDTH
, ndef
).as_int(); // The width of the result
440 const bool a_signed
= cell
->parameters
.at(ID::A_SIGNED
, ndef
).as_bool();
441 const bool b_signed
= cell
->parameters
.at(ID::B_SIGNED
, ndef
).as_bool();
442 bool firrtl_is_signed
= a_signed
; // The result is signed (subsequent code may change this).
443 int firrtl_width
= 0;
445 bool always_uint
= false;
446 string y_id
= make_id(cell
->name
);
447 std::string cellFileinfo
= getFileinfo(cell
);
449 if (cell
->type
.in(ID($
not), ID($logic_not
), ID($neg
), ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_bool
), ID($reduce_xnor
)))
451 string a_expr
= make_expr(cell
->getPort(ID::A
));
452 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), y_width
, cellFileinfo
.c_str()));
455 a_expr
= "asSInt(" + a_expr
+ ")";
458 // Don't use the results of logical operations (a single bit) to control padding
459 if (!(cell
->type
.in(ID($eq
), ID($eqx
), ID($gt
), ID($ge
), ID($lt
), ID($le
), ID($ne
), ID($nex
), ID($reduce_bool
), ID($logic_not
)) && y_width
== 1) ) {
460 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
463 // Assume the FIRRTL width is a single bit.
465 if (cell
->type
== ID($
not)) primop
= "not";
466 else if (cell
->type
== ID($neg
)) {
468 firrtl_is_signed
= true; // Result of "neg" is signed (an SInt).
469 firrtl_width
= a_width
;
470 } else if (cell
->type
== ID($logic_not
)) {
472 a_expr
= stringf("%s, UInt(0)", a_expr
.c_str());
474 else if (cell
->type
== ID($reduce_and
)) primop
= "andr";
475 else if (cell
->type
== ID($reduce_or
)) primop
= "orr";
476 else if (cell
->type
== ID($reduce_xor
)) primop
= "xorr";
477 else if (cell
->type
== ID($reduce_xnor
)) {
479 a_expr
= stringf("xorr(%s)", a_expr
.c_str());
481 else if (cell
->type
== ID($reduce_bool
)) {
483 // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
484 a_expr
= stringf("%s, %cInt<%d>(0)", a_expr
.c_str(), a_signed
? 'S' : 'U', a_width
);
487 string expr
= stringf("%s(%s)", primop
.c_str(), a_expr
.c_str());
489 if ((firrtl_is_signed
&& !always_uint
))
490 expr
= stringf("asUInt(%s)", expr
.c_str());
492 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
493 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
497 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($
xor), ID($xnor
), ID($
and), ID($
or), ID($eq
), ID($eqx
),
498 ID($gt
), ID($ge
), ID($lt
), ID($le
), ID($ne
), ID($nex
), ID($shr
), ID($sshr
), ID($sshl
), ID($shl
),
499 ID($logic_and
), ID($logic_or
), ID($pow
)))
501 string a_expr
= make_expr(cell
->getPort(ID::A
));
502 string b_expr
= make_expr(cell
->getPort(ID::B
));
503 std::string cellFileinfo
= getFileinfo(cell
);
504 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), y_width
, cellFileinfo
.c_str()));
507 a_expr
= "asSInt(" + a_expr
+ ")";
508 // Expand the "A" operand to the result width
509 if (a_width
< y_width
) {
510 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
514 // Shift amount is always unsigned, and needn't be padded to result width,
515 // otherwise, we need to cast the b_expr appropriately
516 if (b_signed
&& !cell
->type
.in(ID($shr
), ID($sshr
), ID($shl
), ID($sshl
), ID($pow
))) {
517 b_expr
= "asSInt(" + b_expr
+ ")";
518 // Expand the "B" operand to the result width
519 if (b_width
< y_width
) {
520 b_expr
= stringf("pad(%s, %d)", b_expr
.c_str(), y_width
);
525 // For the arithmetic ops, expand operand widths to result widths befor performing the operation.
526 // This corresponds (according to iverilog) to what verilog compilers implement.
527 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($
xor), ID($xnor
), ID($
and), ID($
or)))
529 if (a_width
< y_width
) {
530 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
533 if (b_width
< y_width
) {
534 b_expr
= stringf("pad(%s, %d)", b_expr
.c_str(), y_width
);
538 // Assume the FIRRTL width is the width of "A"
539 firrtl_width
= a_width
;
540 auto a_sig
= cell
->getPort(ID::A
);
542 if (cell
->type
== ID($add
)) {
544 firrtl_is_signed
= a_signed
| b_signed
;
545 firrtl_width
= max(a_width
, b_width
);
546 } else if (cell
->type
== ID($sub
)) {
548 firrtl_is_signed
= true;
549 int a_widthInc
= (!a_signed
&& b_signed
) ? 2 : (a_signed
&& !b_signed
) ? 1 : 0;
550 int b_widthInc
= (a_signed
&& !b_signed
) ? 2 : (!a_signed
&& b_signed
) ? 1 : 0;
551 firrtl_width
= max(a_width
+ a_widthInc
, b_width
+ b_widthInc
);
552 } else if (cell
->type
== ID($mul
)) {
554 firrtl_is_signed
= a_signed
| b_signed
;
555 firrtl_width
= a_width
+ b_width
;
556 } else if (cell
->type
== ID($div
)) {
558 firrtl_is_signed
= a_signed
| b_signed
;
559 firrtl_width
= a_width
;
560 } else if (cell
->type
== ID($mod
)) {
562 firrtl_width
= min(a_width
, b_width
);
563 } else if (cell
->type
== ID($
and)) {
566 firrtl_width
= max(a_width
, b_width
);
568 else if (cell
->type
== ID($
or) ) {
571 firrtl_width
= max(a_width
, b_width
);
573 else if (cell
->type
== ID($
xor)) {
576 firrtl_width
= max(a_width
, b_width
);
578 else if (cell
->type
== ID($xnor
)) {
581 firrtl_width
= max(a_width
, b_width
);
583 else if ((cell
->type
== ID($eq
)) | (cell
->type
== ID($eqx
))) {
588 else if ((cell
->type
== ID($ne
)) | (cell
->type
== ID($nex
))) {
593 else if (cell
->type
== ID($gt
)) {
598 else if (cell
->type
== ID($ge
)) {
603 else if (cell
->type
== ID($lt
)) {
608 else if (cell
->type
== ID($le
)) {
613 else if ((cell
->type
== ID($shl
)) | (cell
->type
== ID($sshl
))) {
614 // FIRRTL will widen the result (y) by the amount of the shift.
615 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
616 extract_y_bits
= true;
617 // Is the shift amount constant?
618 auto b_sig
= cell
->getPort(ID::B
);
619 if (b_sig
.is_fully_const()) {
621 int shift_amount
= b_sig
.as_int();
622 b_expr
= std::to_string(shift_amount
);
623 firrtl_width
= a_width
+ shift_amount
;
626 // Convert from FIRRTL left shift semantics.
627 b_expr
= gen_dshl(b_expr
, b_width
);
628 firrtl_width
= a_width
+ (1 << b_width
) - 1;
631 else if ((cell
->type
== ID($shr
)) | (cell
->type
== ID($sshr
))) {
632 // We don't need to extract a specific range of bits.
633 extract_y_bits
= false;
634 // Is the shift amount constant?
635 auto b_sig
= cell
->getPort(ID::B
);
636 if (b_sig
.is_fully_const()) {
638 int shift_amount
= b_sig
.as_int();
639 b_expr
= std::to_string(shift_amount
);
640 firrtl_width
= max(1, a_width
- shift_amount
);
643 firrtl_width
= a_width
;
645 // We'll need to do some special fixups if the source (and thus result) is signed.
646 if (firrtl_is_signed
) {
647 // If this is a "logical" shift right, pretend the source is unsigned.
648 if (cell
->type
== ID($shr
)) {
649 a_expr
= "asUInt(" + a_expr
+ ")";
653 else if ((cell
->type
== ID($logic_and
))) {
655 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
656 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
660 else if ((cell
->type
== ID($logic_or
))) {
662 a_expr
= "neq(" + a_expr
+ ", UInt(0))";
663 b_expr
= "neq(" + b_expr
+ ", UInt(0))";
667 else if ((cell
->type
== ID($pow
))) {
668 if (a_sig
.is_fully_const() && a_sig
.as_int() == 2) {
669 // We'll convert this to a shift. To simplify things, change the a_expr to "1"
670 // so we can use b_expr directly as a shift amount.
671 // Only support 2 ** N (i.e., shift left)
672 // FIRRTL will widen the result (y) by the amount of the shift.
673 // We'll need to offset this by extracting the un-widened portion as Verilog would do.
674 a_expr
= firrtl_is_signed
? "SInt(1)" : "UInt(1)";
675 extract_y_bits
= true;
676 // Is the shift amount constant?
677 auto b_sig
= cell
->getPort(ID::B
);
678 if (b_sig
.is_fully_const()) {
680 int shiftAmount
= b_sig
.as_int();
681 if (shiftAmount
< 0) {
682 log_error("Negative power exponent - %d: %s.%s\n", shiftAmount
, log_id(module
), log_id(cell
));
684 b_expr
= std::to_string(shiftAmount
);
685 firrtl_width
= a_width
+ shiftAmount
;
688 // Convert from FIRRTL left shift semantics.
689 b_expr
= gen_dshl(b_expr
, b_width
);
690 firrtl_width
= a_width
+ (1 << b_width
) - 1;
693 log_error("Non power 2: %s.%s\n", log_id(module
), log_id(cell
));
697 if (!cell
->parameters
.at(ID::B_SIGNED
).as_bool()) {
698 b_expr
= "asUInt(" + b_expr
+ ")";
702 // Deal with $xnor == ~^ (not xor)
703 if (primop
== "xnor") {
704 expr
= stringf("not(xor(%s, %s))", a_expr
.c_str(), b_expr
.c_str());
706 expr
= stringf("%s(%s, %s)", primop
.c_str(), a_expr
.c_str(), b_expr
.c_str());
709 // Deal with FIRRTL's "shift widens" semantics, or the need to widen the FIRRTL result.
710 // If the operation is signed, the FIRRTL width will be 1 one bit larger.
711 if (extract_y_bits
) {
712 expr
= stringf("bits(%s, %d, 0)", expr
.c_str(), y_width
- 1);
713 } else if (firrtl_is_signed
&& (firrtl_width
+ 1) < y_width
) {
714 expr
= stringf("pad(%s, %d)", expr
.c_str(), y_width
);
717 if ((firrtl_is_signed
&& !always_uint
))
718 expr
= stringf("asUInt(%s)", expr
.c_str());
720 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
721 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
726 if (cell
->type
.in(ID($mux
)))
728 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
729 string a_expr
= make_expr(cell
->getPort(ID::A
));
730 string b_expr
= make_expr(cell
->getPort(ID::B
));
731 string s_expr
= make_expr(cell
->getPort(ID::S
));
732 wire_decls
.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id
.c_str(), width
, cellFileinfo
.c_str()));
734 string expr
= stringf("mux(%s, %s, %s)", s_expr
.c_str(), b_expr
.c_str(), a_expr
.c_str());
736 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
737 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
742 if (cell
->type
.in(ID($mem
)))
744 string mem_id
= make_id(cell
->name
);
745 int abits
= cell
->parameters
.at(ID::ABITS
).as_int();
746 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
747 int size
= cell
->parameters
.at(ID::SIZE
).as_int();
748 memory
m(cell
, mem_id
, abits
, size
, width
);
749 int rd_ports
= cell
->parameters
.at(ID::RD_PORTS
).as_int();
750 int wr_ports
= cell
->parameters
.at(ID::WR_PORTS
).as_int();
752 Const initdata
= cell
->parameters
.at(ID::INIT
);
753 for (State bit
: initdata
.bits
)
754 if (bit
!= State::Sx
)
755 log_error("Memory with initialization data: %s.%s\n", log_id(module
), log_id(cell
));
757 Const rd_clk_enable
= cell
->parameters
.at(ID::RD_CLK_ENABLE
);
758 Const wr_clk_enable
= cell
->parameters
.at(ID::WR_CLK_ENABLE
);
759 Const wr_clk_polarity
= cell
->parameters
.at(ID::WR_CLK_POLARITY
);
761 int offset
= cell
->parameters
.at(ID::OFFSET
).as_int();
763 log_error("Memory with nonzero offset: %s.%s\n", log_id(module
), log_id(cell
));
765 for (int i
= 0; i
< rd_ports
; i
++)
767 if (rd_clk_enable
[i
] != State::S0
)
768 log_error("Clocked read port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
770 SigSpec addr_sig
= cell
->getPort(ID::RD_ADDR
).extract(i
*abits
, abits
);
771 SigSpec data_sig
= cell
->getPort(ID::RD_DATA
).extract(i
*width
, width
);
772 string addr_expr
= make_expr(addr_sig
);
773 string
name(stringf("%s.r%d", m
.name
.c_str(), i
));
774 bool clk_enable
= false;
775 bool clk_parity
= true;
776 bool transparency
= false;
777 SigSpec ena_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
778 SigSpec clk_sig
= RTLIL::SigSpec(RTLIL::State::S0
, 1);
779 read_port
rp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, ena_sig
, addr_sig
);
780 m
.add_memory_read_port(rp
);
781 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
782 register_reverse_wire_map(stringf("%s.data", name
.c_str()), data_sig
);
785 for (int i
= 0; i
< wr_ports
; i
++)
787 if (wr_clk_enable
[i
] != State::S1
)
788 log_error("Unclocked write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
790 if (wr_clk_polarity
[i
] != State::S1
)
791 log_error("Negedge write port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
793 string
name(stringf("%s.w%d", m
.name
.c_str(), i
));
794 bool clk_enable
= true;
795 bool clk_parity
= true;
796 bool transparency
= false;
797 SigSpec addr_sig
=cell
->getPort(ID::WR_ADDR
).extract(i
*abits
, abits
);
798 string addr_expr
= make_expr(addr_sig
);
799 SigSpec data_sig
=cell
->getPort(ID::WR_DATA
).extract(i
*width
, width
);
800 string data_expr
= make_expr(data_sig
);
801 SigSpec clk_sig
= cell
->getPort(ID::WR_CLK
).extract(i
);
802 string clk_expr
= make_expr(clk_sig
);
804 SigSpec wen_sig
= cell
->getPort(ID::WR_EN
).extract(i
*width
, width
);
805 string wen_expr
= make_expr(wen_sig
[0]);
807 for (int i
= 1; i
< GetSize(wen_sig
); i
++)
808 if (wen_sig
[0] != wen_sig
[i
])
809 log_error("Complex write enable on port %d on memory %s.%s.\n", i
, log_id(module
), log_id(cell
));
811 SigSpec mask_sig
= RTLIL::SigSpec(RTLIL::State::S1
, 1);
812 write_port
wp(name
, clk_enable
, clk_parity
, transparency
, clk_sig
, wen_sig
[0], addr_sig
, mask_sig
);
813 m
.add_memory_write_port(wp
);
814 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), name
.c_str(), data_expr
.c_str()));
815 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
821 if (cell
->type
.in(ID($memwr
), ID($memrd
), ID($meminit
)))
823 std::string cell_type
= fid(cell
->type
);
824 std::string mem_id
= make_id(cell
->parameters
[ID::MEMID
].decode_string());
825 int abits
= cell
->parameters
.at(ID::ABITS
).as_int();
826 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
827 memory
*mp
= nullptr;
828 if (cell
->type
== ID($meminit
) ) {
829 log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module
), log_id(cell
), mem_id
.c_str());
831 // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
832 auto addrSig
= cell
->getPort(ID::ADDR
);
833 auto dataSig
= cell
->getPort(ID::DATA
);
834 auto enableSig
= cell
->getPort(ID::EN
);
835 auto clockSig
= cell
->getPort(ID::CLK
);
836 Const clk_enable
= cell
->parameters
.at(ID::CLK_ENABLE
);
837 Const clk_polarity
= cell
->parameters
.at(ID::CLK_POLARITY
);
839 // Do we already have an entry for this memory?
840 if (memories
.count(mem_id
) == 0) {
841 memory
m(cell
, mem_id
, abits
, 0, width
);
844 mp
= &memories
.at(mem_id
);
846 bool transparency
= false;
847 string data_expr
= make_expr(dataSig
);
848 if (cell
->type
.in(ID($memwr
))) {
849 portNum
= (int) mp
->write_ports
.size();
850 write_port
wp(stringf("%s.w%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
, dataSig
);
851 mp
->add_memory_write_port(wp
);
852 cell_exprs
.push_back(stringf("%s%s.data <= %s\n", indent
.c_str(), wp
.name
.c_str(), data_expr
.c_str()));
853 cell_exprs
.push_back(wp
.gen_write(indent
.c_str()));
854 } else if (cell
->type
.in(ID($memrd
))) {
855 portNum
= (int) mp
->read_ports
.size();
856 read_port
rp(stringf("%s.r%d", mem_id
.c_str(), portNum
), clk_enable
.as_bool(), clk_polarity
.as_bool(), transparency
, clockSig
, enableSig
, addrSig
);
857 mp
->add_memory_read_port(rp
);
858 cell_exprs
.push_back(rp
.gen_read(indent
.c_str()));
859 register_reverse_wire_map(stringf("%s.data", rp
.name
.c_str()), dataSig
);
865 if (cell
->type
.in(ID($dff
)))
867 bool clkpol
= cell
->parameters
.at(ID::CLK_POLARITY
).as_bool();
869 log_error("Negative edge clock on FF %s.%s.\n", log_id(module
), log_id(cell
));
871 int width
= cell
->parameters
.at(ID::WIDTH
).as_int();
872 string expr
= make_expr(cell
->getPort(ID::D
));
873 string clk_expr
= "asClock(" + make_expr(cell
->getPort(ID::CLK
)) + ")";
875 wire_decls
.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id
.c_str(), width
, clk_expr
.c_str(), cellFileinfo
.c_str()));
877 cell_exprs
.push_back(stringf(" %s <= %s %s\n", y_id
.c_str(), expr
.c_str(), cellFileinfo
.c_str()));
878 register_reverse_wire_map(y_id
, cell
->getPort(ID::Q
));
883 // This may be a parameterized module - paramod.
884 if (cell
->type
.begins_with("$paramod"))
886 process_instance(cell
, wire_exprs
);
889 if (cell
->type
== ID($shiftx
)) {
890 // assign y = a[b +: y_width];
891 // We'll extract the correct bits as part of the primop.
893 string a_expr
= make_expr(cell
->getPort(ID::A
));
894 // Get the initial bit selector
895 string b_expr
= make_expr(cell
->getPort(ID::B
));
896 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
898 if (cell
->getParam(ID::B_SIGNED
).as_bool()) {
899 // Use validif to constrain the selection (test the sign bit)
900 auto b_string
= b_expr
.c_str();
901 int b_sign
= cell
->parameters
.at(ID::B_WIDTH
).as_int() - 1;
902 b_expr
= stringf("validif(not(bits(%s, %d, %d)), %s)", b_string
, b_sign
, b_sign
, b_string
);
904 string expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_expr
.c_str());
906 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
907 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
910 if (cell
->type
== ID($shift
)) {
911 // assign y = a >> b;
912 // where b may be negative
914 string a_expr
= make_expr(cell
->getPort(ID::A
));
915 string b_expr
= make_expr(cell
->getPort(ID::B
));
916 auto b_string
= b_expr
.c_str();
918 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
920 if (cell
->getParam(ID::B_SIGNED
).as_bool()) {
921 // We generate a left or right shift based on the sign of b.
922 std::string dshl
= stringf("bits(dshl(%s, %s), 0, %d)", a_expr
.c_str(), gen_dshl(b_expr
, b_width
).c_str(), y_width
);
923 std::string dshr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
924 expr
= stringf("mux(%s < 0, %s, %s)",
930 expr
= stringf("dshr(%s, %s)", a_expr
.c_str(), b_string
);
932 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
933 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
936 if (cell
->type
== ID($pos
)) {
939 string a_expr
= make_expr(cell
->getPort(ID::A
));
940 // Verilog appears to treat the result as signed, so if the result is wider than "A",
942 if (a_width
< y_width
) {
943 a_expr
= stringf("pad(%s, %d)", a_expr
.c_str(), y_width
);
945 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
946 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), a_expr
.c_str()));
947 register_reverse_wire_map(y_id
, cell
->getPort(ID::Y
));
950 log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell
->type
), log_id(module
), log_id(cell
));
953 for (auto conn
: module
->connections())
955 string y_id
= next_id();
956 int y_width
= GetSize(conn
.first
);
957 string expr
= make_expr(conn
.second
);
959 wire_decls
.push_back(stringf(" wire %s: UInt<%d>\n", y_id
.c_str(), y_width
));
960 cell_exprs
.push_back(stringf(" %s <= %s\n", y_id
.c_str(), expr
.c_str()));
961 register_reverse_wire_map(y_id
, conn
.first
);
964 for (auto wire
: module
->wires())
967 std::string wireFileinfo
= getFileinfo(wire
);
969 if (wire
->port_input
)
973 bool is_valid
= false;
974 bool make_unconn_id
= false;
976 while (cursor
< wire
->width
)
981 SigBit
start_bit(wire
, cursor
);
983 if (reverse_wire_map
.count(start_bit
))
985 pair
<string
, int> start_map
= reverse_wire_map
.at(start_bit
);
987 while (cursor
+chunk_width
< wire
->width
)
989 SigBit
stop_bit(wire
, cursor
+chunk_width
);
991 if (reverse_wire_map
.count(stop_bit
) == 0)
994 pair
<string
, int> stop_map
= reverse_wire_map
.at(stop_bit
);
995 stop_map
.second
-= chunk_width
;
997 if (start_map
!= stop_map
)
1003 new_expr
= stringf("bits(%s, %d, %d)", start_map
.first
.c_str(),
1004 start_map
.second
+ chunk_width
- 1, start_map
.second
);
1009 if (unconn_id
.empty()) {
1010 unconn_id
= next_id();
1011 make_unconn_id
= true;
1013 new_expr
= unconn_id
;
1019 expr
= "cat(" + new_expr
+ ", " + expr
+ ")";
1021 cursor
+= chunk_width
;
1025 if (make_unconn_id
) {
1026 wire_decls
.push_back(stringf(" wire %s: UInt<1> %s\n", unconn_id
.c_str(), wireFileinfo
.c_str()));
1027 // `invalid` is a firrtl construction for simulation so we will not
1028 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1029 // a specific line of verilog code.
1030 wire_decls
.push_back(stringf(" %s is invalid\n", unconn_id
.c_str()));
1032 wire_exprs
.push_back(stringf(" %s <= %s %s\n", make_id(wire
->name
), expr
.c_str(), wireFileinfo
.c_str()));
1034 if (make_unconn_id
) {
1037 // `invalid` is a firrtl construction for simulation so we will not
1038 // tag it with a @[fileinfo] tag as it doesn't directly correspond to
1039 // a specific line of verilog code.
1040 wire_decls
.push_back(stringf(" %s is invalid\n", make_id(wire
->name
)));
1044 for (auto str
: port_decls
)
1049 for (auto str
: wire_decls
)
1054 // If we have any memory definitions, output them.
1055 for (auto kv
: memories
) {
1056 memory
&m
= kv
.second
;
1057 f
<< stringf(" mem %s:\n", m
.name
.c_str());
1058 f
<< stringf(" data-type => UInt<%d>\n", m
.width
);
1059 f
<< stringf(" depth => %d\n", m
.size
);
1060 for (int i
= 0; i
< (int) m
.read_ports
.size(); i
+= 1) {
1061 f
<< stringf(" reader => r%d\n", i
);
1063 for (int i
= 0; i
< (int) m
.write_ports
.size(); i
+= 1) {
1064 f
<< stringf(" writer => w%d\n", i
);
1066 f
<< stringf(" read-latency => %d\n", m
.read_latency
);
1067 f
<< stringf(" write-latency => %d\n", m
.write_latency
);
1068 f
<< stringf(" read-under-write => undefined\n");
1072 for (auto str
: cell_exprs
)
1077 for (auto str
: wire_exprs
)
1082 struct FirrtlBackend
: public Backend
{
1083 FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
1084 void help() YS_OVERRIDE
1086 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1088 log(" write_firrtl [options] [filename]\n");
1090 log("Write a FIRRTL netlist of the current design.\n");
1091 log("The following commands are executed by this command:\n");
1095 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1097 size_t argidx
= args
.size(); // We aren't expecting any arguments.
1099 // If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
1100 if (filename
== "") {
1101 if (argidx
> 0 && args
[argidx
- 1][0] != '-') {
1102 // extra_args and friends need to see this argument.
1104 filename
= args
[argidx
];
1107 extra_args(f
, filename
, args
, argidx
);
1109 if (!design
->full_selection())
1110 log_cmd_error("This command only operates on fully selected designs!\n");
1112 log_header(design
, "Executing FIRRTL backend.\n");
1115 Pass::call(design
, stringf("pmuxtree"));
1120 // Get the top module, or a reasonable facsimile - we need something for the circuit name.
1121 Module
*top
= design
->top_module();
1122 Module
*last
= nullptr;
1123 // Generate module and wire names.
1124 for (auto module
: design
->modules()) {
1125 make_id(module
->name
);
1127 if (top
== nullptr && module
->get_bool_attribute(ID::top
)) {
1130 for (auto wire
: module
->wires())
1132 make_id(wire
->name
);
1138 std::string circuitFileinfo
= getFileinfo(top
);
1139 *f
<< stringf("circuit %s: %s\n", make_id(top
->name
), circuitFileinfo
.c_str());
1141 for (auto module
: design
->modules())
1143 FirrtlWorker
worker(module
, *f
, design
);
1152 PRIVATE_NAMESPACE_END