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Progress in FIRRTL back-end
[yosys.git]
/
backends
/
firrtl
/
test.v
1
module test(input clk, signed input [7:0] a, b, x, output [15:0] s, d, y, z, u, q);
2
assign s = a+{b[6:2], 2'b1}, d = a-b, y = x, z[7:0] = s+d, z[15:8] = s-d;
3
always @(posedge clk) q <= s ^ d ^ x;
4
endmodule