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6a6974133b21879ba06efca8494bdd713051d125
[yosys.git] / backends / ilang / ilang_backend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * A very simple and straightforward backend for the RTLIL text
21 * representation (as understood by the 'ilang' frontend).
22 *
23 */
24
25 #include "ilang_backend.h"
26 #include "kernel/yosys.h"
27 #include <errno.h>
28
29 USING_YOSYS_NAMESPACE
30 using namespace ILANG_BACKEND;
31 YOSYS_NAMESPACE_BEGIN
32
33 void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
34 {
35 if (width < 0)
36 width = data.bits.size() - offset;
37 if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
38 if (width == 32 && autoint) {
39 int32_t val = 0;
40 for (int i = 0; i < width; i++) {
41 log_assert(offset+i < (int)data.bits.size());
42 switch (data.bits[offset+i]) {
43 case RTLIL::S0: break;
44 case RTLIL::S1: val |= 1 << i; break;
45 default: val = -1; break;
46 }
47 }
48 if (val >= 0) {
49 f << stringf("%d", val);
50 return;
51 }
52 }
53 f << stringf("%d'", width);
54 for (int i = offset+width-1; i >= offset; i--) {
55 log_assert(i < (int)data.bits.size());
56 switch (data.bits[i]) {
57 case RTLIL::S0: f << stringf("0"); break;
58 case RTLIL::S1: f << stringf("1"); break;
59 case RTLIL::Sx: f << stringf("x"); break;
60 case RTLIL::Sz: f << stringf("z"); break;
61 case RTLIL::Sa: f << stringf("-"); break;
62 case RTLIL::Sm: f << stringf("m"); break;
63 }
64 }
65 } else {
66 f << stringf("\"");
67 std::string str = data.decode_string();
68 for (size_t i = 0; i < str.size(); i++) {
69 if (str[i] == '\n')
70 f << stringf("\\n");
71 else if (str[i] == '\t')
72 f << stringf("\\t");
73 else if (str[i] < 32)
74 f << stringf("\\%03o", str[i]);
75 else if (str[i] == '"')
76 f << stringf("\\\"");
77 else if (str[i] == '\\')
78 f << stringf("\\\\");
79 else
80 f << str[i];
81 }
82 f << stringf("\"");
83 }
84 }
85
86 void ILANG_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint)
87 {
88 if (chunk.wire == NULL) {
89 dump_const(f, chunk.data, chunk.width, chunk.offset, autoint);
90 } else {
91 if (chunk.width == chunk.wire->width && chunk.offset == 0)
92 f << stringf("%s", chunk.wire->name.c_str());
93 else if (chunk.width == 1)
94 f << stringf("%s [%d]", chunk.wire->name.c_str(), chunk.offset);
95 else
96 f << stringf("%s [%d:%d]", chunk.wire->name.c_str(), chunk.offset+chunk.width-1, chunk.offset);
97 }
98 }
99
100 void ILANG_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint)
101 {
102 if (sig.is_chunk()) {
103 dump_sigchunk(f, sig.as_chunk(), autoint);
104 } else {
105 f << stringf("{ ");
106 for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
107 dump_sigchunk(f, *it, false);
108 f << stringf(" ");
109 }
110 f << stringf("}");
111 }
112 }
113
114 void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
115 {
116 for (auto &it : wire->attributes) {
117 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
118 dump_const(f, it.second);
119 f << stringf("\n");
120 }
121 f << stringf("%s" "wire ", indent.c_str());
122 if (wire->width != 1)
123 f << stringf("width %d ", wire->width);
124 if (wire->upto)
125 f << stringf("upto ");
126 if (wire->start_offset != 0)
127 f << stringf("offset %d ", wire->start_offset);
128 if (wire->port_input && !wire->port_output)
129 f << stringf("input %d ", wire->port_id);
130 if (!wire->port_input && wire->port_output)
131 f << stringf("output %d ", wire->port_id);
132 if (wire->port_input && wire->port_output)
133 f << stringf("inout %d ", wire->port_id);
134 f << stringf("%s\n", wire->name.c_str());
135 }
136
137 void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory)
138 {
139 for (auto &it : memory->attributes) {
140 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
141 dump_const(f, it.second);
142 f << stringf("\n");
143 }
144 f << stringf("%s" "memory ", indent.c_str());
145 if (memory->width != 1)
146 f << stringf("width %d ", memory->width);
147 if (memory->size != 0)
148 f << stringf("size %d ", memory->size);
149 if (memory->start_offset != 0)
150 f << stringf("offset %d ", memory->start_offset);
151 f << stringf("%s\n", memory->name.c_str());
152 }
153
154 void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
155 {
156 for (auto &it : cell->attributes) {
157 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
158 dump_const(f, it.second);
159 f << stringf("\n");
160 }
161 f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
162 for (auto &it : cell->parameters) {
163 f << stringf("%s parameter%s %s ", indent.c_str(), (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", it.first.c_str());
164 dump_const(f, it.second);
165 f << stringf("\n");
166 }
167 for (auto &it : cell->connections()) {
168 f << stringf("%s connect %s ", indent.c_str(), it.first.c_str());
169 dump_sigspec(f, it.second);
170 f << stringf("\n");
171 }
172 f << stringf("%s" "end\n", indent.c_str());
173 }
174
175 void ILANG_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
176 {
177 for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
178 {
179 f << stringf("%s" "assign ", indent.c_str());
180 dump_sigspec(f, it->first);
181 f << stringf(" ");
182 dump_sigspec(f, it->second);
183 f << stringf("\n");
184 }
185
186 for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
187 dump_proc_switch(f, indent, *it);
188 }
189
190 void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw)
191 {
192 for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) {
193 f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
194 dump_const(f, it->second);
195 f << stringf("\n");
196 }
197
198 f << stringf("%s" "switch ", indent.c_str());
199 dump_sigspec(f, sw->signal);
200 f << stringf("\n");
201
202 for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
203 {
204 f << stringf("%s case ", indent.c_str());
205 for (size_t i = 0; i < (*it)->compare.size(); i++) {
206 if (i > 0)
207 f << stringf(", ");
208 dump_sigspec(f, (*it)->compare[i]);
209 }
210 f << stringf("\n");
211
212 dump_proc_case_body(f, indent + " ", *it);
213 }
214
215 f << stringf("%s" "end\n", indent.c_str());
216 }
217
218 void ILANG_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy)
219 {
220 f << stringf("%s" "sync ", indent.c_str());
221 switch (sy->type) {
222 if (0) case RTLIL::ST0: f << stringf("low ");
223 if (0) case RTLIL::ST1: f << stringf("high ");
224 if (0) case RTLIL::STp: f << stringf("posedge ");
225 if (0) case RTLIL::STn: f << stringf("negedge ");
226 if (0) case RTLIL::STe: f << stringf("edge ");
227 dump_sigspec(f, sy->signal);
228 f << stringf("\n");
229 break;
230 case RTLIL::STa: f << stringf("always\n"); break;
231 case RTLIL::STi: f << stringf("init\n"); break;
232 }
233
234 for (auto it = sy->actions.begin(); it != sy->actions.end(); ++it) {
235 f << stringf("%s update ", indent.c_str());
236 dump_sigspec(f, it->first);
237 f << stringf(" ");
238 dump_sigspec(f, it->second);
239 f << stringf("\n");
240 }
241 }
242
243 void ILANG_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc)
244 {
245 for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) {
246 f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
247 dump_const(f, it->second);
248 f << stringf("\n");
249 }
250 f << stringf("%s" "process %s\n", indent.c_str(), proc->name.c_str());
251 dump_proc_case_body(f, indent + " ", &proc->root_case);
252 for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
253 dump_proc_sync(f, indent + " ", *it);
254 f << stringf("%s" "end\n", indent.c_str());
255 }
256
257 void ILANG_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
258 {
259 f << stringf("%s" "connect ", indent.c_str());
260 dump_sigspec(f, left);
261 f << stringf(" ");
262 dump_sigspec(f, right);
263 f << stringf("\n");
264 }
265
266 void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
267 {
268 bool print_header = flag_m || design->selected_whole_module(module->name);
269 bool print_body = !flag_n || !design->selected_whole_module(module->name);
270
271 if (print_header)
272 {
273 for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) {
274 f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
275 dump_const(f, it->second);
276 f << stringf("\n");
277 }
278
279 f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
280 }
281
282 if (print_body)
283 {
284 for (auto it : module->wires())
285 if (!only_selected || design->selected(module, it)) {
286 if (only_selected)
287 f << stringf("\n");
288 dump_wire(f, indent + " ", it);
289 }
290
291 for (auto it : module->memories)
292 if (!only_selected || design->selected(module, it.second)) {
293 if (only_selected)
294 f << stringf("\n");
295 dump_memory(f, indent + " ", it.second);
296 }
297
298 for (auto it : module->cells())
299 if (!only_selected || design->selected(module, it)) {
300 if (only_selected)
301 f << stringf("\n");
302 dump_cell(f, indent + " ", it);
303 }
304
305 for (auto it : module->processes)
306 if (!only_selected || design->selected(module, it.second)) {
307 if (only_selected)
308 f << stringf("\n");
309 dump_proc(f, indent + " ", it.second);
310 }
311
312 bool first_conn_line = true;
313 for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
314 bool show_conn = !only_selected;
315 if (only_selected) {
316 RTLIL::SigSpec sigs = it->first;
317 sigs.append(it->second);
318 for (auto &c : sigs.chunks()) {
319 if (c.wire == NULL || !design->selected(module, c.wire))
320 continue;
321 show_conn = true;
322 }
323 }
324 if (show_conn) {
325 if (only_selected && first_conn_line)
326 f << stringf("\n");
327 dump_conn(f, indent + " ", it->first, it->second);
328 first_conn_line = false;
329 }
330 }
331 }
332
333 if (print_header)
334 f << stringf("%s" "end\n", indent.c_str());
335 }
336
337 void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
338 {
339 int init_autoidx = autoidx;
340
341 if (!flag_m) {
342 int count_selected_mods = 0;
343 for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
344 if (design->selected_whole_module(it->first))
345 flag_m = true;
346 if (design->selected(it->second))
347 count_selected_mods++;
348 }
349 if (count_selected_mods > 1)
350 flag_m = true;
351 }
352
353 if (!only_selected || flag_m) {
354 if (only_selected)
355 f << stringf("\n");
356 f << stringf("autoidx %d\n", autoidx);
357 }
358
359 for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
360 if (!only_selected || design->selected(it->second)) {
361 if (only_selected)
362 f << stringf("\n");
363 dump_module(f, "", it->second, design, only_selected, flag_m, flag_n);
364 }
365 }
366
367 log_assert(init_autoidx == autoidx);
368 }
369
370 YOSYS_NAMESPACE_END
371 PRIVATE_NAMESPACE_BEGIN
372
373 struct IlangBackend : public Backend {
374 IlangBackend() : Backend("ilang", "write design to ilang file") { }
375 virtual void help()
376 {
377 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
378 log("\n");
379 log(" write_ilang [filename]\n");
380 log("\n");
381 log("Write the current design to an 'ilang' file. (ilang is a text representation\n");
382 log("of a design in yosys's internal format.)\n");
383 log("\n");
384 log(" -selected\n");
385 log(" only write selected parts of the design.\n");
386 log("\n");
387 }
388 virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
389 {
390 bool selected = false;
391
392 log_header("Executing ILANG backend.\n");
393
394 size_t argidx;
395 for (argidx = 1; argidx < args.size(); argidx++) {
396 std::string arg = args[argidx];
397 if (arg == "-selected") {
398 selected = true;
399 continue;
400 }
401 break;
402 }
403 extra_args(f, filename, args, argidx);
404
405 design->sort();
406
407 log("Output filename: %s\n", filename.c_str());
408 *f << stringf("# Generated by %s\n", yosys_version_str);
409 ILANG_BACKEND::dump_design(*f, design, selected, true, false);
410 }
411 } IlangBackend;
412
413 struct DumpPass : public Pass {
414 DumpPass() : Pass("dump", "print parts of the design in ilang format") { }
415 virtual void help()
416 {
417 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
418 log("\n");
419 log(" dump [options] [selection]\n");
420 log("\n");
421 log("Write the selected parts of the design to the console or specified file in\n");
422 log("ilang format.\n");
423 log("\n");
424 log(" -m\n");
425 log(" also dump the module headers, even if only parts of a single\n");
426 log(" module is selected\n");
427 log("\n");
428 log(" -n\n");
429 log(" only dump the module headers if the entire module is selected\n");
430 log("\n");
431 log(" -outfile <filename>\n");
432 log(" write to the specified file.\n");
433 log("\n");
434 log(" -append <filename>\n");
435 log(" like -outfile but append instead of overwrite\n");
436 log("\n");
437 }
438 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
439 {
440 std::string filename;
441 bool flag_m = false, flag_n = false, append = false;
442
443 size_t argidx;
444 for (argidx = 1; argidx < args.size(); argidx++)
445 {
446 std::string arg = args[argidx];
447 if (arg == "-outfile" && argidx+1 < args.size()) {
448 filename = args[++argidx];
449 append = false;
450 continue;
451 }
452 if (arg == "-append" && argidx+1 < args.size()) {
453 filename = args[++argidx];
454 append = true;
455 continue;
456 }
457 if (arg == "-m") {
458 flag_m = true;
459 continue;
460 }
461 if (arg == "-n") {
462 flag_n = true;
463 continue;
464 }
465 break;
466 }
467 extra_args(args, argidx, design);
468
469 std::ostream *f;
470 std::stringstream buf;
471
472 if (!filename.empty()) {
473 std::ofstream *ff = new std::ofstream;
474 ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
475 if (ff->fail()) {
476 delete ff;
477 log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
478 }
479 f = ff;
480 } else {
481 f = &buf;
482 }
483
484 ILANG_BACKEND::dump_design(*f, design, true, flag_m, flag_n);
485
486 if (!filename.empty()) {
487 delete f;
488 } else {
489 log("%s", buf.str().c_str());
490 }
491 }
492 } DumpPass;
493
494 PRIVATE_NAMESPACE_END