backends/ilang/ilang_backend.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  A very simple and straightforward backend for the RTLIL text
  21  *  representation (as understood by the 'ilang' frontend).
  22  *
  23  */
  24
  25 #include "ilang_backend.h"
  26 #include "kernel/yosys.h"
  27 #include <errno.h>
  28
  29 USING_YOSYS_NAMESPACE
  30 using namespace ILANG_BACKEND;
  31 YOSYS_NAMESPACE_BEGIN
  32
  33 void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
  34 {
  35         if (width < 0)
  36                 width = data.bits.size() - offset;
  37         if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
  38                 if (width == 32 && autoint) {
  39                         int32_t val = 0;
  40                         for (int i = 0; i < width; i++) {
  41                                 log_assert(offset+i < (int)data.bits.size());
  42                                 switch (data.bits[offset+i]) {
  43                                 case RTLIL::S0: break;
  44                                 case RTLIL::S1: val |= 1 << i; break;
  45                                 default: val = -1; break;
  46                                 }
  47                         }
  48                         if (val >= 0) {
  49                                 f << stringf("%d", val);
  50                                 return;
  51                         }
  52                 }
  53                 f << stringf("%d'", width);
  54                 for (int i = offset+width-1; i >= offset; i--) {
  55                         log_assert(i < (int)data.bits.size());
  56                         switch (data.bits[i]) {
  57                         case RTLIL::S0: f << stringf("0"); break;
  58                         case RTLIL::S1: f << stringf("1"); break;
  59                         case RTLIL::Sx: f << stringf("x"); break;
  60                         case RTLIL::Sz: f << stringf("z"); break;
  61                         case RTLIL::Sa: f << stringf("-"); break;
  62                         case RTLIL::Sm: f << stringf("m"); break;
  63                         }
  64                 }
  65         } else {
  66                 f << stringf("\"");
  67                 std::string str = data.decode_string();
  68                 for (size_t i = 0; i < str.size(); i++) {
  69                         if (str[i] == '\n')
  70                                 f << stringf("\\n");
  71                         else if (str[i] == '\t')
  72                                 f << stringf("\\t");
  73                         else if (str[i] < 32)
  74                                 f << stringf("\\%03o", str[i]);
  75                         else if (str[i] == '"')
  76                                 f << stringf("\\\"");
  77                         else if (str[i] == '\\')
  78                                 f << stringf("\\\\");
  79                         else
  80                                 f << str[i];
  81                 }
  82                 f << stringf("\"");
  83         }
  84 }
  85
  86 void ILANG_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint)
  87 {
  88         if (chunk.wire == NULL) {
  89                 dump_const(f, chunk.data, chunk.width, chunk.offset, autoint);
  90         } else {
  91                 if (chunk.width == chunk.wire->width && chunk.offset == 0)
  92                         f << stringf("%s", chunk.wire->name.c_str());
  93                 else if (chunk.width == 1)
  94                         f << stringf("%s [%d]", chunk.wire->name.c_str(), chunk.offset);
  95                 else
  96                         f << stringf("%s [%d:%d]", chunk.wire->name.c_str(), chunk.offset+chunk.width-1, chunk.offset);
  97         }
  98 }
  99
 100 void ILANG_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint)
 101 {
 102         if (sig.is_chunk()) {
 103                 dump_sigchunk(f, sig.as_chunk(), autoint);
 104         } else {
 105                 f << stringf("{ ");
 106                 for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
 107                         dump_sigchunk(f, *it, false);
 108                         f << stringf(" ");
 109                 }
 110                 f << stringf("}");
 111         }
 112 }
 113
 114 void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
 115 {
 116         for (auto &it : wire->attributes) {
 117                 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
 118                 dump_const(f, it.second);
 119                 f << stringf("\n");
 120         }
 121         f << stringf("%s" "wire ", indent.c_str());
 122         if (wire->width != 1)
 123                 f << stringf("width %d ", wire->width);
 124         if (wire->upto)
 125                 f << stringf("upto ");
 126         if (wire->start_offset != 0)
 127                 f << stringf("offset %d ", wire->start_offset);
 128         if (wire->port_input && !wire->port_output)
 129                 f << stringf("input %d ", wire->port_id);
 130         if (!wire->port_input && wire->port_output)
 131                 f << stringf("output %d ", wire->port_id);
 132         if (wire->port_input && wire->port_output)
 133                 f << stringf("inout %d ", wire->port_id);
 134         f << stringf("%s\n", wire->name.c_str());
 135 }
 136
 137 void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory)
 138 {
 139         for (auto &it : memory->attributes) {
 140                 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
 141                 dump_const(f, it.second);
 142                 f << stringf("\n");
 143         }
 144         f << stringf("%s" "memory ", indent.c_str());
 145         if (memory->width != 1)
 146                 f << stringf("width %d ", memory->width);
 147         if (memory->size != 0)
 148                 f << stringf("size %d ", memory->size);
 149         if (memory->start_offset != 0)
 150                 f << stringf("offset %d ", memory->start_offset);
 151         f << stringf("%s\n", memory->name.c_str());
 152 }
 153
 154 void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
 155 {
 156         for (auto &it : cell->attributes) {
 157                 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
 158                 dump_const(f, it.second);
 159                 f << stringf("\n");
 160         }
 161         f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
 162         for (auto &it : cell->parameters) {
 163                 f << stringf("%s  parameter%s%s %s ", indent.c_str(),
 164                                 (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
 165                                 (it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",
 166                                 it.first.c_str());
 167                 dump_const(f, it.second);
 168                 f << stringf("\n");
 169         }
 170         for (auto &it : cell->connections()) {
 171                 f << stringf("%s  connect %s ", indent.c_str(), it.first.c_str());
 172                 dump_sigspec(f, it.second);
 173                 f << stringf("\n");
 174         }
 175         f << stringf("%s" "end\n", indent.c_str());
 176 }
 177
 178 void ILANG_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
 179 {
 180         for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
 181         {
 182                 f << stringf("%s" "assign ", indent.c_str());
 183                 dump_sigspec(f, it->first);
 184                 f << stringf(" ");
 185                 dump_sigspec(f, it->second);
 186                 f << stringf("\n");
 187         }
 188
 189         for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
 190                 dump_proc_switch(f, indent, *it);
 191 }
 192
 193 void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw)
 194 {
 195         for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) {
 196                 f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
 197                 dump_const(f, it->second);
 198                 f << stringf("\n");
 199         }
 200
 201         f << stringf("%s" "switch ", indent.c_str());
 202         dump_sigspec(f, sw->signal);
 203         f << stringf("\n");
 204
 205         for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
 206         {
 207                 f << stringf("%s  case ", indent.c_str());
 208                 for (size_t i = 0; i < (*it)->compare.size(); i++) {
 209                         if (i > 0)
 210                                 f << stringf(" , ");
 211                         dump_sigspec(f, (*it)->compare[i]);
 212                 }
 213                 f << stringf("\n");
 214
 215                 dump_proc_case_body(f, indent + "    ", *it);
 216         }
 217
 218         f << stringf("%s" "end\n", indent.c_str());
 219 }
 220
 221 void ILANG_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy)
 222 {
 223         f << stringf("%s" "sync ", indent.c_str());
 224         switch (sy->type) {
 225         case RTLIL::ST0: f << stringf("low ");
 226         if (0) case RTLIL::ST1: f << stringf("high ");
 227         if (0) case RTLIL::STp: f << stringf("posedge ");
 228         if (0) case RTLIL::STn: f << stringf("negedge ");
 229         if (0) case RTLIL::STe: f << stringf("edge ");
 230                 dump_sigspec(f, sy->signal);
 231                 f << stringf("\n");
 232                 break;
 233         case RTLIL::STa: f << stringf("always\n"); break;
 234         case RTLIL::STg: f << stringf("global\n"); break;
 235         case RTLIL::STi: f << stringf("init\n"); break;
 236         }
 237
 238         for (auto it = sy->actions.begin(); it != sy->actions.end(); ++it) {
 239                 f << stringf("%s  update ", indent.c_str());
 240                 dump_sigspec(f, it->first);
 241                 f << stringf(" ");
 242                 dump_sigspec(f, it->second);
 243                 f << stringf("\n");
 244         }
 245 }
 246
 247 void ILANG_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc)
 248 {
 249         for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) {
 250                 f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
 251                 dump_const(f, it->second);
 252                 f << stringf("\n");
 253         }
 254         f << stringf("%s" "process %s\n", indent.c_str(), proc->name.c_str());
 255         dump_proc_case_body(f, indent + "  ", &proc->root_case);
 256         for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
 257                 dump_proc_sync(f, indent + "  ", *it);
 258         f << stringf("%s" "end\n", indent.c_str());
 259 }
 260
 261 void ILANG_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 262 {
 263         f << stringf("%s" "connect ", indent.c_str());
 264         dump_sigspec(f, left);
 265         f << stringf(" ");
 266         dump_sigspec(f, right);
 267         f << stringf("\n");
 268 }
 269
 270 void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
 271 {
 272         bool print_header = flag_m || design->selected_whole_module(module->name);
 273         bool print_body = !flag_n || !design->selected_whole_module(module->name);
 274
 275         if (print_header)
 276         {
 277                 for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) {
 278                         f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
 279                         dump_const(f, it->second);
 280                         f << stringf("\n");
 281                 }
 282
 283                 f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
 284
 285                 if (!module->avail_parameters.empty()) {
 286                         if (only_selected)
 287                                 f << stringf("\n");
 288                         for (auto &p : module->avail_parameters)
 289                                 f << stringf("%s" "  parameter %s\n", indent.c_str(), p.c_str());
 290                 }
 291         }
 292
 293         if (print_body)
 294         {
 295                 for (auto it : module->wires())
 296                         if (!only_selected || design->selected(module, it)) {
 297                                 if (only_selected)
 298                                         f << stringf("\n");
 299                                 dump_wire(f, indent + "  ", it);
 300                         }
 301
 302                 for (auto it : module->memories)
 303                         if (!only_selected || design->selected(module, it.second)) {
 304                                 if (only_selected)
 305                                         f << stringf("\n");
 306                                 dump_memory(f, indent + "  ", it.second);
 307                         }
 308
 309                 for (auto it : module->cells())
 310                         if (!only_selected || design->selected(module, it)) {
 311                                 if (only_selected)
 312                                         f << stringf("\n");
 313                                 dump_cell(f, indent + "  ", it);
 314                         }
 315
 316                 for (auto it : module->processes)
 317                         if (!only_selected || design->selected(module, it.second)) {
 318                                 if (only_selected)
 319                                         f << stringf("\n");
 320                                 dump_proc(f, indent + "  ", it.second);
 321                         }
 322
 323                 bool first_conn_line = true;
 324                 for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
 325                         bool show_conn = !only_selected;
 326                         if (only_selected) {
 327                                 RTLIL::SigSpec sigs = it->first;
 328                                 sigs.append(it->second);
 329                                 for (auto &c : sigs.chunks()) {
 330                                         if (c.wire == NULL || !design->selected(module, c.wire))
 331                                                 continue;
 332                                         show_conn = true;
 333                                 }
 334                         }
 335                         if (show_conn) {
 336                                 if (only_selected && first_conn_line)
 337                                         f << stringf("\n");
 338                                 dump_conn(f, indent + "  ", it->first, it->second);
 339                                 first_conn_line = false;
 340                         }
 341                 }
 342         }
 343
 344         if (print_header)
 345                 f << stringf("%s" "end\n", indent.c_str());
 346 }
 347
 348 void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
 349 {
 350 #ifndef NDEBUG
 351         int init_autoidx = autoidx;
 352 #endif
 353
 354         if (!flag_m) {
 355                 int count_selected_mods = 0;
 356                 for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
 357                         if (design->selected_whole_module(it->first))
 358                                 flag_m = true;
 359                         if (design->selected(it->second))
 360                                 count_selected_mods++;
 361                 }
 362                 if (count_selected_mods > 1)
 363                         flag_m = true;
 364         }
 365
 366         if (!only_selected || flag_m) {
 367                 if (only_selected)
 368                         f << stringf("\n");
 369                 f << stringf("autoidx %d\n", autoidx);
 370         }
 371
 372         for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
 373                 if (!only_selected || design->selected(it->second)) {
 374                         if (only_selected)
 375                                 f << stringf("\n");
 376                         dump_module(f, "", it->second, design, only_selected, flag_m, flag_n);
 377                 }
 378         }
 379
 380         log_assert(init_autoidx == autoidx);
 381 }
 382
 383 YOSYS_NAMESPACE_END
 384 PRIVATE_NAMESPACE_BEGIN
 385
 386 struct IlangBackend : public Backend {
 387         IlangBackend() : Backend("ilang", "write design to ilang file") { }
 388         void help() YS_OVERRIDE
 389         {
 390                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 391                 log("\n");
 392                 log("    write_ilang [filename]\n");
 393                 log("\n");
 394                 log("Write the current design to an 'ilang' file. (ilang is a text representation\n");
 395                 log("of a design in yosys's internal format.)\n");
 396                 log("\n");
 397                 log("    -selected\n");
 398                 log("        only write selected parts of the design.\n");
 399                 log("\n");
 400         }
 401         void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 402         {
 403                 bool selected = false;
 404
 405                 log_header(design, "Executing ILANG backend.\n");
 406
 407                 size_t argidx;
 408                 for (argidx = 1; argidx < args.size(); argidx++) {
 409                         std::string arg = args[argidx];
 410                         if (arg == "-selected") {
 411                                 selected = true;
 412                                 continue;
 413                         }
 414                         break;
 415                 }
 416                 extra_args(f, filename, args, argidx);
 417
 418                 design->sort();
 419
 420                 log("Output filename: %s\n", filename.c_str());
 421                 *f << stringf("# Generated by %s\n", yosys_version_str);
 422                 ILANG_BACKEND::dump_design(*f, design, selected, true, false);
 423         }
 424 } IlangBackend;
 425
 426 struct DumpPass : public Pass {
 427         DumpPass() : Pass("dump", "print parts of the design in ilang format") { }
 428         void help() YS_OVERRIDE
 429         {
 430                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 431                 log("\n");
 432                 log("    dump [options] [selection]\n");
 433                 log("\n");
 434                 log("Write the selected parts of the design to the console or specified file in\n");
 435                 log("ilang format.\n");
 436                 log("\n");
 437                 log("    -m\n");
 438                 log("        also dump the module headers, even if only parts of a single\n");
 439                 log("        module is selected\n");
 440                 log("\n");
 441                 log("    -n\n");
 442                 log("        only dump the module headers if the entire module is selected\n");
 443                 log("\n");
 444                 log("    -o <filename>\n");
 445                 log("        write to the specified file.\n");
 446                 log("\n");
 447                 log("    -a <filename>\n");
 448                 log("        like -outfile but append instead of overwrite\n");
 449                 log("\n");
 450         }
 451         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 452         {
 453                 std::string filename;
 454                 bool flag_m = false, flag_n = false, append = false;
 455
 456                 size_t argidx;
 457                 for (argidx = 1; argidx < args.size(); argidx++)
 458                 {
 459                         std::string arg = args[argidx];
 460                         if ((arg == "-o" || arg == "-outfile") && argidx+1 < args.size()) {
 461                                 filename = args[++argidx];
 462                                 append = false;
 463                                 continue;
 464                         }
 465                         if ((arg == "-a" || arg == "-append") && argidx+1 < args.size()) {
 466                                 filename = args[++argidx];
 467                                 append = true;
 468                                 continue;
 469                         }
 470                         if (arg == "-m") {
 471                                 flag_m = true;
 472                                 continue;
 473                         }
 474                         if (arg == "-n") {
 475                                 flag_n = true;
 476                                 continue;
 477                         }
 478                         break;
 479                 }
 480                 extra_args(args, argidx, design);
 481
 482                 std::ostream *f;
 483                 std::stringstream buf;
 484
 485                 if (!filename.empty()) {
 486                         rewrite_filename(filename);
 487                         std::ofstream *ff = new std::ofstream;
 488                         ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
 489                         if (ff->fail()) {
 490                                 delete ff;
 491                                 log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
 492                         }
 493                         f = ff;
 494                 } else {
 495                         f = &buf;
 496                 }
 497
 498                 ILANG_BACKEND::dump_design(*f, design, true, flag_m, flag_n);
 499
 500                 if (!filename.empty()) {
 501                         delete f;
 502                 } else {
 503                         log("%s", buf.str().c_str());
 504                 }
 505         }
 506 } DumpPass;
 507
 508 PRIVATE_NAMESPACE_END