2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * A very simple and straightforward backend for the RTLIL text
21 * representation (as understood by the 'ilang' frontend).
25 #ifndef ILANG_BACKEND_H
26 #define ILANG_BACKEND_H
28 #include "kernel/yosys.h"
33 namespace ILANG_BACKEND
{
34 void dump_const(std::ostream
&f
, const RTLIL::Const
&data
, int width
= -1, int offset
= 0, bool autoint
= true);
35 void dump_sigchunk(std::ostream
&f
, const RTLIL::SigChunk
&chunk
, bool autoint
= true);
36 void dump_sigspec(std::ostream
&f
, const RTLIL::SigSpec
&sig
, bool autoint
= true);
37 void dump_wire(std::ostream
&f
, std::string indent
, const RTLIL::Wire
*wire
);
38 void dump_memory(std::ostream
&f
, std::string indent
, const RTLIL::Memory
*memory
);
39 void dump_cell(std::ostream
&f
, std::string indent
, const RTLIL::Cell
*cell
);
40 void dump_proc_case_body(std::ostream
&f
, std::string indent
, const RTLIL::CaseRule
*cs
);
41 void dump_proc_switch(std::ostream
&f
, std::string indent
, const RTLIL::SwitchRule
*sw
);
42 void dump_proc_sync(std::ostream
&f
, std::string indent
, const RTLIL::SyncRule
*sy
);
43 void dump_proc(std::ostream
&f
, std::string indent
, const RTLIL::Process
*proc
);
44 void dump_conn(std::ostream
&f
, std::string indent
, const RTLIL::SigSpec
&left
, const RTLIL::SigSpec
&right
);
45 void dump_module(std::ostream
&f
, std::string indent
, RTLIL::Module
*module
, RTLIL::Design
*design
, bool only_selected
, bool flag_m
= true, bool flag_n
= false);
46 void dump_design(std::ostream
&f
, RTLIL::Design
*design
, bool only_selected
, bool flag_m
= true, bool flag_n
= false);