backends/intersynth/intersynth.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/rtlil.h"
  21 #include "kernel/register.h"
  22 #include "kernel/sigtools.h"
  23 #include "kernel/celltypes.h"
  24 #include "kernel/log.h"
  25 #include <string>
  26 #include <assert.h>
  27
  28
  29 static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
  30 {
  31         sig.optimize();
  32
  33         if (sig.chunks.size() != 1)
  34 error:
  35                 log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
  36
  37         conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width));
  38
  39         if (sig.chunks[0].wire == NULL) {
  40                 celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.width, sig.width, sig.width));
  41                 constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.width, sig.chunks[0].data.as_int(),
  42                                 sig.width, sig.width, sig.chunks[0].data.as_int(), sig.chunks[0].data.as_int()));
  43                 return stringf("CONST_%d_0x%x", sig.width, sig.chunks[0].data.as_int());
  44         }
  45
  46         if (sig.chunks[0].offset != 0 || sig.width != sig.chunks[0].wire->width)
  47                 goto error;
  48
  49         return RTLIL::unescape_id(sig.chunks[0].wire->name);
  50 }
  51
  52 struct IntersynthBackend : public Backend {
  53         IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
  54         virtual void help()
  55         {
  56                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  57                 log("\n");
  58                 log("    write_intersynth [options] [filename]\n");
  59                 log("\n");
  60                 log("Write the current design to an 'intersynth' netlist file. InterSynth is\n");
  61                 log("a tool for Coarse-Grain Example-Driven Interconnect Synthesis.\n");
  62                 log("\n");
  63                 log("    -notypes\n");
  64                 log("        do not generate celltypes and conntypes commands. i.e. just output\n");
  65                 log("        the netlists. this is used for postsilicon synthesis.\n");
  66                 log("\n");
  67                 log("    -lib <verilog_or_ilang_file>\n");
  68                 log("        Use the specified library file for determining whether cell ports are\n");
  69                 log("        inputs or outputs. This option can be used multiple times to specify\n");
  70                 log("        more than one library.\n");
  71                 log("\n");
  72                 log("    -selected\n");
  73                 log("        only write selected modules. modules must be selected entirely or\n");
  74                 log("        not at all.\n");
  75                 log("\n");
  76                 log("http://www.clifford.at/intersynth/\n");
  77                 log("\n");
  78         }
  79         virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
  80         {
  81                 log_header("Executing INTERSYNTH backend.\n");
  82                 log_push();
  83
  84                 std::vector<std::string> libfiles;
  85                 std::vector<RTLIL::Design*> libs;
  86                 bool flag_notypes = false;
  87                 bool selected = false;
  88
  89                 size_t argidx;
  90                 for (argidx = 1; argidx < args.size(); argidx++)
  91                 {
  92                         if (args[argidx] == "-notypes") {
  93                                 flag_notypes = true;
  94                                 continue;
  95                         }
  96                         if (args[argidx] == "-lib" && argidx+1 < args.size()) {
  97                                 libfiles.push_back(args[++argidx]);
  98                                 continue;
  99                         }
 100                         if (args[argidx] == "-selected") {
 101                                 selected = true;
 102                                 continue;
 103                         }
 104                         break;
 105                 }
 106                 extra_args(f, filename, args, argidx);
 107
 108                 log("Output filename: %s\n", filename.c_str());
 109
 110                 for (auto filename : libfiles) {
 111                         FILE *f = fopen(filename.c_str(), "rt");
 112                         if (f == NULL)
 113                                 log_error("Can't open lib file `%s'.\n", filename.c_str());
 114                         RTLIL::Design *lib = new RTLIL::Design;
 115                         Frontend::frontend_call(lib, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
 116                         libs.push_back(lib);
 117                         fclose(f);
 118                 }
 119
 120                 if (libs.size() > 0)
 121                         log_header("Continuing INTERSYNTH backend.\n");
 122
 123                 std::set<std::string> conntypes_code, celltypes_code;
 124                 std::string netlists_code;
 125                 CellTypes ct(design);
 126
 127                 for (auto lib : libs)
 128                         ct.setup_design(lib);
 129
 130                 for (auto module_it : design->modules)
 131                 {
 132                         RTLIL::Module *module = module_it.second;
 133                         SigMap sigmap(module);
 134
 135                         if (module->attributes.count("\\placeholder") > 0)
 136                                 continue;
 137                         if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
 138                                 continue;
 139
 140                         if (selected && !design->selected_whole_module(module->name)) {
 141                                 if (design->selected_module(module->name))
 142                                         log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name));
 143                                 continue;
 144                         }
 145
 146                         log("Generating netlist %s.\n", RTLIL::id2cstr(module->name));
 147
 148                         if (module->memories.size() != 0 || module->processes.size() != 0)
 149                                 log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
 150
 151                         std::set<std::string> constcells_code;
 152                         netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
 153
 154                         for (auto wire_it : module->wires) {
 155                                 RTLIL::Wire *wire = wire_it.second;
 156                                 if (wire->port_input || wire->port_output) {
 157                                         celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
 158                                                         RTLIL::id2cstr(wire->name), wire->width, wire->port_input ? "*" : "",
 159                                                         wire->port_input ? "input" : "output", RTLIL::id2cstr(wire->name), wire->width, RTLIL::id2cstr(wire->name)));
 160                                         netlists_code += stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(wire->name),
 161                                                         netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
 162                                 }
 163                         }
 164
 165                         for (auto cell_it : module->cells)
 166                         {
 167                                 RTLIL::Cell *cell = cell_it.second;
 168                                 std::string celltype_code, node_code;
 169
 170                                 if (!ct.cell_known(cell->type))
 171                                         log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell->type));
 172
 173                                 celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type));
 174                                 node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 175                                 for (auto &port : cell->connections) {
 176                                         RTLIL::SigSpec sig = sigmap(port.second);
 177                                         conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width));
 178                                         celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
 179                                         node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
 180                                 }
 181                                 for (auto &param : cell->parameters) {
 182                                         celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first));
 183                                         if (param.second.bits.size() != 32) {
 184                                                 node_code += stringf(" %s '", RTLIL::id2cstr(param.first));
 185                                                 for (int i = param.second.bits.size()-1; i >= 0; i--)
 186                                                         node_code += param.second.bits[i] == RTLIL::S1 ? "1" : "0";
 187                                         } else
 188                                                 node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int());
 189                                 }
 190
 191                                 celltypes_code.insert(celltype_code + "\n");
 192                                 netlists_code += node_code + "\n";
 193                         }
 194
 195                         for (auto code : constcells_code)
 196                                 netlists_code += code;
 197                 }
 198
 199                 if (!flag_notypes) {
 200                         for (auto code : conntypes_code)
 201                                 fprintf(f, "%s", code.c_str());
 202                         for (auto code : celltypes_code)
 203                                 fprintf(f, "%s", code.c_str());
 204                 }
 205                 fprintf(f, "%s", netlists_code.c_str());
 206
 207                 for (auto lib : libs)
 208                         delete lib;
 209
 210                 log_pop();
 211         }
 212 } IntersynthBackend;
 213