2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
29 static std::string
netname(std::set
<std::string
> &conntypes_code
, std::set
<std::string
> &celltypes_code
, std::set
<std::string
> &constcells_code
, RTLIL::SigSpec sig
)
33 if (sig
.chunks
.size() != 1)
35 log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig
));
37 conntypes_code
.insert(stringf("conntype b%d %d 2 %d\n", sig
.width
, sig
.width
, sig
.width
));
39 if (sig
.chunks
[0].wire
== NULL
) {
40 celltypes_code
.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig
.width
, sig
.width
, sig
.width
));
41 constcells_code
.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig
.width
, sig
.chunks
[0].data
.as_int(),
42 sig
.width
, sig
.width
, sig
.chunks
[0].data
.as_int(), sig
.chunks
[0].data
.as_int()));
43 return stringf("CONST_%d_0x%x", sig
.width
, sig
.chunks
[0].data
.as_int());
46 if (sig
.chunks
[0].offset
!= 0 || sig
.width
!= sig
.chunks
[0].wire
->width
)
49 return unescape_id(sig
.chunks
[0].wire
->name
);
52 struct IntersynthBackend
: public Backend
{
53 IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
56 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
58 log(" write_intersynth [options] [filename]\n");
60 log("Write the current design to an 'intersynth' netlist file. InterSynth is\n");
61 log("a tool for Coarse-Grain Example-Driven Interconnect Synthesis.\n");
63 log(" -lib <verilog_or_ilang_file>\n");
64 log(" Use the specified library file for determining whether cell ports are\n");
65 log(" inputs or outputs. This option can be used multiple times to specify\n");
66 log(" more than one library.\n");
68 log("http://www.clifford.at/intersynth/\n");
71 virtual void execute(FILE *&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
)
73 log_header("Executing INTERSYNTH backend.\n");
76 std::vector
<std::string
> libfiles
;
77 std::vector
<RTLIL::Design
*> libs
;
80 for (argidx
= 1; argidx
< args
.size(); argidx
++)
82 if (args
[argidx
] == "-lib" && argidx
+1 < args
.size()) {
83 libfiles
.push_back(args
[++argidx
]);
88 extra_args(f
, filename
, args
, argidx
);
90 log("Output filename: %s\n", filename
.c_str());
92 for (auto filename
: libfiles
) {
93 FILE *f
= fopen(filename
.c_str(), "rt");
95 log_error("Can't open lib file `%s'.\n", filename
.c_str());
96 RTLIL::Design
*lib
= new RTLIL::Design
;
97 Frontend::frontend_call(lib
, f
, filename
, (filename
.size() > 3 && filename
.substr(filename
.size()-3) == ".il") ? "ilang" : "verilog");
103 log_header("Continuing INTERSYNTH backend.\n");
105 std::set
<std::string
> conntypes_code
, celltypes_code
;
106 std::string netlists_code
;
107 CellTypes
ct(design
);
109 for (auto lib
: libs
)
110 ct
.setup_design(lib
);
112 for (auto module_it
: design
->modules
)
114 RTLIL::Module
*module
= module_it
.second
;
115 SigMap
sigmap(module
);
117 if (module
->memories
.size() == 0 && module
->processes
.size() == 0 && module
->cells
.size() == 0)
120 log("Generating netlist %s.\n", id2cstr(module
->name
));
122 if (module
->memories
.size() != 0 || module
->processes
.size() != 0)
123 log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
125 std::set
<std::string
> constcells_code
;
126 netlists_code
+= stringf("netlist %s\n", id2cstr(module
->name
));
128 for (auto wire_it
: module
->wires
) {
129 RTLIL::Wire
*wire
= wire_it
.second
;
130 if (wire
->port_input
|| wire
->port_output
) {
131 celltypes_code
.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
132 id2cstr(wire
->name
), wire
->width
, wire
->port_input
? "*" : "",
133 wire
->port_input
? "input" : "output", id2cstr(wire
->name
), wire
->width
, id2cstr(wire
->name
)));
134 netlists_code
+= stringf("node %s %s PORT %s\n", id2cstr(wire
->name
), id2cstr(wire
->name
),
135 netname(conntypes_code
, celltypes_code
, constcells_code
, sigmap(wire
)).c_str());
139 for (auto cell_it
: module
->cells
)
141 RTLIL::Cell
*cell
= cell_it
.second
;
142 std::string celltype_code
, node_code
;
144 if (!ct
.cell_known(cell
->type
))
145 log_error("Found unknown cell type %s in module!\n", id2cstr(cell
->type
));
147 celltype_code
= stringf("celltype %s", id2cstr(cell
->type
));
148 node_code
= stringf("node %s %s", id2cstr(cell
->name
), id2cstr(cell
->type
));
149 for (auto &port
: cell
->connections
) {
150 RTLIL::SigSpec sig
= sigmap(port
.second
);
151 conntypes_code
.insert(stringf("conntype b%d %d 2 %d\n", sig
.width
, sig
.width
, sig
.width
));
152 celltype_code
+= stringf(" b%d %s%s", sig
.width
, ct
.cell_output(cell
->type
, port
.first
) ? "*" : "", id2cstr(port
.first
));
153 node_code
+= stringf(" %s %s", id2cstr(port
.first
), netname(conntypes_code
, celltypes_code
, constcells_code
, sig
).c_str());
155 for (auto ¶m
: cell
->parameters
) {
156 celltype_code
+= stringf(" cfg:%d %s", int(param
.second
.bits
.size()), id2cstr(param
.first
));
157 if (param
.second
.bits
.size() != 32) {
158 node_code
+= stringf(" %s '", id2cstr(param
.first
));
159 for (int i
= param
.second
.bits
.size()-1; i
>= 0; i
--)
160 node_code
+= param
.second
.bits
[i
] == RTLIL::S1
? "1" : "0";
162 node_code
+= stringf(" %s 0x%x", id2cstr(param
.first
), param
.second
.as_int());
165 celltypes_code
.insert(celltype_code
+ "\n");
166 netlists_code
+= node_code
+ "\n";
169 for (auto code
: constcells_code
)
170 netlists_code
+= code
;
173 for (auto code
: conntypes_code
)
174 fprintf(f
, "%s", code
.c_str());
175 for (auto code
: celltypes_code
)
176 fprintf(f
, "%s", code
.c_str());
177 fprintf(f
, "%s", netlists_code
.c_str());
179 for (auto lib
: libs
)