2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
28 static std::string
netname(std::set
<std::string
> &conntypes_code
, std::set
<std::string
> &celltypes_code
, std::set
<std::string
> &constcells_code
, RTLIL::SigSpec sig
)
30 if (!sig
.is_fully_const() && !sig
.is_wire())
31 log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig
));
33 conntypes_code
.insert(stringf("conntype b%d %d 2 %d\n", sig
.size(), sig
.size(), sig
.size()));
35 if (sig
.is_fully_const()) {
36 celltypes_code
.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig
.size(), sig
.size(), sig
.size()));
37 constcells_code
.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n",
38 sig
.size(), sig
.as_int(), sig
.size(), sig
.size(), sig
.as_int(), sig
.as_int()));
39 return stringf("CONST_%d_0x%x", sig
.size(), sig
.as_int());
42 return RTLIL::unescape_id(sig
.as_wire()->name
);
45 struct IntersynthBackend
: public Backend
{
46 IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
49 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
51 log(" write_intersynth [options] [filename]\n");
53 log("Write the current design to an 'intersynth' netlist file. InterSynth is\n");
54 log("a tool for Coarse-Grain Example-Driven Interconnect Synthesis.\n");
57 log(" do not generate celltypes and conntypes commands. i.e. just output\n");
58 log(" the netlists. this is used for postsilicon synthesis.\n");
60 log(" -lib <verilog_or_ilang_file>\n");
61 log(" Use the specified library file for determining whether cell ports are\n");
62 log(" inputs or outputs. This option can be used multiple times to specify\n");
63 log(" more than one library.\n");
66 log(" only write selected modules. modules must be selected entirely or\n");
67 log(" not at all.\n");
69 log("http://www.clifford.at/intersynth/\n");
72 virtual void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
)
74 log_header("Executing INTERSYNTH backend.\n");
77 std::vector
<std::string
> libfiles
;
78 std::vector
<RTLIL::Design
*> libs
;
79 bool flag_notypes
= false;
80 bool selected
= false;
83 for (argidx
= 1; argidx
< args
.size(); argidx
++)
85 if (args
[argidx
] == "-notypes") {
89 if (args
[argidx
] == "-lib" && argidx
+1 < args
.size()) {
90 libfiles
.push_back(args
[++argidx
]);
93 if (args
[argidx
] == "-selected") {
99 extra_args(f
, filename
, args
, argidx
);
101 log("Output filename: %s\n", filename
.c_str());
103 for (auto filename
: libfiles
) {
105 f
.open(filename
.c_str());
107 log_error("Can't open lib file `%s'.\n", filename
.c_str());
108 RTLIL::Design
*lib
= new RTLIL::Design
;
109 Frontend::frontend_call(lib
, &f
, filename
, (filename
.size() > 3 && filename
.substr(filename
.size()-3) == ".il") ? "ilang" : "verilog");
114 log_header("Continuing INTERSYNTH backend.\n");
116 std::set
<std::string
> conntypes_code
, celltypes_code
;
117 std::string netlists_code
;
118 CellTypes
ct(design
);
120 for (auto lib
: libs
)
121 ct
.setup_design(lib
);
123 for (auto module_it
: design
->modules_
)
125 RTLIL::Module
*module
= module_it
.second
;
126 SigMap
sigmap(module
);
128 if (module
->get_bool_attribute("\\blackbox"))
130 if (module
->memories
.size() == 0 && module
->processes
.size() == 0 && module
->cells_
.size() == 0)
133 if (selected
&& !design
->selected_whole_module(module
->name
)) {
134 if (design
->selected_module(module
->name
))
135 log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module
->name
));
139 log("Generating netlist %s.\n", RTLIL::id2cstr(module
->name
));
141 if (module
->memories
.size() != 0 || module
->processes
.size() != 0)
142 log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
144 std::set
<std::string
> constcells_code
;
145 netlists_code
+= stringf("# Netlist of module %s\n", RTLIL::id2cstr(module
->name
));
146 netlists_code
+= stringf("netlist %s\n", RTLIL::id2cstr(module
->name
));
148 // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
149 for (auto wire_it
: module
->wires_
) {
150 RTLIL::Wire
*wire
= wire_it
.second
;
151 if (wire
->port_input
|| wire
->port_output
) {
152 celltypes_code
.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
153 RTLIL::id2cstr(wire
->name
), wire
->width
, wire
->port_input
? "*" : "",
154 wire
->port_input
? "input" : "output", RTLIL::id2cstr(wire
->name
), wire
->width
, RTLIL::id2cstr(wire
->name
)));
155 netlists_code
+= stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire
->name
), RTLIL::id2cstr(wire
->name
),
156 netname(conntypes_code
, celltypes_code
, constcells_code
, sigmap(wire
)).c_str());
160 // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
161 for (auto cell_it
: module
->cells_
)
163 RTLIL::Cell
*cell
= cell_it
.second
;
164 std::string celltype_code
, node_code
;
166 if (!ct
.cell_known(cell
->type
))
167 log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell
->type
));
169 celltype_code
= stringf("celltype %s", RTLIL::id2cstr(cell
->type
));
170 node_code
= stringf("node %s %s", RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
171 for (auto &port
: cell
->connections()) {
172 RTLIL::SigSpec sig
= sigmap(port
.second
);
173 if (sig
.size() != 0) {
174 conntypes_code
.insert(stringf("conntype b%d %d 2 %d\n", sig
.size(), sig
.size(), sig
.size()));
175 celltype_code
+= stringf(" b%d %s%s", sig
.size(), ct
.cell_output(cell
->type
, port
.first
) ? "*" : "", RTLIL::id2cstr(port
.first
));
176 node_code
+= stringf(" %s %s", RTLIL::id2cstr(port
.first
), netname(conntypes_code
, celltypes_code
, constcells_code
, sig
).c_str());
179 for (auto ¶m
: cell
->parameters
) {
180 celltype_code
+= stringf(" cfg:%d %s", int(param
.second
.bits
.size()), RTLIL::id2cstr(param
.first
));
181 if (param
.second
.bits
.size() != 32) {
182 node_code
+= stringf(" %s '", RTLIL::id2cstr(param
.first
));
183 for (int i
= param
.second
.bits
.size()-1; i
>= 0; i
--)
184 node_code
+= param
.second
.bits
[i
] == RTLIL::S1
? "1" : "0";
186 node_code
+= stringf(" %s 0x%x", RTLIL::id2cstr(param
.first
), param
.second
.as_int());
189 celltypes_code
.insert(celltype_code
+ "\n");
190 netlists_code
+= node_code
+ "\n";
193 if (constcells_code
.size() > 0)
194 netlists_code
+= "# constant cells\n";
195 for (auto code
: constcells_code
)
196 netlists_code
+= code
;
197 netlists_code
+= "\n";
201 *f
<< stringf("### Connection Types\n");
202 for (auto code
: conntypes_code
)
203 *f
<< stringf("%s", code
.c_str());
204 *f
<< stringf("\n### Cell Types\n");
205 for (auto code
: celltypes_code
)
206 *f
<< stringf("%s", code
.c_str());
208 *f
<< stringf("\n### Netlists\n");
209 *f
<< stringf("%s", netlists_code
.c_str());
211 for (auto lib
: libs
)