2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
29 static std::string
netname(std::set
<std::string
> &conntypes_code
, std::set
<std::string
> &celltypes_code
, std::set
<std::string
> &constcells_code
, RTLIL::SigSpec sig
)
33 if (sig
.chunks
.size() != 1)
35 log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig
));
37 conntypes_code
.insert(stringf("conntype b%d %d 2 %d\n", sig
.width
, sig
.width
, sig
.width
));
39 if (sig
.chunks
[0].wire
== NULL
) {
40 celltypes_code
.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig
.width
, sig
.width
, sig
.width
));
41 constcells_code
.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig
.width
, sig
.chunks
[0].data
.as_int(),
42 sig
.width
, sig
.width
, sig
.chunks
[0].data
.as_int(), sig
.chunks
[0].data
.as_int()));
43 return stringf("CONST_%d_0x%x", sig
.width
, sig
.chunks
[0].data
.as_int());
46 if (sig
.chunks
[0].offset
!= 0 || sig
.width
!= sig
.chunks
[0].wire
->width
)
49 return RTLIL::unescape_id(sig
.chunks
[0].wire
->name
);
52 struct IntersynthBackend
: public Backend
{
53 IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
56 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
58 log(" write_intersynth [options] [filename]\n");
60 log("Write the current design to an 'intersynth' netlist file. InterSynth is\n");
61 log("a tool for Coarse-Grain Example-Driven Interconnect Synthesis.\n");
64 log(" do not generate celltypes and conntypes commands. i.e. just output\n");
65 log(" the netlists. this is used for postsilicon synthesis.\n");
67 log(" -lib <verilog_or_ilang_file>\n");
68 log(" Use the specified library file for determining whether cell ports are\n");
69 log(" inputs or outputs. This option can be used multiple times to specify\n");
70 log(" more than one library.\n");
73 log(" only write selected modules. modules must be selected entirely or\n");
74 log(" not at all.\n");
76 log("http://www.clifford.at/intersynth/\n");
79 virtual void execute(FILE *&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
)
81 log_header("Executing INTERSYNTH backend.\n");
84 std::vector
<std::string
> libfiles
;
85 std::vector
<RTLIL::Design
*> libs
;
86 bool flag_notypes
= false;
87 bool selected
= false;
90 for (argidx
= 1; argidx
< args
.size(); argidx
++)
92 if (args
[argidx
] == "-notypes") {
96 if (args
[argidx
] == "-lib" && argidx
+1 < args
.size()) {
97 libfiles
.push_back(args
[++argidx
]);
100 if (args
[argidx
] == "-selected") {
106 extra_args(f
, filename
, args
, argidx
);
108 log("Output filename: %s\n", filename
.c_str());
110 for (auto filename
: libfiles
) {
111 FILE *f
= fopen(filename
.c_str(), "rt");
113 log_error("Can't open lib file `%s'.\n", filename
.c_str());
114 RTLIL::Design
*lib
= new RTLIL::Design
;
115 Frontend::frontend_call(lib
, f
, filename
, (filename
.size() > 3 && filename
.substr(filename
.size()-3) == ".il") ? "ilang" : "verilog");
121 log_header("Continuing INTERSYNTH backend.\n");
123 std::set
<std::string
> conntypes_code
, celltypes_code
;
124 std::string netlists_code
;
125 CellTypes
ct(design
);
127 for (auto lib
: libs
)
128 ct
.setup_design(lib
);
130 for (auto module_it
: design
->modules
)
132 RTLIL::Module
*module
= module_it
.second
;
133 SigMap
sigmap(module
);
135 if (module
->get_bool_attribute("\\blackbox"))
137 if (module
->memories
.size() == 0 && module
->processes
.size() == 0 && module
->cells
.size() == 0)
140 if (selected
&& !design
->selected_whole_module(module
->name
)) {
141 if (design
->selected_module(module
->name
))
142 log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module
->name
));
146 log("Generating netlist %s.\n", RTLIL::id2cstr(module
->name
));
148 if (module
->memories
.size() != 0 || module
->processes
.size() != 0)
149 log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
151 std::set
<std::string
> constcells_code
;
152 netlists_code
+= stringf("# Netlist of module %s\n", RTLIL::id2cstr(module
->name
));
153 netlists_code
+= stringf("netlist %s\n", RTLIL::id2cstr(module
->name
));
155 // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
156 for (auto wire_it
: module
->wires
) {
157 RTLIL::Wire
*wire
= wire_it
.second
;
158 if (wire
->port_input
|| wire
->port_output
) {
159 celltypes_code
.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
160 RTLIL::id2cstr(wire
->name
), wire
->width
, wire
->port_input
? "*" : "",
161 wire
->port_input
? "input" : "output", RTLIL::id2cstr(wire
->name
), wire
->width
, RTLIL::id2cstr(wire
->name
)));
162 netlists_code
+= stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire
->name
), RTLIL::id2cstr(wire
->name
),
163 netname(conntypes_code
, celltypes_code
, constcells_code
, sigmap(wire
)).c_str());
167 // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
168 for (auto cell_it
: module
->cells
)
170 RTLIL::Cell
*cell
= cell_it
.second
;
171 std::string celltype_code
, node_code
;
173 if (!ct
.cell_known(cell
->type
))
174 log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell
->type
));
176 celltype_code
= stringf("celltype %s", RTLIL::id2cstr(cell
->type
));
177 node_code
= stringf("node %s %s", RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
178 for (auto &port
: cell
->connections
) {
179 RTLIL::SigSpec sig
= sigmap(port
.second
);
180 if (sig
.width
!= 0) {
181 conntypes_code
.insert(stringf("conntype b%d %d 2 %d\n", sig
.width
, sig
.width
, sig
.width
));
182 celltype_code
+= stringf(" b%d %s%s", sig
.width
, ct
.cell_output(cell
->type
, port
.first
) ? "*" : "", RTLIL::id2cstr(port
.first
));
183 node_code
+= stringf(" %s %s", RTLIL::id2cstr(port
.first
), netname(conntypes_code
, celltypes_code
, constcells_code
, sig
).c_str());
186 for (auto ¶m
: cell
->parameters
) {
187 celltype_code
+= stringf(" cfg:%d %s", int(param
.second
.bits
.size()), RTLIL::id2cstr(param
.first
));
188 if (param
.second
.bits
.size() != 32) {
189 node_code
+= stringf(" %s '", RTLIL::id2cstr(param
.first
));
190 for (int i
= param
.second
.bits
.size()-1; i
>= 0; i
--)
191 node_code
+= param
.second
.bits
[i
] == RTLIL::S1
? "1" : "0";
193 node_code
+= stringf(" %s 0x%x", RTLIL::id2cstr(param
.first
), param
.second
.as_int());
196 celltypes_code
.insert(celltype_code
+ "\n");
197 netlists_code
+= node_code
+ "\n";
200 if (constcells_code
.size() > 0)
201 netlists_code
+= "# constant cells\n";
202 for (auto code
: constcells_code
)
203 netlists_code
+= code
;
204 netlists_code
+= "\n";
208 fprintf(f
, "### Connection Types\n");
209 for (auto code
: conntypes_code
)
210 fprintf(f
, "%s", code
.c_str());
211 fprintf(f
, "\n### Cell Types\n");
212 for (auto code
: celltypes_code
)
213 fprintf(f
, "%s", code
.c_str());
215 fprintf(f
, "\n### Netlists\n");
216 fprintf(f
, "%s", netlists_code
.c_str());
218 for (auto lib
: libs
)