2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
29 PRIVATE_NAMESPACE_BEGIN
42 dict
<SigBit
, string
> sigids
;
45 JsonWriter(std::ostream
&f
, bool use_selection
, bool aig_mode
) :
46 f(f
), use_selection(use_selection
), aig_mode(aig_mode
) { }
48 string
get_string(string str
)
59 string
get_name(IdString name
)
61 return get_string(RTLIL::unescape_id(name
));
64 string
get_bits(SigSpec sig
)
68 for (auto bit
: sigmap(sig
)) {
69 str
+= first
? " " : ", ";
71 if (sigids
.count(bit
) == 0) {
72 string
&s
= sigids
[bit
];
73 if (bit
.wire
== nullptr) {
74 if (bit
== State::S0
) s
= "\"0\"";
75 else if (bit
== State::S1
) s
= "\"1\"";
76 else if (bit
== State::Sz
) s
= "\"z\"";
79 s
= stringf("%d", sigidcounter
++);
86 void write_parameter_value(const Const
&value
)
88 if ((value
.flags
& RTLIL::ConstFlags::CONST_FLAG_STRING
) != 0) {
89 string str
= value
.decode_string();
93 if (c
== '0' || c
== '1' || c
== 'x' || c
== 'z')
99 } else if (state
== 1 && c
!= ' ')
104 f
<< get_string(str
);
106 if (GetSize(value
) == 32 && value
.is_fully_def()) {
107 if ((value
.flags
& RTLIL::ConstFlags::CONST_FLAG_SIGNED
) != 0)
108 f
<< stringf("%d", value
.as_int());
110 f
<< stringf("%u", value
.as_int());
112 f
<< get_string(value
.as_string());
116 void write_parameters(const dict
<IdString
, Const
> ¶meters
, bool for_module
=false)
119 for (auto ¶m
: parameters
) {
120 f
<< stringf("%s\n", first
? "" : ",");
121 f
<< stringf(" %s%s: ", for_module
? "" : " ", get_name(param
.first
).c_str());
122 write_parameter_value(param
.second
);
127 void write_module(Module
*module_
)
130 log_assert(module
->design
== design
);
134 // reserve 0 and 1 to avoid confusion with "0" and "1"
137 f
<< stringf(" %s: {\n", get_name(module
->name
).c_str());
139 f
<< stringf(" \"attributes\": {");
140 write_parameters(module
->attributes
, /*for_module=*/true);
141 f
<< stringf("\n },\n");
143 f
<< stringf(" \"ports\": {");
145 for (auto n
: module
->ports
) {
146 Wire
*w
= module
->wire(n
);
147 if (use_selection
&& !module
->selected(w
))
149 f
<< stringf("%s\n", first
? "" : ",");
150 f
<< stringf(" %s: {\n", get_name(n
).c_str());
151 f
<< stringf(" \"direction\": \"%s\",\n", w
->port_input
? w
->port_output
? "inout" : "input" : "output");
153 f
<< stringf(" \"offset\": %d,\n", w
->start_offset
);
155 f
<< stringf(" \"upto\": 1,\n");
156 f
<< stringf(" \"bits\": %s\n", get_bits(w
).c_str());
160 f
<< stringf("\n },\n");
162 f
<< stringf(" \"cells\": {");
164 for (auto c
: module
->cells()) {
165 if (use_selection
&& !module
->selected(c
))
167 f
<< stringf("%s\n", first
? "" : ",");
168 f
<< stringf(" %s: {\n", get_name(c
->name
).c_str());
169 f
<< stringf(" \"hide_name\": %s,\n", c
->name
[0] == '$' ? "1" : "0");
170 f
<< stringf(" \"type\": %s,\n", get_name(c
->type
).c_str());
173 if (!aig
.name
.empty()) {
174 f
<< stringf(" \"model\": \"%s\",\n", aig
.name
.c_str());
175 aig_models
.insert(aig
);
178 f
<< stringf(" \"parameters\": {");
179 write_parameters(c
->parameters
);
180 f
<< stringf("\n },\n");
181 f
<< stringf(" \"attributes\": {");
182 write_parameters(c
->attributes
);
183 f
<< stringf("\n },\n");
185 f
<< stringf(" \"port_directions\": {");
187 for (auto &conn
: c
->connections()) {
188 string direction
= "output";
189 if (c
->input(conn
.first
))
190 direction
= c
->output(conn
.first
) ? "inout" : "input";
191 f
<< stringf("%s\n", first2
? "" : ",");
192 f
<< stringf(" %s: \"%s\"", get_name(conn
.first
).c_str(), direction
.c_str());
195 f
<< stringf("\n },\n");
197 f
<< stringf(" \"connections\": {");
199 for (auto &conn
: c
->connections()) {
200 f
<< stringf("%s\n", first2
? "" : ",");
201 f
<< stringf(" %s: %s", get_name(conn
.first
).c_str(), get_bits(conn
.second
).c_str());
204 f
<< stringf("\n }\n");
208 f
<< stringf("\n },\n");
210 f
<< stringf(" \"netnames\": {");
212 for (auto w
: module
->wires()) {
213 if (use_selection
&& !module
->selected(w
))
215 f
<< stringf("%s\n", first
? "" : ",");
216 f
<< stringf(" %s: {\n", get_name(w
->name
).c_str());
217 f
<< stringf(" \"hide_name\": %s,\n", w
->name
[0] == '$' ? "1" : "0");
218 f
<< stringf(" \"bits\": %s,\n", get_bits(w
).c_str());
220 f
<< stringf(" \"offset\": %d,\n", w
->start_offset
);
222 f
<< stringf(" \"upto\": 1,\n");
223 f
<< stringf(" \"attributes\": {");
224 write_parameters(w
->attributes
);
225 f
<< stringf("\n }\n");
229 f
<< stringf("\n }\n");
234 void write_design(Design
*design_
)
240 f
<< stringf(" \"creator\": %s,\n", get_string(yosys_version_str
).c_str());
241 f
<< stringf(" \"modules\": {\n");
242 vector
<Module
*> modules
= use_selection
? design
->selected_modules() : design
->modules();
243 bool first_module
= true;
244 for (auto mod
: modules
) {
248 first_module
= false;
250 f
<< stringf("\n }");
251 if (!aig_models
.empty()) {
252 f
<< stringf(",\n \"models\": {\n");
253 bool first_model
= true;
254 for (auto &aig
: aig_models
) {
257 f
<< stringf(" \"%s\": [\n", aig
.name
.c_str());
259 for (auto &node
: aig
.nodes
) {
262 f
<< stringf(" /* %3d */ [ ", node_idx
);
263 if (node
.portbit
>= 0)
264 f
<< stringf("\"%sport\", \"%s\", %d", node
.inverter
? "n" : "",
265 log_id(node
.portname
), node
.portbit
);
266 else if (node
.left_parent
< 0 && node
.right_parent
< 0)
267 f
<< stringf("\"%s\"", node
.inverter
? "true" : "false");
269 f
<< stringf("\"%s\", %d, %d", node
.inverter
? "nand" : "and", node
.left_parent
, node
.right_parent
);
270 for (auto &op
: node
.outports
)
271 f
<< stringf(", \"%s\", %d", log_id(op
.first
), op
.second
);
275 f
<< stringf("\n ]");
278 f
<< stringf("\n }");
280 f
<< stringf("\n}\n");
284 struct JsonBackend
: public Backend
{
285 JsonBackend() : Backend("json", "write design to a JSON file") { }
286 void help() YS_OVERRIDE
288 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
290 log(" write_json [options] [filename]\n");
292 log("Write a JSON netlist of the current design.\n");
295 log(" include AIG models for the different gate types\n");
298 log("The general syntax of the JSON output created by this command is as follows:\n");
301 log(" \"modules\": {\n");
302 log(" <module_name>: {\n");
303 log(" \"ports\": {\n");
304 log(" <port_name>: <port_details>,\n");
307 log(" \"cells\": {\n");
308 log(" <cell_name>: <cell_details>,\n");
311 log(" \"netnames\": {\n");
312 log(" <net_name>: <net_details>,\n");
317 log(" \"models\": {\n");
322 log("Where <port_details> is:\n");
325 log(" \"direction\": <\"input\" | \"output\" | \"inout\">,\n");
326 log(" \"bits\": <bit_vector>\n");
329 log("And <cell_details> is:\n");
332 log(" \"hide_name\": <1 | 0>,\n");
333 log(" \"type\": <cell_type>,\n");
334 log(" \"parameters\": {\n");
335 log(" <parameter_name>: <parameter_value>,\n");
338 log(" \"attributes\": {\n");
339 log(" <attribute_name>: <attribute_value>,\n");
342 log(" \"port_directions\": {\n");
343 log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
346 log(" \"connections\": {\n");
347 log(" <port_name>: <bit_vector>,\n");
352 log("And <net_details> is:\n");
355 log(" \"hide_name\": <1 | 0>,\n");
356 log(" \"bits\": <bit_vector>\n");
359 log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
360 log("automatically created and is likely not of interest for a regular user.\n");
362 log("The \"port_directions\" section is only included for cells for which the\n");
363 log("interface is known.\n");
365 log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
366 log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
367 log("values referenced above are vectors of this integers. Signal bits that are\n");
368 log("connected to a constant driver are denoted as string \"0\", \"1\", \"x\", or\n");
369 log("\"z\" instead of a number.\n");
371 log("Numeric 32-bit parameter and attribute values are written as decimal values.\n");
372 log("Bit verctors of different sizes, or ones containing 'x' or 'z' bits, are written\n");
373 log("as string holding the binary representation of the value. Strings are written\n");
374 log("as strings, with an appended blank in cases of strings of the form /[01xz]* */.\n");
376 log("For example the following Verilog code:\n");
378 log(" module test(input x, y);\n");
379 log(" (* keep *) foo #(.P(42), .Q(1337))\n");
380 log(" foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));\n");
383 log("Translates to the following JSON output:\n");
386 log(" \"modules\": {\n");
387 log(" \"test\": {\n");
388 log(" \"ports\": {\n");
390 log(" \"direction\": \"input\",\n");
391 log(" \"bits\": [ 2 ]\n");
394 log(" \"direction\": \"input\",\n");
395 log(" \"bits\": [ 3 ]\n");
398 log(" \"cells\": {\n");
399 log(" \"foo_inst\": {\n");
400 log(" \"hide_name\": 0,\n");
401 log(" \"type\": \"foo\",\n");
402 log(" \"parameters\": {\n");
403 log(" \"Q\": 1337,\n");
406 log(" \"attributes\": {\n");
407 log(" \"keep\": 1,\n");
408 log(" \"src\": \"test.v:2\"\n");
410 log(" \"connections\": {\n");
411 log(" \"C\": [ 2, 2, 2, 2, \"0\", \"1\", \"0\", \"1\" ],\n");
412 log(" \"B\": [ 2, 3 ],\n");
413 log(" \"A\": [ 3, 2 ]\n");
417 log(" \"netnames\": {\n");
419 log(" \"hide_name\": 0,\n");
420 log(" \"bits\": [ 3 ],\n");
421 log(" \"attributes\": {\n");
422 log(" \"src\": \"test.v:1\"\n");
426 log(" \"hide_name\": 0,\n");
427 log(" \"bits\": [ 2 ],\n");
428 log(" \"attributes\": {\n");
429 log(" \"src\": \"test.v:1\"\n");
437 log("The models are given as And-Inverter-Graphs (AIGs) in the following form:\n");
439 log(" \"models\": {\n");
440 log(" <model_name>: [\n");
441 log(" /* 0 */ [ <node-spec> ],\n");
442 log(" /* 1 */ [ <node-spec> ],\n");
443 log(" /* 2 */ [ <node-spec> ],\n");
449 log("The following node-types may be used:\n");
451 log(" [ \"port\", <portname>, <bitindex>, <out-list> ]\n");
452 log(" - the value of the specified input port bit\n");
454 log(" [ \"nport\", <portname>, <bitindex>, <out-list> ]\n");
455 log(" - the inverted value of the specified input port bit\n");
457 log(" [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
458 log(" - the ANDed value of the specified nodes\n");
460 log(" [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
461 log(" - the inverted ANDed value of the specified nodes\n");
463 log(" [ \"true\", <out-list> ]\n");
464 log(" - the constant value 1\n");
466 log(" [ \"false\", <out-list> ]\n");
467 log(" - the constant value 0\n");
469 log("All nodes appear in topological order. I.e. only nodes with smaller indices\n");
470 log("are referenced by \"and\" and \"nand\" nodes.\n");
472 log("The optional <out-list> at the end of a node specification is a list of\n");
473 log("output portname and bitindex pairs, specifying the outputs driven by this node.\n");
475 log("For example, the following is the model for a 3-input 3-output $reduce_and cell\n");
476 log("inferred by the following code:\n");
478 log(" module test(input [2:0] in, output [2:0] out);\n");
479 log(" assign in = &out;\n");
482 log(" \"$reduce_and:3U:3\": [\n");
483 log(" /* 0 */ [ \"port\", \"A\", 0 ],\n");
484 log(" /* 1 */ [ \"port\", \"A\", 1 ],\n");
485 log(" /* 2 */ [ \"and\", 0, 1 ],\n");
486 log(" /* 3 */ [ \"port\", \"A\", 2 ],\n");
487 log(" /* 4 */ [ \"and\", 2, 3, \"Y\", 0 ],\n");
488 log(" /* 5 */ [ \"false\", \"Y\", 1, \"Y\", 2 ]\n");
491 log("Future version of Yosys might add support for additional fields in the JSON\n");
492 log("format. A program processing this format must ignore all unknown fields.\n");
495 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
497 bool aig_mode
= false;
500 for (argidx
= 1; argidx
< args
.size(); argidx
++)
502 if (args
[argidx
] == "-aig") {
508 extra_args(f
, filename
, args
, argidx
);
510 log_header(design
, "Executing JSON backend.\n");
512 JsonWriter
json_writer(*f
, false, aig_mode
);
513 json_writer
.write_design(design
);
517 struct JsonPass
: public Pass
{
518 JsonPass() : Pass("json", "write design in JSON format") { }
519 void help() YS_OVERRIDE
521 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
523 log(" json [options] [selection]\n");
525 log("Write a JSON netlist of all selected objects.\n");
527 log(" -o <filename>\n");
528 log(" write to the specified file.\n");
531 log(" also include AIG models for the different gate types\n");
533 log("See 'help write_json' for a description of the JSON format used.\n");
536 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
538 std::string filename
;
539 bool aig_mode
= false;
542 for (argidx
= 1; argidx
< args
.size(); argidx
++)
544 if (args
[argidx
] == "-o" && argidx
+1 < args
.size()) {
545 filename
= args
[++argidx
];
548 if (args
[argidx
] == "-aig") {
554 extra_args(args
, argidx
, design
);
557 std::stringstream buf
;
559 if (!filename
.empty()) {
560 rewrite_filename(filename
);
561 std::ofstream
*ff
= new std::ofstream
;
562 ff
->open(filename
.c_str(), std::ofstream::trunc
);
565 log_error("Can't open file `%s' for writing: %s\n", filename
.c_str(), strerror(errno
));
572 JsonWriter
json_writer(*f
, true, aig_mode
);
573 json_writer
.write_design(design
);
575 if (!filename
.empty()) {
578 log("%s", buf
.str().c_str());
583 PRIVATE_NAMESPACE_END