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Fix handling of some formal cells in btor back-end
[yosys.git] / backends / json / json.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
26 #include <string>
27
28 USING_YOSYS_NAMESPACE
29 PRIVATE_NAMESPACE_BEGIN
30
31 struct JsonWriter
32 {
33 std::ostream &f;
34 bool use_selection;
35 bool aig_mode;
36 bool compat_int_mode;
37
38 Design *design;
39 Module *module;
40
41 SigMap sigmap;
42 int sigidcounter;
43 dict<SigBit, string> sigids;
44 pool<Aig> aig_models;
45
46 JsonWriter(std::ostream &f, bool use_selection, bool aig_mode, bool compat_int_mode) :
47 f(f), use_selection(use_selection), aig_mode(aig_mode),
48 compat_int_mode(compat_int_mode) { }
49
50 string get_string(string str)
51 {
52 string newstr = "\"";
53 for (char c : str) {
54 if (c == '\\')
55 newstr += "\\\\";
56 else if (c == '"')
57 newstr += "\\\"";
58 else if (c == '\b')
59 newstr += "\\b";
60 else if (c == '\f')
61 newstr += "\\f";
62 else if (c == '\n')
63 newstr += "\\n";
64 else if (c == '\r')
65 newstr += "\\r";
66 else if (c == '\t')
67 newstr += "\\t";
68 else if (c < 0x20)
69 newstr += stringf("\\u%04X", c);
70 else
71 newstr += c;
72 }
73 return newstr + "\"";
74 }
75
76 string get_name(IdString name)
77 {
78 return get_string(RTLIL::unescape_id(name));
79 }
80
81 string get_bits(SigSpec sig)
82 {
83 bool first = true;
84 string str = "[";
85 for (auto bit : sigmap(sig)) {
86 str += first ? " " : ", ";
87 first = false;
88 if (sigids.count(bit) == 0) {
89 string &s = sigids[bit];
90 if (bit.wire == nullptr) {
91 if (bit == State::S0) s = "\"0\"";
92 else if (bit == State::S1) s = "\"1\"";
93 else if (bit == State::Sz) s = "\"z\"";
94 else s = "\"x\"";
95 } else
96 s = stringf("%d", sigidcounter++);
97 }
98 str += sigids[bit];
99 }
100 return str + " ]";
101 }
102
103 void write_parameter_value(const Const &value)
104 {
105 if ((value.flags & RTLIL::ConstFlags::CONST_FLAG_STRING) != 0) {
106 string str = value.decode_string();
107 int state = 0;
108 for (char c : str) {
109 if (state == 0) {
110 if (c == '0' || c == '1' || c == 'x' || c == 'z')
111 state = 0;
112 else if (c == ' ')
113 state = 1;
114 else
115 state = 2;
116 } else if (state == 1 && c != ' ')
117 state = 2;
118 }
119 if (state < 2)
120 str += " ";
121 f << get_string(str);
122 } else if (compat_int_mode && GetSize(value) <= 32 && value.is_fully_def()) {
123 if ((value.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) != 0)
124 f << stringf("%d", value.as_int());
125 else
126 f << stringf("%u", value.as_int());
127 } else {
128 f << get_string(value.as_string());
129 }
130 }
131
132 void write_parameters(const dict<IdString, Const> &parameters, bool for_module=false)
133 {
134 bool first = true;
135 for (auto &param : parameters) {
136 f << stringf("%s\n", first ? "" : ",");
137 f << stringf(" %s%s: ", for_module ? "" : " ", get_name(param.first).c_str());
138 write_parameter_value(param.second);
139 first = false;
140 }
141 }
142
143 void write_module(Module *module_)
144 {
145 module = module_;
146 log_assert(module->design == design);
147 sigmap.set(module);
148 sigids.clear();
149
150 // reserve 0 and 1 to avoid confusion with "0" and "1"
151 sigidcounter = 2;
152
153 if (module->has_processes()) {
154 log_error("Module %s contains processes, which are not supported by JSON backend (run `proc` first).\n", log_id(module));
155 }
156
157 f << stringf(" %s: {\n", get_name(module->name).c_str());
158
159 f << stringf(" \"attributes\": {");
160 write_parameters(module->attributes, /*for_module=*/true);
161 f << stringf("\n },\n");
162
163 if (module->parameter_default_values.size()) {
164 f << stringf(" \"parameter_default_values\": {");
165 write_parameters(module->parameter_default_values, /*for_module=*/true);
166 f << stringf("\n },\n");
167 }
168
169 f << stringf(" \"ports\": {");
170 bool first = true;
171 for (auto n : module->ports) {
172 Wire *w = module->wire(n);
173 if (use_selection && !module->selected(w))
174 continue;
175 f << stringf("%s\n", first ? "" : ",");
176 f << stringf(" %s: {\n", get_name(n).c_str());
177 f << stringf(" \"direction\": \"%s\",\n", w->port_input ? w->port_output ? "inout" : "input" : "output");
178 if (w->start_offset)
179 f << stringf(" \"offset\": %d,\n", w->start_offset);
180 if (w->upto)
181 f << stringf(" \"upto\": 1,\n");
182 if (w->is_signed)
183 f << stringf(" \"signed\": %d,\n", w->is_signed);
184 f << stringf(" \"bits\": %s\n", get_bits(w).c_str());
185 f << stringf(" }");
186 first = false;
187 }
188 f << stringf("\n },\n");
189
190 f << stringf(" \"cells\": {");
191 first = true;
192 for (auto c : module->cells()) {
193 if (use_selection && !module->selected(c))
194 continue;
195 f << stringf("%s\n", first ? "" : ",");
196 f << stringf(" %s: {\n", get_name(c->name).c_str());
197 f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
198 f << stringf(" \"type\": %s,\n", get_name(c->type).c_str());
199 if (aig_mode) {
200 Aig aig(c);
201 if (!aig.name.empty()) {
202 f << stringf(" \"model\": \"%s\",\n", aig.name.c_str());
203 aig_models.insert(aig);
204 }
205 }
206 f << stringf(" \"parameters\": {");
207 write_parameters(c->parameters);
208 f << stringf("\n },\n");
209 f << stringf(" \"attributes\": {");
210 write_parameters(c->attributes);
211 f << stringf("\n },\n");
212 if (c->known()) {
213 f << stringf(" \"port_directions\": {");
214 bool first2 = true;
215 for (auto &conn : c->connections()) {
216 string direction = "output";
217 if (c->input(conn.first))
218 direction = c->output(conn.first) ? "inout" : "input";
219 f << stringf("%s\n", first2 ? "" : ",");
220 f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
221 first2 = false;
222 }
223 f << stringf("\n },\n");
224 }
225 f << stringf(" \"connections\": {");
226 bool first2 = true;
227 for (auto &conn : c->connections()) {
228 f << stringf("%s\n", first2 ? "" : ",");
229 f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
230 first2 = false;
231 }
232 f << stringf("\n }\n");
233 f << stringf(" }");
234 first = false;
235 }
236 f << stringf("\n },\n");
237
238 if (!module->memories.empty()) {
239 f << stringf(" \"memories\": {");
240 first = true;
241 for (auto &it : module->memories) {
242 if (use_selection && !module->selected(it.second))
243 continue;
244 f << stringf("%s\n", first ? "" : ",");
245 f << stringf(" %s: {\n", get_name(it.second->name).c_str());
246 f << stringf(" \"hide_name\": %s,\n", it.second->name[0] == '$' ? "1" : "0");
247 f << stringf(" \"attributes\": {");
248 write_parameters(it.second->attributes);
249 f << stringf("\n },\n");
250 f << stringf(" \"width\": %d,\n", it.second->width);
251 f << stringf(" \"start_offset\": %d,\n", it.second->start_offset);
252 f << stringf(" \"size\": %d\n", it.second->size);
253 f << stringf(" }");
254 first = false;
255 }
256 f << stringf("\n },\n");
257 }
258
259 f << stringf(" \"netnames\": {");
260 first = true;
261 for (auto w : module->wires()) {
262 if (use_selection && !module->selected(w))
263 continue;
264 f << stringf("%s\n", first ? "" : ",");
265 f << stringf(" %s: {\n", get_name(w->name).c_str());
266 f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
267 f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
268 if (w->start_offset)
269 f << stringf(" \"offset\": %d,\n", w->start_offset);
270 if (w->upto)
271 f << stringf(" \"upto\": 1,\n");
272 if (w->is_signed)
273 f << stringf(" \"signed\": %d,\n", w->is_signed);
274 f << stringf(" \"attributes\": {");
275 write_parameters(w->attributes);
276 f << stringf("\n }\n");
277 f << stringf(" }");
278 first = false;
279 }
280 f << stringf("\n }\n");
281
282 f << stringf(" }");
283 }
284
285 void write_design(Design *design_)
286 {
287 design = design_;
288 design->sort();
289
290 f << stringf("{\n");
291 f << stringf(" \"creator\": %s,\n", get_string(yosys_version_str).c_str());
292 f << stringf(" \"modules\": {\n");
293 vector<Module*> modules = use_selection ? design->selected_modules() : design->modules();
294 bool first_module = true;
295 for (auto mod : modules) {
296 if (!first_module)
297 f << stringf(",\n");
298 write_module(mod);
299 first_module = false;
300 }
301 f << stringf("\n }");
302 if (!aig_models.empty()) {
303 f << stringf(",\n \"models\": {\n");
304 bool first_model = true;
305 for (auto &aig : aig_models) {
306 if (!first_model)
307 f << stringf(",\n");
308 f << stringf(" \"%s\": [\n", aig.name.c_str());
309 int node_idx = 0;
310 for (auto &node : aig.nodes) {
311 if (node_idx != 0)
312 f << stringf(",\n");
313 f << stringf(" /* %3d */ [ ", node_idx);
314 if (node.portbit >= 0)
315 f << stringf("\"%sport\", \"%s\", %d", node.inverter ? "n" : "",
316 log_id(node.portname), node.portbit);
317 else if (node.left_parent < 0 && node.right_parent < 0)
318 f << stringf("\"%s\"", node.inverter ? "true" : "false");
319 else
320 f << stringf("\"%s\", %d, %d", node.inverter ? "nand" : "and", node.left_parent, node.right_parent);
321 for (auto &op : node.outports)
322 f << stringf(", \"%s\", %d", log_id(op.first), op.second);
323 f << stringf(" ]");
324 node_idx++;
325 }
326 f << stringf("\n ]");
327 first_model = false;
328 }
329 f << stringf("\n }");
330 }
331 f << stringf("\n}\n");
332 }
333 };
334
335 struct JsonBackend : public Backend {
336 JsonBackend() : Backend("json", "write design to a JSON file") { }
337 void help() override
338 {
339 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
340 log("\n");
341 log(" write_json [options] [filename]\n");
342 log("\n");
343 log("Write a JSON netlist of the current design.\n");
344 log("\n");
345 log(" -aig\n");
346 log(" include AIG models for the different gate types\n");
347 log("\n");
348 log(" -compat-int\n");
349 log(" emit 32-bit or smaller fully-defined parameter values directly\n");
350 log(" as JSON numbers (for compatibility with old parsers)\n");
351 log("\n");
352 log("\n");
353 log("The general syntax of the JSON output created by this command is as follows:\n");
354 log("\n");
355 log(" {\n");
356 log(" \"creator\": \"Yosys <version info>\",\n");
357 log(" \"modules\": {\n");
358 log(" <module_name>: {\n");
359 log(" \"attributes\": {\n");
360 log(" <attribute_name>: <attribute_value>,\n");
361 log(" ...\n");
362 log(" },\n");
363 log(" \"parameter_default_values\": {\n");
364 log(" <parameter_name>: <parameter_value>,\n");
365 log(" ...\n");
366 log(" },\n");
367 log(" \"ports\": {\n");
368 log(" <port_name>: <port_details>,\n");
369 log(" ...\n");
370 log(" },\n");
371 log(" \"cells\": {\n");
372 log(" <cell_name>: <cell_details>,\n");
373 log(" ...\n");
374 log(" },\n");
375 log(" \"memories\": {\n");
376 log(" <memory_name>: <memory_details>,\n");
377 log(" ...\n");
378 log(" },\n");
379 log(" \"netnames\": {\n");
380 log(" <net_name>: <net_details>,\n");
381 log(" ...\n");
382 log(" }\n");
383 log(" }\n");
384 log(" },\n");
385 log(" \"models\": {\n");
386 log(" ...\n");
387 log(" },\n");
388 log(" }\n");
389 log("\n");
390 log("Where <port_details> is:\n");
391 log("\n");
392 log(" {\n");
393 log(" \"direction\": <\"input\" | \"output\" | \"inout\">,\n");
394 log(" \"bits\": <bit_vector>\n");
395 log(" \"offset\": <the lowest bit index in use, if non-0>\n");
396 log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
397 log(" }\n");
398 log("\n");
399 log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.");
400 log("They don't affect connection semantics, and are only used to preserve original");
401 log("HDL bit indexing.");
402 log("And <cell_details> is:\n");
403 log("\n");
404 log(" {\n");
405 log(" \"hide_name\": <1 | 0>,\n");
406 log(" \"type\": <cell_type>,\n");
407 log(" \"model\": <AIG model name, if -aig option used>,\n");
408 log(" \"parameters\": {\n");
409 log(" <parameter_name>: <parameter_value>,\n");
410 log(" ...\n");
411 log(" },\n");
412 log(" \"attributes\": {\n");
413 log(" <attribute_name>: <attribute_value>,\n");
414 log(" ...\n");
415 log(" },\n");
416 log(" \"port_directions\": {\n");
417 log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
418 log(" ...\n");
419 log(" },\n");
420 log(" \"connections\": {\n");
421 log(" <port_name>: <bit_vector>,\n");
422 log(" ...\n");
423 log(" },\n");
424 log(" }\n");
425 log("\n");
426 log("And <memory_details> is:\n");
427 log("\n");
428 log(" {\n");
429 log(" \"hide_name\": <1 | 0>,\n");
430 log(" \"attributes\": {\n");
431 log(" <attribute_name>: <attribute_value>,\n");
432 log(" ...\n");
433 log(" },\n");
434 log(" \"width\": <memory width>\n");
435 log(" \"start_offset\": <the lowest valid memory address>\n");
436 log(" \"size\": <memory size>\n");
437 log(" }\n");
438 log("\n");
439 log("And <net_details> is:\n");
440 log("\n");
441 log(" {\n");
442 log(" \"hide_name\": <1 | 0>,\n");
443 log(" \"bits\": <bit_vector>\n");
444 log(" \"offset\": <the lowest bit index in use, if non-0>\n");
445 log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
446 log(" }\n");
447 log("\n");
448 log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
449 log("automatically created and is likely not of interest for a regular user.\n");
450 log("\n");
451 log("The \"port_directions\" section is only included for cells for which the\n");
452 log("interface is known.\n");
453 log("\n");
454 log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
455 log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
456 log("values referenced above are vectors of this integers. Signal bits that are\n");
457 log("connected to a constant driver are denoted as string \"0\", \"1\", \"x\", or\n");
458 log("\"z\" instead of a number.\n");
459 log("\n");
460 log("Bit vectors (including integers) are written as string holding the binary");
461 log("representation of the value. Strings are written as strings, with an appended");
462 log("blank in cases of strings of the form /[01xz]* */.\n");
463 log("\n");
464 log("For example the following Verilog code:\n");
465 log("\n");
466 log(" module test(input x, y);\n");
467 log(" (* keep *) foo #(.P(42), .Q(1337))\n");
468 log(" foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));\n");
469 log(" endmodule\n");
470 log("\n");
471 log("Translates to the following JSON output:\n");
472 log("\n");
473
474 log(" {\n");
475 log(" \"creator\": \"Yosys 0.9+2406 (git sha1 fb1168d8, clang 9.0.1 -fPIC -Os)\",\n");
476 log(" \"modules\": {\n");
477 log(" \"test\": {\n");
478 log(" \"attributes\": {\n");
479 log(" \"cells_not_processed\": \"00000000000000000000000000000001\",\n");
480 log(" \"src\": \"test.v:1.1-4.10\"\n");
481 log(" },\n");
482 log(" \"ports\": {\n");
483 log(" \"x\": {\n");
484 log(" \"direction\": \"input\",\n");
485 log(" \"bits\": [ 2 ]\n");
486 log(" },\n");
487 log(" \"y\": {\n");
488 log(" \"direction\": \"input\",\n");
489 log(" \"bits\": [ 3 ]\n");
490 log(" }\n");
491 log(" },\n");
492 log(" \"cells\": {\n");
493 log(" \"foo_inst\": {\n");
494 log(" \"hide_name\": 0,\n");
495 log(" \"type\": \"foo\",\n");
496 log(" \"parameters\": {\n");
497 log(" \"P\": \"00000000000000000000000000101010\",\n");
498 log(" \"Q\": \"00000000000000000000010100111001\"\n");
499 log(" },\n");
500 log(" \"attributes\": {\n");
501 log(" \"keep\": \"00000000000000000000000000000001\",\n");
502 log(" \"module_not_derived\": \"00000000000000000000000000000001\",\n");
503 log(" \"src\": \"test.v:3.1-3.55\"\n");
504 log(" },\n");
505 log(" \"connections\": {\n");
506 log(" \"A\": [ 3, 2 ],\n");
507 log(" \"B\": [ 2, 3 ],\n");
508 log(" \"C\": [ 2, 2, 2, 2, \"0\", \"1\", \"0\", \"1\" ]\n");
509 log(" }\n");
510 log(" }\n");
511 log(" },\n");
512 log(" \"netnames\": {\n");
513 log(" \"x\": {\n");
514 log(" \"hide_name\": 0,\n");
515 log(" \"bits\": [ 2 ],\n");
516 log(" \"attributes\": {\n");
517 log(" \"src\": \"test.v:1.19-1.20\"\n");
518 log(" }\n");
519 log(" },\n");
520 log(" \"y\": {\n");
521 log(" \"hide_name\": 0,\n");
522 log(" \"bits\": [ 3 ],\n");
523 log(" \"attributes\": {\n");
524 log(" \"src\": \"test.v:1.22-1.23\"\n");
525 log(" }\n");
526 log(" }\n");
527 log(" }\n");
528 log(" }\n");
529 log(" }\n");
530 log(" }\n");
531 log("\n");
532 log("The models are given as And-Inverter-Graphs (AIGs) in the following form:\n");
533 log("\n");
534 log(" \"models\": {\n");
535 log(" <model_name>: [\n");
536 log(" /* 0 */ [ <node-spec> ],\n");
537 log(" /* 1 */ [ <node-spec> ],\n");
538 log(" /* 2 */ [ <node-spec> ],\n");
539 log(" ...\n");
540 log(" ],\n");
541 log(" ...\n");
542 log(" },\n");
543 log("\n");
544 log("The following node-types may be used:\n");
545 log("\n");
546 log(" [ \"port\", <portname>, <bitindex>, <out-list> ]\n");
547 log(" - the value of the specified input port bit\n");
548 log("\n");
549 log(" [ \"nport\", <portname>, <bitindex>, <out-list> ]\n");
550 log(" - the inverted value of the specified input port bit\n");
551 log("\n");
552 log(" [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
553 log(" - the ANDed value of the specified nodes\n");
554 log("\n");
555 log(" [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
556 log(" - the inverted ANDed value of the specified nodes\n");
557 log("\n");
558 log(" [ \"true\", <out-list> ]\n");
559 log(" - the constant value 1\n");
560 log("\n");
561 log(" [ \"false\", <out-list> ]\n");
562 log(" - the constant value 0\n");
563 log("\n");
564 log("All nodes appear in topological order. I.e. only nodes with smaller indices\n");
565 log("are referenced by \"and\" and \"nand\" nodes.\n");
566 log("\n");
567 log("The optional <out-list> at the end of a node specification is a list of\n");
568 log("output portname and bitindex pairs, specifying the outputs driven by this node.\n");
569 log("\n");
570 log("For example, the following is the model for a 3-input 3-output $reduce_and cell\n");
571 log("inferred by the following code:\n");
572 log("\n");
573 log(" module test(input [2:0] in, output [2:0] out);\n");
574 log(" assign in = &out;\n");
575 log(" endmodule\n");
576 log("\n");
577 log(" \"$reduce_and:3U:3\": [\n");
578 log(" /* 0 */ [ \"port\", \"A\", 0 ],\n");
579 log(" /* 1 */ [ \"port\", \"A\", 1 ],\n");
580 log(" /* 2 */ [ \"and\", 0, 1 ],\n");
581 log(" /* 3 */ [ \"port\", \"A\", 2 ],\n");
582 log(" /* 4 */ [ \"and\", 2, 3, \"Y\", 0 ],\n");
583 log(" /* 5 */ [ \"false\", \"Y\", 1, \"Y\", 2 ]\n");
584 log(" ]\n");
585 log("\n");
586 log("Future version of Yosys might add support for additional fields in the JSON\n");
587 log("format. A program processing this format must ignore all unknown fields.\n");
588 log("\n");
589 }
590 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
591 {
592 bool aig_mode = false;
593 bool compat_int_mode = false;
594
595 size_t argidx;
596 for (argidx = 1; argidx < args.size(); argidx++)
597 {
598 if (args[argidx] == "-aig") {
599 aig_mode = true;
600 continue;
601 }
602 if (args[argidx] == "-compat-int") {
603 compat_int_mode = true;
604 continue;
605 }
606 break;
607 }
608 extra_args(f, filename, args, argidx);
609
610 log_header(design, "Executing JSON backend.\n");
611
612 JsonWriter json_writer(*f, false, aig_mode, compat_int_mode);
613 json_writer.write_design(design);
614 }
615 } JsonBackend;
616
617 struct JsonPass : public Pass {
618 JsonPass() : Pass("json", "write design in JSON format") { }
619 void help() override
620 {
621 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
622 log("\n");
623 log(" json [options] [selection]\n");
624 log("\n");
625 log("Write a JSON netlist of all selected objects.\n");
626 log("\n");
627 log(" -o <filename>\n");
628 log(" write to the specified file.\n");
629 log("\n");
630 log(" -aig\n");
631 log(" also include AIG models for the different gate types\n");
632 log("\n");
633 log(" -compat-int\n");
634 log(" emit 32-bit or smaller fully-defined parameter values directly\n");
635 log(" as JSON numbers (for compatibility with old parsers)\n");
636 log("\n");
637 log("See 'help write_json' for a description of the JSON format used.\n");
638 log("\n");
639 }
640 void execute(std::vector<std::string> args, RTLIL::Design *design) override
641 {
642 std::string filename;
643 bool aig_mode = false;
644 bool compat_int_mode = false;
645
646 size_t argidx;
647 for (argidx = 1; argidx < args.size(); argidx++)
648 {
649 if (args[argidx] == "-o" && argidx+1 < args.size()) {
650 filename = args[++argidx];
651 continue;
652 }
653 if (args[argidx] == "-aig") {
654 aig_mode = true;
655 continue;
656 }
657 if (args[argidx] == "-compat-int") {
658 compat_int_mode = true;
659 continue;
660 }
661 break;
662 }
663 extra_args(args, argidx, design);
664
665 std::ostream *f;
666 std::stringstream buf;
667
668 if (!filename.empty()) {
669 rewrite_filename(filename);
670 std::ofstream *ff = new std::ofstream;
671 ff->open(filename.c_str(), std::ofstream::trunc);
672 if (ff->fail()) {
673 delete ff;
674 log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
675 }
676 f = ff;
677 } else {
678 f = &buf;
679 }
680
681 JsonWriter json_writer(*f, true, aig_mode, compat_int_mode);
682 json_writer.write_design(design);
683
684 if (!filename.empty()) {
685 delete f;
686 } else {
687 log("%s", buf.str().c_str());
688 }
689 }
690 } JsonPass;
691
692 PRIVATE_NAMESPACE_END