2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
29 PRIVATE_NAMESPACE_BEGIN
42 dict
<SigBit
, string
> sigids
;
45 JsonWriter(std::ostream
&f
, bool use_selection
, bool aig_mode
) :
46 f(f
), use_selection(use_selection
), aig_mode(aig_mode
) { }
48 string
get_string(string str
)
59 string
get_name(IdString name
)
61 return get_string(RTLIL::unescape_id(name
));
64 string
get_bits(SigSpec sig
)
68 for (auto bit
: sigmap(sig
)) {
69 str
+= first
? " " : ", ";
71 if (sigids
.count(bit
) == 0) {
72 string
&s
= sigids
[bit
];
73 if (bit
.wire
== nullptr) {
74 if (bit
== State::S0
) s
= "\"0\"";
75 else if (bit
== State::S1
) s
= "\"1\"";
76 else if (bit
== State::Sz
) s
= "\"z\"";
79 s
= stringf("%d", sigidcounter
++);
86 void write_parameters(const dict
<IdString
, Const
> ¶meters
, bool for_module
=false)
89 for (auto ¶m
: parameters
) {
90 f
<< stringf("%s\n", first
? "" : ",");
91 f
<< stringf(" %s%s: ", for_module
? "" : " ", get_name(param
.first
).c_str());
92 if ((param
.second
.flags
& RTLIL::ConstFlags::CONST_FLAG_STRING
) != 0)
93 f
<< get_string(param
.second
.decode_string());
94 else if (GetSize(param
.second
.bits
) > 32)
95 f
<< get_string(param
.second
.as_string());
96 else if ((param
.second
.flags
& RTLIL::ConstFlags::CONST_FLAG_SIGNED
) != 0)
97 f
<< stringf("%d", param
.second
.as_int());
99 f
<< stringf("%u", param
.second
.as_int());
104 void write_module(Module
*module_
)
107 log_assert(module
->design
== design
);
111 // reserve 0 and 1 to avoid confusion with "0" and "1"
114 f
<< stringf(" %s: {\n", get_name(module
->name
).c_str());
116 f
<< stringf(" \"attributes\": {");
117 write_parameters(module
->attributes
, /*for_module=*/true);
118 f
<< stringf("\n },\n");
120 f
<< stringf(" \"ports\": {");
122 for (auto n
: module
->ports
) {
123 Wire
*w
= module
->wire(n
);
124 if (use_selection
&& !module
->selected(w
))
126 f
<< stringf("%s\n", first
? "" : ",");
127 f
<< stringf(" %s: {\n", get_name(n
).c_str());
128 f
<< stringf(" \"direction\": \"%s\",\n", w
->port_input
? w
->port_output
? "inout" : "input" : "output");
129 f
<< stringf(" \"bits\": %s\n", get_bits(w
).c_str());
133 f
<< stringf("\n },\n");
135 f
<< stringf(" \"cells\": {");
137 for (auto c
: module
->cells()) {
138 if (use_selection
&& !module
->selected(c
))
140 f
<< stringf("%s\n", first
? "" : ",");
141 f
<< stringf(" %s: {\n", get_name(c
->name
).c_str());
142 f
<< stringf(" \"hide_name\": %s,\n", c
->name
[0] == '$' ? "1" : "0");
143 f
<< stringf(" \"type\": %s,\n", get_name(c
->type
).c_str());
146 if (!aig
.name
.empty()) {
147 f
<< stringf(" \"model\": \"%s\",\n", aig
.name
.c_str());
148 aig_models
.insert(aig
);
151 f
<< stringf(" \"parameters\": {");
152 write_parameters(c
->parameters
);
153 f
<< stringf("\n },\n");
154 f
<< stringf(" \"attributes\": {");
155 write_parameters(c
->attributes
);
156 f
<< stringf("\n },\n");
158 f
<< stringf(" \"port_directions\": {");
160 for (auto &conn
: c
->connections()) {
161 string direction
= "output";
162 if (c
->input(conn
.first
))
163 direction
= c
->output(conn
.first
) ? "inout" : "input";
164 f
<< stringf("%s\n", first2
? "" : ",");
165 f
<< stringf(" %s: \"%s\"", get_name(conn
.first
).c_str(), direction
.c_str());
168 f
<< stringf("\n },\n");
170 f
<< stringf(" \"connections\": {");
172 for (auto &conn
: c
->connections()) {
173 f
<< stringf("%s\n", first2
? "" : ",");
174 f
<< stringf(" %s: %s", get_name(conn
.first
).c_str(), get_bits(conn
.second
).c_str());
177 f
<< stringf("\n }\n");
181 f
<< stringf("\n },\n");
183 f
<< stringf(" \"netnames\": {");
185 for (auto w
: module
->wires()) {
186 if (use_selection
&& !module
->selected(w
))
188 f
<< stringf("%s\n", first
? "" : ",");
189 f
<< stringf(" %s: {\n", get_name(w
->name
).c_str());
190 f
<< stringf(" \"hide_name\": %s,\n", w
->name
[0] == '$' ? "1" : "0");
191 f
<< stringf(" \"bits\": %s,\n", get_bits(w
).c_str());
192 f
<< stringf(" \"attributes\": {");
193 write_parameters(w
->attributes
);
194 f
<< stringf("\n }\n");
198 f
<< stringf("\n }\n");
203 void write_design(Design
*design_
)
209 f
<< stringf(" \"creator\": %s,\n", get_string(yosys_version_str
).c_str());
210 f
<< stringf(" \"modules\": {\n");
211 vector
<Module
*> modules
= use_selection
? design
->selected_modules() : design
->modules();
212 bool first_module
= true;
213 for (auto mod
: modules
) {
217 first_module
= false;
219 f
<< stringf("\n }");
220 if (!aig_models
.empty()) {
221 f
<< stringf(",\n \"models\": {\n");
222 bool first_model
= true;
223 for (auto &aig
: aig_models
) {
226 f
<< stringf(" \"%s\": [\n", aig
.name
.c_str());
228 for (auto &node
: aig
.nodes
) {
231 f
<< stringf(" /* %3d */ [ ", node_idx
);
232 if (node
.portbit
>= 0)
233 f
<< stringf("\"%sport\", \"%s\", %d", node
.inverter
? "n" : "",
234 log_id(node
.portname
), node
.portbit
);
235 else if (node
.left_parent
< 0 && node
.right_parent
< 0)
236 f
<< stringf("\"%s\"", node
.inverter
? "true" : "false");
238 f
<< stringf("\"%s\", %d, %d", node
.inverter
? "nand" : "and", node
.left_parent
, node
.right_parent
);
239 for (auto &op
: node
.outports
)
240 f
<< stringf(", \"%s\", %d", log_id(op
.first
), op
.second
);
244 f
<< stringf("\n ]");
247 f
<< stringf("\n }");
249 f
<< stringf("\n}\n");
253 struct JsonBackend
: public Backend
{
254 JsonBackend() : Backend("json", "write design to a JSON file") { }
255 void help() YS_OVERRIDE
257 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
259 log(" write_json [options] [filename]\n");
261 log("Write a JSON netlist of the current design.\n");
264 log(" include AIG models for the different gate types\n");
267 log("The general syntax of the JSON output created by this command is as follows:\n");
270 log(" \"modules\": {\n");
271 log(" <module_name>: {\n");
272 log(" \"ports\": {\n");
273 log(" <port_name>: <port_details>,\n");
276 log(" \"cells\": {\n");
277 log(" <cell_name>: <cell_details>,\n");
280 log(" \"netnames\": {\n");
281 log(" <net_name>: <net_details>,\n");
286 log(" \"models\": {\n");
291 log("Where <port_details> is:\n");
294 log(" \"direction\": <\"input\" | \"output\" | \"inout\">,\n");
295 log(" \"bits\": <bit_vector>\n");
298 log("And <cell_details> is:\n");
301 log(" \"hide_name\": <1 | 0>,\n");
302 log(" \"type\": <cell_type>,\n");
303 log(" \"parameters\": {\n");
304 log(" <parameter_name>: <parameter_value>,\n");
307 log(" \"attributes\": {\n");
308 log(" <attribute_name>: <attribute_value>,\n");
311 log(" \"port_directions\": {\n");
312 log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
315 log(" \"connections\": {\n");
316 log(" <port_name>: <bit_vector>,\n");
321 log("And <net_details> is:\n");
324 log(" \"hide_name\": <1 | 0>,\n");
325 log(" \"bits\": <bit_vector>\n");
328 log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
329 log("automatically created and is likely not of interest for a regular user.\n");
331 log("The \"port_directions\" section is only included for cells for which the\n");
332 log("interface is known.\n");
334 log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
335 log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
336 log("values referenced above are vectors of this integers. Signal bits that are\n");
337 log("connected to a constant driver are denoted as string \"0\" or \"1\" instead of\n");
340 log("Numeric parameter and attribute values up to 32 bits are written as decimal\n");
341 log("values. Numbers larger than that are written as string holding the binary\n");
342 log("representation of the value.\n");
344 log("For example the following Verilog code:\n");
346 log(" module test(input x, y);\n");
347 log(" (* keep *) foo #(.P(42), .Q(1337))\n");
348 log(" foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));\n");
351 log("Translates to the following JSON output:\n");
354 log(" \"modules\": {\n");
355 log(" \"test\": {\n");
356 log(" \"ports\": {\n");
358 log(" \"direction\": \"input\",\n");
359 log(" \"bits\": [ 2 ]\n");
362 log(" \"direction\": \"input\",\n");
363 log(" \"bits\": [ 3 ]\n");
366 log(" \"cells\": {\n");
367 log(" \"foo_inst\": {\n");
368 log(" \"hide_name\": 0,\n");
369 log(" \"type\": \"foo\",\n");
370 log(" \"parameters\": {\n");
371 log(" \"Q\": 1337,\n");
374 log(" \"attributes\": {\n");
375 log(" \"keep\": 1,\n");
376 log(" \"src\": \"test.v:2\"\n");
378 log(" \"connections\": {\n");
379 log(" \"C\": [ 2, 2, 2, 2, \"0\", \"1\", \"0\", \"1\" ],\n");
380 log(" \"B\": [ 2, 3 ],\n");
381 log(" \"A\": [ 3, 2 ]\n");
385 log(" \"netnames\": {\n");
387 log(" \"hide_name\": 0,\n");
388 log(" \"bits\": [ 3 ],\n");
389 log(" \"attributes\": {\n");
390 log(" \"src\": \"test.v:1\"\n");
394 log(" \"hide_name\": 0,\n");
395 log(" \"bits\": [ 2 ],\n");
396 log(" \"attributes\": {\n");
397 log(" \"src\": \"test.v:1\"\n");
405 log("The models are given as And-Inverter-Graphs (AIGs) in the following form:\n");
407 log(" \"models\": {\n");
408 log(" <model_name>: [\n");
409 log(" /* 0 */ [ <node-spec> ],\n");
410 log(" /* 1 */ [ <node-spec> ],\n");
411 log(" /* 2 */ [ <node-spec> ],\n");
417 log("The following node-types may be used:\n");
419 log(" [ \"port\", <portname>, <bitindex>, <out-list> ]\n");
420 log(" - the value of the specified input port bit\n");
422 log(" [ \"nport\", <portname>, <bitindex>, <out-list> ]\n");
423 log(" - the inverted value of the specified input port bit\n");
425 log(" [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
426 log(" - the ANDed value of the specified nodes\n");
428 log(" [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
429 log(" - the inverted ANDed value of the specified nodes\n");
431 log(" [ \"true\", <out-list> ]\n");
432 log(" - the constant value 1\n");
434 log(" [ \"false\", <out-list> ]\n");
435 log(" - the constant value 0\n");
437 log("All nodes appear in topological order. I.e. only nodes with smaller indices\n");
438 log("are referenced by \"and\" and \"nand\" nodes.\n");
440 log("The optional <out-list> at the end of a node specification is a list of\n");
441 log("output portname and bitindex pairs, specifying the outputs driven by this node.\n");
443 log("For example, the following is the model for a 3-input 3-output $reduce_and cell\n");
444 log("inferred by the following code:\n");
446 log(" module test(input [2:0] in, output [2:0] out);\n");
447 log(" assign in = &out;\n");
450 log(" \"$reduce_and:3U:3\": [\n");
451 log(" /* 0 */ [ \"port\", \"A\", 0 ],\n");
452 log(" /* 1 */ [ \"port\", \"A\", 1 ],\n");
453 log(" /* 2 */ [ \"and\", 0, 1 ],\n");
454 log(" /* 3 */ [ \"port\", \"A\", 2 ],\n");
455 log(" /* 4 */ [ \"and\", 2, 3, \"Y\", 0 ],\n");
456 log(" /* 5 */ [ \"false\", \"Y\", 1, \"Y\", 2 ]\n");
459 log("Future version of Yosys might add support for additional fields in the JSON\n");
460 log("format. A program processing this format must ignore all unknown fields.\n");
463 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
465 bool aig_mode
= false;
468 for (argidx
= 1; argidx
< args
.size(); argidx
++)
470 if (args
[argidx
] == "-aig") {
476 extra_args(f
, filename
, args
, argidx
);
478 log_header(design
, "Executing JSON backend.\n");
480 JsonWriter
json_writer(*f
, false, aig_mode
);
481 json_writer
.write_design(design
);
485 struct JsonPass
: public Pass
{
486 JsonPass() : Pass("json", "write design in JSON format") { }
487 void help() YS_OVERRIDE
489 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
491 log(" json [options] [selection]\n");
493 log("Write a JSON netlist of all selected objects.\n");
495 log(" -o <filename>\n");
496 log(" write to the specified file.\n");
499 log(" also include AIG models for the different gate types\n");
501 log("See 'help write_json' for a description of the JSON format used.\n");
504 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
506 std::string filename
;
507 bool aig_mode
= false;
510 for (argidx
= 1; argidx
< args
.size(); argidx
++)
512 if (args
[argidx
] == "-o" && argidx
+1 < args
.size()) {
513 filename
= args
[++argidx
];
516 if (args
[argidx
] == "-aig") {
522 extra_args(args
, argidx
, design
);
525 std::stringstream buf
;
527 if (!filename
.empty()) {
528 rewrite_filename(filename
);
529 std::ofstream
*ff
= new std::ofstream
;
530 ff
->open(filename
.c_str(), std::ofstream::trunc
);
533 log_error("Can't open file `%s' for writing: %s\n", filename
.c_str(), strerror(errno
));
540 JsonWriter
json_writer(*f
, true, aig_mode
);
541 json_writer
.write_design(design
);
543 if (!filename
.empty()) {
546 log("%s", buf
.str().c_str());
551 PRIVATE_NAMESPACE_END