2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
29 PRIVATE_NAMESPACE_BEGIN
42 dict
<SigBit
, string
> sigids
;
45 JsonWriter(std::ostream
&f
, bool use_selection
, bool aig_mode
) :
46 f(f
), use_selection(use_selection
), aig_mode(aig_mode
) { }
48 string
get_string(string str
)
59 string
get_name(IdString name
)
61 return get_string(RTLIL::unescape_id(name
));
64 string
get_bits(SigSpec sig
)
68 for (auto bit
: sigmap(sig
)) {
69 str
+= first
? " " : ", ";
71 if (sigids
.count(bit
) == 0) {
72 string
&s
= sigids
[bit
];
73 if (bit
.wire
== nullptr) {
74 if (bit
== State::S0
) s
= "\"0\"";
75 else if (bit
== State::S1
) s
= "\"1\"";
76 else if (bit
== State::Sz
) s
= "\"z\"";
79 s
= stringf("%d", sigidcounter
++);
86 void write_parameters(const dict
<IdString
, Const
> ¶meters
, bool for_module
=false)
89 for (auto ¶m
: parameters
) {
90 f
<< stringf("%s\n", first
? "" : ",");
91 f
<< stringf(" %s%s: ", for_module
? "" : " ", get_name(param
.first
).c_str());
92 if ((param
.second
.flags
& RTLIL::ConstFlags::CONST_FLAG_STRING
) != 0)
93 f
<< get_string(param
.second
.decode_string());
94 else if (GetSize(param
.second
.bits
) > 32)
95 f
<< get_string(param
.second
.as_string());
96 else if ((param
.second
.flags
& RTLIL::ConstFlags::CONST_FLAG_SIGNED
) != 0)
97 f
<< stringf("%d", param
.second
.as_int());
99 f
<< stringf("%u", param
.second
.as_int());
104 void write_module(Module
*module_
)
107 log_assert(module
->design
== design
);
111 // reserve 0 and 1 to avoid confusion with "0" and "1"
114 f
<< stringf(" %s: {\n", get_name(module
->name
).c_str());
116 f
<< stringf(" \"attributes\": {");
117 write_parameters(module
->attributes
, /*for_module=*/true);
118 f
<< stringf("\n },\n");
120 f
<< stringf(" \"ports\": {");
122 for (auto n
: module
->ports
) {
123 Wire
*w
= module
->wire(n
);
124 if (use_selection
&& !module
->selected(w
))
126 f
<< stringf("%s\n", first
? "" : ",");
127 f
<< stringf(" %s: {\n", get_name(n
).c_str());
128 f
<< stringf(" \"direction\": \"%s\",\n", w
->port_input
? w
->port_output
? "inout" : "input" : "output");
129 f
<< stringf(" \"bits\": %s\n", get_bits(w
).c_str());
133 f
<< stringf("\n }");
135 if (!module
->get_blackbox_attribute()) {
136 f
<< stringf(",\n \"cells\": {");
138 for (auto c
: module
->cells()) {
139 if (use_selection
&& !module
->selected(c
))
141 f
<< stringf("%s\n", first
? "" : ",");
142 f
<< stringf(" %s: {\n", get_name(c
->name
).c_str());
143 f
<< stringf(" \"hide_name\": %s,\n", c
->name
[0] == '$' ? "1" : "0");
144 f
<< stringf(" \"type\": %s,\n", get_name(c
->type
).c_str());
147 if (!aig
.name
.empty()) {
148 f
<< stringf(" \"model\": \"%s\",\n", aig
.name
.c_str());
149 aig_models
.insert(aig
);
152 f
<< stringf(" \"parameters\": {");
153 write_parameters(c
->parameters
);
154 f
<< stringf("\n },\n");
155 f
<< stringf(" \"attributes\": {");
156 write_parameters(c
->attributes
);
157 f
<< stringf("\n },\n");
159 f
<< stringf(" \"port_directions\": {");
161 for (auto &conn
: c
->connections()) {
162 string direction
= "output";
163 if (c
->input(conn
.first
))
164 direction
= c
->output(conn
.first
) ? "inout" : "input";
165 f
<< stringf("%s\n", first2
? "" : ",");
166 f
<< stringf(" %s: \"%s\"", get_name(conn
.first
).c_str(), direction
.c_str());
169 f
<< stringf("\n },\n");
171 f
<< stringf(" \"connections\": {");
173 for (auto &conn
: c
->connections()) {
174 f
<< stringf("%s\n", first2
? "" : ",");
175 f
<< stringf(" %s: %s", get_name(conn
.first
).c_str(), get_bits(conn
.second
).c_str());
178 f
<< stringf("\n }\n");
182 f
<< stringf("\n },\n");
184 f
<< stringf(" \"netnames\": {");
186 for (auto w
: module
->wires()) {
187 if (use_selection
&& !module
->selected(w
))
189 f
<< stringf("%s\n", first
? "" : ",");
190 f
<< stringf(" %s: {\n", get_name(w
->name
).c_str());
191 f
<< stringf(" \"hide_name\": %s,\n", w
->name
[0] == '$' ? "1" : "0");
192 f
<< stringf(" \"bits\": %s,\n", get_bits(w
).c_str());
193 f
<< stringf(" \"attributes\": {");
194 write_parameters(w
->attributes
);
195 f
<< stringf("\n }\n");
199 f
<< stringf("\n }");
206 void write_design(Design
*design_
)
212 f
<< stringf(" \"creator\": %s,\n", get_string(yosys_version_str
).c_str());
213 f
<< stringf(" \"modules\": {\n");
214 vector
<Module
*> modules
= use_selection
? design
->selected_modules() : design
->modules();
215 bool first_module
= true;
216 for (auto mod
: modules
) {
220 first_module
= false;
222 f
<< stringf("\n }");
223 if (!aig_models
.empty()) {
224 f
<< stringf(",\n \"models\": {\n");
225 bool first_model
= true;
226 for (auto &aig
: aig_models
) {
229 f
<< stringf(" \"%s\": [\n", aig
.name
.c_str());
231 for (auto &node
: aig
.nodes
) {
234 f
<< stringf(" /* %3d */ [ ", node_idx
);
235 if (node
.portbit
>= 0)
236 f
<< stringf("\"%sport\", \"%s\", %d", node
.inverter
? "n" : "",
237 log_id(node
.portname
), node
.portbit
);
238 else if (node
.left_parent
< 0 && node
.right_parent
< 0)
239 f
<< stringf("\"%s\"", node
.inverter
? "true" : "false");
241 f
<< stringf("\"%s\", %d, %d", node
.inverter
? "nand" : "and", node
.left_parent
, node
.right_parent
);
242 for (auto &op
: node
.outports
)
243 f
<< stringf(", \"%s\", %d", log_id(op
.first
), op
.second
);
247 f
<< stringf("\n ]");
250 f
<< stringf("\n }");
252 f
<< stringf("\n}\n");
256 struct JsonBackend
: public Backend
{
257 JsonBackend() : Backend("json", "write design to a JSON file") { }
258 void help() YS_OVERRIDE
260 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
262 log(" write_json [options] [filename]\n");
264 log("Write a JSON netlist of the current design.\n");
267 log(" include AIG models for the different gate types\n");
270 log("The general syntax of the JSON output created by this command is as follows:\n");
273 log(" \"modules\": {\n");
274 log(" <module_name>: {\n");
275 log(" \"ports\": {\n");
276 log(" <port_name>: <port_details>,\n");
279 log(" \"cells\": {\n");
280 log(" <cell_name>: <cell_details>,\n");
283 log(" \"netnames\": {\n");
284 log(" <net_name>: <net_details>,\n");
289 log(" \"models\": {\n");
294 log("Where <port_details> is:\n");
297 log(" \"direction\": <\"input\" | \"output\" | \"inout\">,\n");
298 log(" \"bits\": <bit_vector>\n");
301 log("And <cell_details> is:\n");
304 log(" \"hide_name\": <1 | 0>,\n");
305 log(" \"type\": <cell_type>,\n");
306 log(" \"parameters\": {\n");
307 log(" <parameter_name>: <parameter_value>,\n");
310 log(" \"attributes\": {\n");
311 log(" <attribute_name>: <attribute_value>,\n");
314 log(" \"port_directions\": {\n");
315 log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
318 log(" \"connections\": {\n");
319 log(" <port_name>: <bit_vector>,\n");
324 log("And <net_details> is:\n");
327 log(" \"hide_name\": <1 | 0>,\n");
328 log(" \"bits\": <bit_vector>\n");
331 log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
332 log("automatically created and is likely not of interest for a regular user.\n");
334 log("The \"port_directions\" section is only included for cells for which the\n");
335 log("interface is known.\n");
337 log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
338 log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
339 log("values referenced above are vectors of this integers. Signal bits that are\n");
340 log("connected to a constant driver are denoted as string \"0\" or \"1\" instead of\n");
343 log("Numeric parameter and attribute values up to 32 bits are written as decimal\n");
344 log("values. Numbers larger than that are written as string holding the binary\n");
345 log("representation of the value.\n");
347 log("For example the following Verilog code:\n");
349 log(" module test(input x, y);\n");
350 log(" (* keep *) foo #(.P(42), .Q(1337))\n");
351 log(" foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));\n");
354 log("Translates to the following JSON output:\n");
357 log(" \"modules\": {\n");
358 log(" \"test\": {\n");
359 log(" \"ports\": {\n");
361 log(" \"direction\": \"input\",\n");
362 log(" \"bits\": [ 2 ]\n");
365 log(" \"direction\": \"input\",\n");
366 log(" \"bits\": [ 3 ]\n");
369 log(" \"cells\": {\n");
370 log(" \"foo_inst\": {\n");
371 log(" \"hide_name\": 0,\n");
372 log(" \"type\": \"foo\",\n");
373 log(" \"parameters\": {\n");
374 log(" \"Q\": 1337,\n");
377 log(" \"attributes\": {\n");
378 log(" \"keep\": 1,\n");
379 log(" \"src\": \"test.v:2\"\n");
381 log(" \"connections\": {\n");
382 log(" \"C\": [ 2, 2, 2, 2, \"0\", \"1\", \"0\", \"1\" ],\n");
383 log(" \"B\": [ 2, 3 ],\n");
384 log(" \"A\": [ 3, 2 ]\n");
388 log(" \"netnames\": {\n");
390 log(" \"hide_name\": 0,\n");
391 log(" \"bits\": [ 3 ],\n");
392 log(" \"attributes\": {\n");
393 log(" \"src\": \"test.v:1\"\n");
397 log(" \"hide_name\": 0,\n");
398 log(" \"bits\": [ 2 ],\n");
399 log(" \"attributes\": {\n");
400 log(" \"src\": \"test.v:1\"\n");
408 log("The models are given as And-Inverter-Graphs (AIGs) in the following form:\n");
410 log(" \"models\": {\n");
411 log(" <model_name>: [\n");
412 log(" /* 0 */ [ <node-spec> ],\n");
413 log(" /* 1 */ [ <node-spec> ],\n");
414 log(" /* 2 */ [ <node-spec> ],\n");
420 log("The following node-types may be used:\n");
422 log(" [ \"port\", <portname>, <bitindex>, <out-list> ]\n");
423 log(" - the value of the specified input port bit\n");
425 log(" [ \"nport\", <portname>, <bitindex>, <out-list> ]\n");
426 log(" - the inverted value of the specified input port bit\n");
428 log(" [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
429 log(" - the ANDed value of the specified nodes\n");
431 log(" [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
432 log(" - the inverted ANDed value of the specified nodes\n");
434 log(" [ \"true\", <out-list> ]\n");
435 log(" - the constant value 1\n");
437 log(" [ \"false\", <out-list> ]\n");
438 log(" - the constant value 0\n");
440 log("All nodes appear in topological order. I.e. only nodes with smaller indices\n");
441 log("are referenced by \"and\" and \"nand\" nodes.\n");
443 log("The optional <out-list> at the end of a node specification is a list of\n");
444 log("output portname and bitindex pairs, specifying the outputs driven by this node.\n");
446 log("For example, the following is the model for a 3-input 3-output $reduce_and cell\n");
447 log("inferred by the following code:\n");
449 log(" module test(input [2:0] in, output [2:0] out);\n");
450 log(" assign in = &out;\n");
453 log(" \"$reduce_and:3U:3\": [\n");
454 log(" /* 0 */ [ \"port\", \"A\", 0 ],\n");
455 log(" /* 1 */ [ \"port\", \"A\", 1 ],\n");
456 log(" /* 2 */ [ \"and\", 0, 1 ],\n");
457 log(" /* 3 */ [ \"port\", \"A\", 2 ],\n");
458 log(" /* 4 */ [ \"and\", 2, 3, \"Y\", 0 ],\n");
459 log(" /* 5 */ [ \"false\", \"Y\", 1, \"Y\", 2 ]\n");
462 log("Future version of Yosys might add support for additional fields in the JSON\n");
463 log("format. A program processing this format must ignore all unknown fields.\n");
466 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
468 bool aig_mode
= false;
471 for (argidx
= 1; argidx
< args
.size(); argidx
++)
473 if (args
[argidx
] == "-aig") {
479 extra_args(f
, filename
, args
, argidx
);
481 log_header(design
, "Executing JSON backend.\n");
483 JsonWriter
json_writer(*f
, false, aig_mode
);
484 json_writer
.write_design(design
);
488 struct JsonPass
: public Pass
{
489 JsonPass() : Pass("json", "write design in JSON format") { }
490 void help() YS_OVERRIDE
492 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
494 log(" json [options] [selection]\n");
496 log("Write a JSON netlist of all selected objects.\n");
498 log(" -o <filename>\n");
499 log(" write to the specified file.\n");
502 log(" also include AIG models for the different gate types\n");
504 log("See 'help write_json' for a description of the JSON format used.\n");
507 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
509 std::string filename
;
510 bool aig_mode
= false;
513 for (argidx
= 1; argidx
< args
.size(); argidx
++)
515 if (args
[argidx
] == "-o" && argidx
+1 < args
.size()) {
516 filename
= args
[++argidx
];
519 if (args
[argidx
] == "-aig") {
525 extra_args(args
, argidx
, design
);
528 std::stringstream buf
;
530 if (!filename
.empty()) {
531 std::ofstream
*ff
= new std::ofstream
;
532 ff
->open(filename
.c_str(), std::ofstream::trunc
);
535 log_error("Can't open file `%s' for writing: %s\n", filename
.c_str(), strerror(errno
));
542 JsonWriter
json_writer(*f
, true, aig_mode
);
543 json_writer
.write_design(design
);
545 if (!filename
.empty()) {
548 log("%s", buf
.str().c_str());
553 PRIVATE_NAMESPACE_END