2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
29 PRIVATE_NAMESPACE_BEGIN
43 dict
<SigBit
, string
> sigids
;
46 JsonWriter(std::ostream
&f
, bool use_selection
, bool aig_mode
, bool compat_int_mode
) :
47 f(f
), use_selection(use_selection
), aig_mode(aig_mode
),
48 compat_int_mode(compat_int_mode
) { }
50 string
get_string(string str
)
61 string
get_name(IdString name
)
63 return get_string(RTLIL::unescape_id(name
));
66 string
get_bits(SigSpec sig
)
70 for (auto bit
: sigmap(sig
)) {
71 str
+= first
? " " : ", ";
73 if (sigids
.count(bit
) == 0) {
74 string
&s
= sigids
[bit
];
75 if (bit
.wire
== nullptr) {
76 if (bit
== State::S0
) s
= "\"0\"";
77 else if (bit
== State::S1
) s
= "\"1\"";
78 else if (bit
== State::Sz
) s
= "\"z\"";
81 s
= stringf("%d", sigidcounter
++);
88 void write_parameter_value(const Const
&value
)
90 if ((value
.flags
& RTLIL::ConstFlags::CONST_FLAG_STRING
) != 0) {
91 string str
= value
.decode_string();
95 if (c
== '0' || c
== '1' || c
== 'x' || c
== 'z')
101 } else if (state
== 1 && c
!= ' ')
106 f
<< get_string(str
);
107 } else if (compat_int_mode
&& GetSize(value
) <= 32 && value
.is_fully_def()) {
108 if ((value
.flags
& RTLIL::ConstFlags::CONST_FLAG_SIGNED
) != 0)
109 f
<< stringf("%d", value
.as_int());
111 f
<< stringf("%u", value
.as_int());
113 f
<< get_string(value
.as_string());
117 void write_parameters(const dict
<IdString
, Const
> ¶meters
, bool for_module
=false)
120 for (auto ¶m
: parameters
) {
121 f
<< stringf("%s\n", first
? "" : ",");
122 f
<< stringf(" %s%s: ", for_module
? "" : " ", get_name(param
.first
).c_str());
123 write_parameter_value(param
.second
);
128 void write_module(Module
*module_
)
131 log_assert(module
->design
== design
);
135 // reserve 0 and 1 to avoid confusion with "0" and "1"
138 f
<< stringf(" %s: {\n", get_name(module
->name
).c_str());
140 f
<< stringf(" \"attributes\": {");
141 write_parameters(module
->attributes
, /*for_module=*/true);
142 f
<< stringf("\n },\n");
144 if (module
->parameter_default_values
.size()) {
145 f
<< stringf(" \"parameter_default_values\": {");
146 write_parameters(module
->parameter_default_values
, /*for_module=*/true);
147 f
<< stringf("\n },\n");
150 f
<< stringf(" \"ports\": {");
152 for (auto n
: module
->ports
) {
153 Wire
*w
= module
->wire(n
);
154 if (use_selection
&& !module
->selected(w
))
156 f
<< stringf("%s\n", first
? "" : ",");
157 f
<< stringf(" %s: {\n", get_name(n
).c_str());
158 f
<< stringf(" \"direction\": \"%s\",\n", w
->port_input
? w
->port_output
? "inout" : "input" : "output");
160 f
<< stringf(" \"offset\": %d,\n", w
->start_offset
);
162 f
<< stringf(" \"upto\": 1,\n");
164 f
<< stringf(" \"signed\": %d,\n", w
->is_signed
);
165 f
<< stringf(" \"bits\": %s\n", get_bits(w
).c_str());
169 f
<< stringf("\n },\n");
171 f
<< stringf(" \"cells\": {");
173 for (auto c
: module
->cells()) {
174 if (use_selection
&& !module
->selected(c
))
176 f
<< stringf("%s\n", first
? "" : ",");
177 f
<< stringf(" %s: {\n", get_name(c
->name
).c_str());
178 f
<< stringf(" \"hide_name\": %s,\n", c
->name
[0] == '$' ? "1" : "0");
179 f
<< stringf(" \"type\": %s,\n", get_name(c
->type
).c_str());
182 if (!aig
.name
.empty()) {
183 f
<< stringf(" \"model\": \"%s\",\n", aig
.name
.c_str());
184 aig_models
.insert(aig
);
187 f
<< stringf(" \"parameters\": {");
188 write_parameters(c
->parameters
);
189 f
<< stringf("\n },\n");
190 f
<< stringf(" \"attributes\": {");
191 write_parameters(c
->attributes
);
192 f
<< stringf("\n },\n");
194 f
<< stringf(" \"port_directions\": {");
196 for (auto &conn
: c
->connections()) {
197 string direction
= "output";
198 if (c
->input(conn
.first
))
199 direction
= c
->output(conn
.first
) ? "inout" : "input";
200 f
<< stringf("%s\n", first2
? "" : ",");
201 f
<< stringf(" %s: \"%s\"", get_name(conn
.first
).c_str(), direction
.c_str());
204 f
<< stringf("\n },\n");
206 f
<< stringf(" \"connections\": {");
208 for (auto &conn
: c
->connections()) {
209 f
<< stringf("%s\n", first2
? "" : ",");
210 f
<< stringf(" %s: %s", get_name(conn
.first
).c_str(), get_bits(conn
.second
).c_str());
213 f
<< stringf("\n }\n");
217 f
<< stringf("\n },\n");
219 f
<< stringf(" \"netnames\": {");
221 for (auto w
: module
->wires()) {
222 if (use_selection
&& !module
->selected(w
))
224 f
<< stringf("%s\n", first
? "" : ",");
225 f
<< stringf(" %s: {\n", get_name(w
->name
).c_str());
226 f
<< stringf(" \"hide_name\": %s,\n", w
->name
[0] == '$' ? "1" : "0");
227 f
<< stringf(" \"bits\": %s,\n", get_bits(w
).c_str());
229 f
<< stringf(" \"offset\": %d,\n", w
->start_offset
);
231 f
<< stringf(" \"upto\": 1,\n");
233 f
<< stringf(" \"signed\": %d,\n", w
->is_signed
);
234 f
<< stringf(" \"attributes\": {");
235 write_parameters(w
->attributes
);
236 f
<< stringf("\n }\n");
240 f
<< stringf("\n }\n");
245 void write_design(Design
*design_
)
251 f
<< stringf(" \"creator\": %s,\n", get_string(yosys_version_str
).c_str());
252 f
<< stringf(" \"modules\": {\n");
253 vector
<Module
*> modules
= use_selection
? design
->selected_modules() : design
->modules();
254 bool first_module
= true;
255 for (auto mod
: modules
) {
259 first_module
= false;
261 f
<< stringf("\n }");
262 if (!aig_models
.empty()) {
263 f
<< stringf(",\n \"models\": {\n");
264 bool first_model
= true;
265 for (auto &aig
: aig_models
) {
268 f
<< stringf(" \"%s\": [\n", aig
.name
.c_str());
270 for (auto &node
: aig
.nodes
) {
273 f
<< stringf(" /* %3d */ [ ", node_idx
);
274 if (node
.portbit
>= 0)
275 f
<< stringf("\"%sport\", \"%s\", %d", node
.inverter
? "n" : "",
276 log_id(node
.portname
), node
.portbit
);
277 else if (node
.left_parent
< 0 && node
.right_parent
< 0)
278 f
<< stringf("\"%s\"", node
.inverter
? "true" : "false");
280 f
<< stringf("\"%s\", %d, %d", node
.inverter
? "nand" : "and", node
.left_parent
, node
.right_parent
);
281 for (auto &op
: node
.outports
)
282 f
<< stringf(", \"%s\", %d", log_id(op
.first
), op
.second
);
286 f
<< stringf("\n ]");
289 f
<< stringf("\n }");
291 f
<< stringf("\n}\n");
295 struct JsonBackend
: public Backend
{
296 JsonBackend() : Backend("json", "write design to a JSON file") { }
299 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
301 log(" write_json [options] [filename]\n");
303 log("Write a JSON netlist of the current design.\n");
306 log(" include AIG models for the different gate types\n");
308 log(" -compat-int\n");
309 log(" emit 32-bit or smaller fully-defined parameter values directly\n");
310 log(" as JSON numbers (for compatibility with old parsers)\n");
313 log("The general syntax of the JSON output created by this command is as follows:\n");
316 log(" \"creator\": \"Yosys <version info>\",\n");
317 log(" \"modules\": {\n");
318 log(" <module_name>: {\n");
319 log(" \"attributes\": {\n");
320 log(" <attribute_name>: <attribute_value>,\n");
323 log(" \"parameter_default_values\": {\n");
324 log(" <parameter_name>: <parameter_value>,\n");
327 log(" \"ports\": {\n");
328 log(" <port_name>: <port_details>,\n");
331 log(" \"cells\": {\n");
332 log(" <cell_name>: <cell_details>,\n");
335 log(" \"netnames\": {\n");
336 log(" <net_name>: <net_details>,\n");
341 log(" \"models\": {\n");
346 log("Where <port_details> is:\n");
349 log(" \"direction\": <\"input\" | \"output\" | \"inout\">,\n");
350 log(" \"bits\": <bit_vector>\n");
351 log(" \"offset\": <the lowest bit index in use, if non-0>\n");
352 log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
355 log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.");
356 log("They don't affect connection semantics, and are only used to preserve original");
357 log("HDL bit indexing.");
358 log("And <cell_details> is:\n");
361 log(" \"hide_name\": <1 | 0>,\n");
362 log(" \"type\": <cell_type>,\n");
363 log(" \"model\": <AIG model name, if -aig option used>,\n");
364 log(" \"parameters\": {\n");
365 log(" <parameter_name>: <parameter_value>,\n");
368 log(" \"attributes\": {\n");
369 log(" <attribute_name>: <attribute_value>,\n");
372 log(" \"port_directions\": {\n");
373 log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
376 log(" \"connections\": {\n");
377 log(" <port_name>: <bit_vector>,\n");
382 log("And <net_details> is:\n");
385 log(" \"hide_name\": <1 | 0>,\n");
386 log(" \"bits\": <bit_vector>\n");
387 log(" \"offset\": <the lowest bit index in use, if non-0>\n");
388 log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
391 log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
392 log("automatically created and is likely not of interest for a regular user.\n");
394 log("The \"port_directions\" section is only included for cells for which the\n");
395 log("interface is known.\n");
397 log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
398 log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
399 log("values referenced above are vectors of this integers. Signal bits that are\n");
400 log("connected to a constant driver are denoted as string \"0\", \"1\", \"x\", or\n");
401 log("\"z\" instead of a number.\n");
403 log("Bit vectors (including integers) are written as string holding the binary");
404 log("representation of the value. Strings are written as strings, with an appended");
405 log("blank in cases of strings of the form /[01xz]* */.\n");
407 log("For example the following Verilog code:\n");
409 log(" module test(input x, y);\n");
410 log(" (* keep *) foo #(.P(42), .Q(1337))\n");
411 log(" foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));\n");
414 log("Translates to the following JSON output:\n");
418 log(" \"creator\": \"Yosys 0.9+2406 (git sha1 fb1168d8, clang 9.0.1 -fPIC -Os)\",\n");
419 log(" \"modules\": {\n");
420 log(" \"test\": {\n");
421 log(" \"attributes\": {\n");
422 log(" \"cells_not_processed\": \"00000000000000000000000000000001\",\n");
423 log(" \"src\": \"test.v:1.1-4.10\"\n");
425 log(" \"ports\": {\n");
427 log(" \"direction\": \"input\",\n");
428 log(" \"bits\": [ 2 ]\n");
431 log(" \"direction\": \"input\",\n");
432 log(" \"bits\": [ 3 ]\n");
435 log(" \"cells\": {\n");
436 log(" \"foo_inst\": {\n");
437 log(" \"hide_name\": 0,\n");
438 log(" \"type\": \"foo\",\n");
439 log(" \"parameters\": {\n");
440 log(" \"P\": \"00000000000000000000000000101010\",\n");
441 log(" \"Q\": \"00000000000000000000010100111001\"\n");
443 log(" \"attributes\": {\n");
444 log(" \"keep\": \"00000000000000000000000000000001\",\n");
445 log(" \"module_not_derived\": \"00000000000000000000000000000001\",\n");
446 log(" \"src\": \"test.v:3.1-3.55\"\n");
448 log(" \"connections\": {\n");
449 log(" \"A\": [ 3, 2 ],\n");
450 log(" \"B\": [ 2, 3 ],\n");
451 log(" \"C\": [ 2, 2, 2, 2, \"0\", \"1\", \"0\", \"1\" ]\n");
455 log(" \"netnames\": {\n");
457 log(" \"hide_name\": 0,\n");
458 log(" \"bits\": [ 2 ],\n");
459 log(" \"attributes\": {\n");
460 log(" \"src\": \"test.v:1.19-1.20\"\n");
464 log(" \"hide_name\": 0,\n");
465 log(" \"bits\": [ 3 ],\n");
466 log(" \"attributes\": {\n");
467 log(" \"src\": \"test.v:1.22-1.23\"\n");
475 log("The models are given as And-Inverter-Graphs (AIGs) in the following form:\n");
477 log(" \"models\": {\n");
478 log(" <model_name>: [\n");
479 log(" /* 0 */ [ <node-spec> ],\n");
480 log(" /* 1 */ [ <node-spec> ],\n");
481 log(" /* 2 */ [ <node-spec> ],\n");
487 log("The following node-types may be used:\n");
489 log(" [ \"port\", <portname>, <bitindex>, <out-list> ]\n");
490 log(" - the value of the specified input port bit\n");
492 log(" [ \"nport\", <portname>, <bitindex>, <out-list> ]\n");
493 log(" - the inverted value of the specified input port bit\n");
495 log(" [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
496 log(" - the ANDed value of the specified nodes\n");
498 log(" [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
499 log(" - the inverted ANDed value of the specified nodes\n");
501 log(" [ \"true\", <out-list> ]\n");
502 log(" - the constant value 1\n");
504 log(" [ \"false\", <out-list> ]\n");
505 log(" - the constant value 0\n");
507 log("All nodes appear in topological order. I.e. only nodes with smaller indices\n");
508 log("are referenced by \"and\" and \"nand\" nodes.\n");
510 log("The optional <out-list> at the end of a node specification is a list of\n");
511 log("output portname and bitindex pairs, specifying the outputs driven by this node.\n");
513 log("For example, the following is the model for a 3-input 3-output $reduce_and cell\n");
514 log("inferred by the following code:\n");
516 log(" module test(input [2:0] in, output [2:0] out);\n");
517 log(" assign in = &out;\n");
520 log(" \"$reduce_and:3U:3\": [\n");
521 log(" /* 0 */ [ \"port\", \"A\", 0 ],\n");
522 log(" /* 1 */ [ \"port\", \"A\", 1 ],\n");
523 log(" /* 2 */ [ \"and\", 0, 1 ],\n");
524 log(" /* 3 */ [ \"port\", \"A\", 2 ],\n");
525 log(" /* 4 */ [ \"and\", 2, 3, \"Y\", 0 ],\n");
526 log(" /* 5 */ [ \"false\", \"Y\", 1, \"Y\", 2 ]\n");
529 log("Future version of Yosys might add support for additional fields in the JSON\n");
530 log("format. A program processing this format must ignore all unknown fields.\n");
533 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) override
535 bool aig_mode
= false;
536 bool compat_int_mode
= false;
539 for (argidx
= 1; argidx
< args
.size(); argidx
++)
541 if (args
[argidx
] == "-aig") {
545 if (args
[argidx
] == "-compat-int") {
546 compat_int_mode
= true;
551 extra_args(f
, filename
, args
, argidx
);
553 log_header(design
, "Executing JSON backend.\n");
555 JsonWriter
json_writer(*f
, false, aig_mode
, compat_int_mode
);
556 json_writer
.write_design(design
);
560 struct JsonPass
: public Pass
{
561 JsonPass() : Pass("json", "write design in JSON format") { }
564 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
566 log(" json [options] [selection]\n");
568 log("Write a JSON netlist of all selected objects.\n");
570 log(" -o <filename>\n");
571 log(" write to the specified file.\n");
574 log(" also include AIG models for the different gate types\n");
576 log(" -compat-int\n");
577 log(" emit 32-bit or smaller fully-defined parameter values directly\n");
578 log(" as JSON numbers (for compatibility with old parsers)\n");
580 log("See 'help write_json' for a description of the JSON format used.\n");
583 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
585 std::string filename
;
586 bool aig_mode
= false;
587 bool compat_int_mode
= false;
590 for (argidx
= 1; argidx
< args
.size(); argidx
++)
592 if (args
[argidx
] == "-o" && argidx
+1 < args
.size()) {
593 filename
= args
[++argidx
];
596 if (args
[argidx
] == "-aig") {
600 if (args
[argidx
] == "-compat-int") {
601 compat_int_mode
= true;
606 extra_args(args
, argidx
, design
);
609 std::stringstream buf
;
611 if (!filename
.empty()) {
612 rewrite_filename(filename
);
613 std::ofstream
*ff
= new std::ofstream
;
614 ff
->open(filename
.c_str(), std::ofstream::trunc
);
617 log_error("Can't open file `%s' for writing: %s\n", filename
.c_str(), strerror(errno
));
624 JsonWriter
json_writer(*f
, true, aig_mode
, compat_int_mode
);
625 json_writer
.write_design(design
);
627 if (!filename
.empty()) {
630 log("%s", buf
.str().c_str());
635 PRIVATE_NAMESPACE_END