backends/rtlil/rtlil_backend.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  A very simple and straightforward backend for the RTLIL text
  21  *  representation.
  22  *
  23  */
  24
  25 #include "rtlil_backend.h"
  26 #include "kernel/yosys.h"
  27 #include <errno.h>
  28
  29 USING_YOSYS_NAMESPACE
  30 using namespace RTLIL_BACKEND;
  31 YOSYS_NAMESPACE_BEGIN
  32
  33 void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
  34 {
  35         if (width < 0)
  36                 width = data.bits.size() - offset;
  37         if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
  38                 if (width == 32 && autoint) {
  39                         int32_t val = 0;
  40                         for (int i = 0; i < width; i++) {
  41                                 log_assert(offset+i < (int)data.bits.size());
  42                                 switch (data.bits[offset+i]) {
  43                                 case State::S0: break;
  44                                 case State::S1: val |= 1 << i; break;
  45                                 default: val = -1; break;
  46                                 }
  47                         }
  48                         if (val >= 0) {
  49                                 f << stringf("%d", val);
  50                                 return;
  51                         }
  52                 }
  53                 f << stringf("%d'", width);
  54                 for (int i = offset+width-1; i >= offset; i--) {
  55                         log_assert(i < (int)data.bits.size());
  56                         switch (data.bits[i]) {
  57                         case State::S0: f << stringf("0"); break;
  58                         case State::S1: f << stringf("1"); break;
  59                         case RTLIL::Sx: f << stringf("x"); break;
  60                         case RTLIL::Sz: f << stringf("z"); break;
  61                         case RTLIL::Sa: f << stringf("-"); break;
  62                         case RTLIL::Sm: f << stringf("m"); break;
  63                         }
  64                 }
  65         } else {
  66                 f << stringf("\"");
  67                 std::string str = data.decode_string();
  68                 for (size_t i = 0; i < str.size(); i++) {
  69                         if (str[i] == '\n')
  70                                 f << stringf("\\n");
  71                         else if (str[i] == '\t')
  72                                 f << stringf("\\t");
  73                         else if (str[i] < 32)
  74                                 f << stringf("\\%03o", str[i]);
  75                         else if (str[i] == '"')
  76                                 f << stringf("\\\"");
  77                         else if (str[i] == '\\')
  78                                 f << stringf("\\\\");
  79                         else
  80                                 f << str[i];
  81                 }
  82                 f << stringf("\"");
  83         }
  84 }
  85
  86 void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint)
  87 {
  88         if (chunk.wire == NULL) {
  89                 dump_const(f, chunk.data, chunk.width, chunk.offset, autoint);
  90         } else {
  91                 if (chunk.width == chunk.wire->width && chunk.offset == 0)
  92                         f << stringf("%s", chunk.wire->name.c_str());
  93                 else if (chunk.width == 1)
  94                         f << stringf("%s [%d]", chunk.wire->name.c_str(), chunk.offset);
  95                 else
  96                         f << stringf("%s [%d:%d]", chunk.wire->name.c_str(), chunk.offset+chunk.width-1, chunk.offset);
  97         }
  98 }
  99
 100 void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint)
 101 {
 102         if (sig.is_chunk()) {
 103                 dump_sigchunk(f, sig.as_chunk(), autoint);
 104         } else {
 105                 f << stringf("{ ");
 106                 for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
 107                         dump_sigchunk(f, *it, false);
 108                         f << stringf(" ");
 109                 }
 110                 f << stringf("}");
 111         }
 112 }
 113
 114 void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
 115 {
 116         for (auto &it : wire->attributes) {
 117                 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
 118                 dump_const(f, it.second);
 119                 f << stringf("\n");
 120         }
 121         f << stringf("%s" "wire ", indent.c_str());
 122         if (wire->width != 1)
 123                 f << stringf("width %d ", wire->width);
 124         if (wire->upto)
 125                 f << stringf("upto ");
 126         if (wire->start_offset != 0)
 127                 f << stringf("offset %d ", wire->start_offset);
 128         if (wire->port_input && !wire->port_output)
 129                 f << stringf("input %d ", wire->port_id);
 130         if (!wire->port_input && wire->port_output)
 131                 f << stringf("output %d ", wire->port_id);
 132         if (wire->port_input && wire->port_output)
 133                 f << stringf("inout %d ", wire->port_id);
 134         if (wire->is_signed)
 135                 f << stringf("signed ");
 136         f << stringf("%s\n", wire->name.c_str());
 137 }
 138
 139 void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory)
 140 {
 141         for (auto &it : memory->attributes) {
 142                 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
 143                 dump_const(f, it.second);
 144                 f << stringf("\n");
 145         }
 146         f << stringf("%s" "memory ", indent.c_str());
 147         if (memory->width != 1)
 148                 f << stringf("width %d ", memory->width);
 149         if (memory->size != 0)
 150                 f << stringf("size %d ", memory->size);
 151         if (memory->start_offset != 0)
 152                 f << stringf("offset %d ", memory->start_offset);
 153         f << stringf("%s\n", memory->name.c_str());
 154 }
 155
 156 void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
 157 {
 158         for (auto &it : cell->attributes) {
 159                 f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
 160                 dump_const(f, it.second);
 161                 f << stringf("\n");
 162         }
 163         f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
 164         for (auto &it : cell->parameters) {
 165                 f << stringf("%s  parameter%s%s %s ", indent.c_str(),
 166                                 (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
 167                                 (it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",
 168                                 it.first.c_str());
 169                 dump_const(f, it.second);
 170                 f << stringf("\n");
 171         }
 172         for (auto &it : cell->connections()) {
 173                 f << stringf("%s  connect %s ", indent.c_str(), it.first.c_str());
 174                 dump_sigspec(f, it.second);
 175                 f << stringf("\n");
 176         }
 177         f << stringf("%s" "end\n", indent.c_str());
 178 }
 179
 180 void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
 181 {
 182         for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
 183         {
 184                 f << stringf("%s" "assign ", indent.c_str());
 185                 dump_sigspec(f, it->first);
 186                 f << stringf(" ");
 187                 dump_sigspec(f, it->second);
 188                 f << stringf("\n");
 189         }
 190
 191         for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
 192                 dump_proc_switch(f, indent, *it);
 193 }
 194
 195 void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw)
 196 {
 197         for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) {
 198                 f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
 199                 dump_const(f, it->second);
 200                 f << stringf("\n");
 201         }
 202
 203         f << stringf("%s" "switch ", indent.c_str());
 204         dump_sigspec(f, sw->signal);
 205         f << stringf("\n");
 206
 207         for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
 208         {
 209                 for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) {
 210                         f << stringf("%s  attribute %s ", indent.c_str(), ait->first.c_str());
 211                         dump_const(f, ait->second);
 212                         f << stringf("\n");
 213                 }
 214                 f << stringf("%s  case ", indent.c_str());
 215                 for (size_t i = 0; i < (*it)->compare.size(); i++) {
 216                         if (i > 0)
 217                                 f << stringf(" , ");
 218                         dump_sigspec(f, (*it)->compare[i]);
 219                 }
 220                 f << stringf("\n");
 221
 222                 dump_proc_case_body(f, indent + "    ", *it);
 223         }
 224
 225         f << stringf("%s" "end\n", indent.c_str());
 226 }
 227
 228 void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy)
 229 {
 230         f << stringf("%s" "sync ", indent.c_str());
 231         switch (sy->type) {
 232         case RTLIL::ST0: f << stringf("low ");
 233         if (0) case RTLIL::ST1: f << stringf("high ");
 234         if (0) case RTLIL::STp: f << stringf("posedge ");
 235         if (0) case RTLIL::STn: f << stringf("negedge ");
 236         if (0) case RTLIL::STe: f << stringf("edge ");
 237                 dump_sigspec(f, sy->signal);
 238                 f << stringf("\n");
 239                 break;
 240         case RTLIL::STa: f << stringf("always\n"); break;
 241         case RTLIL::STg: f << stringf("global\n"); break;
 242         case RTLIL::STi: f << stringf("init\n"); break;
 243         }
 244
 245         for (auto &it: sy->actions) {
 246                 f << stringf("%s  update ", indent.c_str());
 247                 dump_sigspec(f, it.first);
 248                 f << stringf(" ");
 249                 dump_sigspec(f, it.second);
 250                 f << stringf("\n");
 251         }
 252
 253         for (auto &it: sy->mem_write_actions) {
 254                 for (auto it2 = it.attributes.begin(); it2 != it.attributes.end(); ++it2) {
 255                         f << stringf("%s  attribute %s ", indent.c_str(), it2->first.c_str());
 256                         dump_const(f, it2->second);
 257                         f << stringf("\n");
 258                 }
 259                 f << stringf("%s  memwr %s ", indent.c_str(), it.memid.c_str());
 260                 dump_sigspec(f, it.address);
 261                 f << stringf(" ");
 262                 dump_sigspec(f, it.data);
 263                 f << stringf(" ");
 264                 dump_sigspec(f, it.enable);
 265                 f << stringf(" ");
 266                 dump_const(f, it.priority_mask);
 267                 f << stringf("\n");
 268         }
 269 }
 270
 271 void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc)
 272 {
 273         for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) {
 274                 f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
 275                 dump_const(f, it->second);
 276                 f << stringf("\n");
 277         }
 278         f << stringf("%s" "process %s\n", indent.c_str(), proc->name.c_str());
 279         dump_proc_case_body(f, indent + "  ", &proc->root_case);
 280         for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
 281                 dump_proc_sync(f, indent + "  ", *it);
 282         f << stringf("%s" "end\n", indent.c_str());
 283 }
 284
 285 void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 286 {
 287         f << stringf("%s" "connect ", indent.c_str());
 288         dump_sigspec(f, left);
 289         f << stringf(" ");
 290         dump_sigspec(f, right);
 291         f << stringf("\n");
 292 }
 293
 294 void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
 295 {
 296         bool print_header = flag_m || design->selected_whole_module(module->name);
 297         bool print_body = !flag_n || !design->selected_whole_module(module->name);
 298
 299         if (print_header)
 300         {
 301                 for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) {
 302                         f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
 303                         dump_const(f, it->second);
 304                         f << stringf("\n");
 305                 }
 306
 307                 f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
 308
 309                 if (!module->avail_parameters.empty()) {
 310                         if (only_selected)
 311                                 f << stringf("\n");
 312                         for (const auto &p : module->avail_parameters) {
 313                                 const auto &it = module->parameter_default_values.find(p);
 314                                 if (it == module->parameter_default_values.end()) {
 315                                         f << stringf("%s" "  parameter %s\n", indent.c_str(), p.c_str());
 316                                 } else {
 317                                         f << stringf("%s" "  parameter %s ", indent.c_str(), p.c_str());
 318                                         dump_const(f, it->second);
 319                                         f << stringf("\n");
 320                                 }
 321                         }
 322                 }
 323         }
 324
 325         if (print_body)
 326         {
 327                 for (auto it : module->wires())
 328                         if (!only_selected || design->selected(module, it)) {
 329                                 if (only_selected)
 330                                         f << stringf("\n");
 331                                 dump_wire(f, indent + "  ", it);
 332                         }
 333
 334                 for (auto it : module->memories)
 335                         if (!only_selected || design->selected(module, it.second)) {
 336                                 if (only_selected)
 337                                         f << stringf("\n");
 338                                 dump_memory(f, indent + "  ", it.second);
 339                         }
 340
 341                 for (auto it : module->cells())
 342                         if (!only_selected || design->selected(module, it)) {
 343                                 if (only_selected)
 344                                         f << stringf("\n");
 345                                 dump_cell(f, indent + "  ", it);
 346                         }
 347
 348                 for (auto it : module->processes)
 349                         if (!only_selected || design->selected(module, it.second)) {
 350                                 if (only_selected)
 351                                         f << stringf("\n");
 352                                 dump_proc(f, indent + "  ", it.second);
 353                         }
 354
 355                 bool first_conn_line = true;
 356                 for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
 357                         bool show_conn = !only_selected;
 358                         if (only_selected) {
 359                                 RTLIL::SigSpec sigs = it->first;
 360                                 sigs.append(it->second);
 361                                 for (auto &c : sigs.chunks()) {
 362                                         if (c.wire == NULL || !design->selected(module, c.wire))
 363                                                 continue;
 364                                         show_conn = true;
 365                                 }
 366                         }
 367                         if (show_conn) {
 368                                 if (only_selected && first_conn_line)
 369                                         f << stringf("\n");
 370                                 dump_conn(f, indent + "  ", it->first, it->second);
 371                                 first_conn_line = false;
 372                         }
 373                 }
 374         }
 375
 376         if (print_header)
 377                 f << stringf("%s" "end\n", indent.c_str());
 378 }
 379
 380 void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
 381 {
 382         int init_autoidx = autoidx;
 383
 384         if (!flag_m) {
 385                 int count_selected_mods = 0;
 386                 for (auto module : design->modules()) {
 387                         if (design->selected_whole_module(module->name))
 388                                 flag_m = true;
 389                         if (design->selected(module))
 390                                 count_selected_mods++;
 391                 }
 392                 if (count_selected_mods > 1)
 393                         flag_m = true;
 394         }
 395
 396         if (!only_selected || flag_m) {
 397                 if (only_selected)
 398                         f << stringf("\n");
 399                 f << stringf("autoidx %d\n", autoidx);
 400         }
 401
 402         for (auto module : design->modules()) {
 403                 if (!only_selected || design->selected(module)) {
 404                         if (only_selected)
 405                                 f << stringf("\n");
 406                         dump_module(f, "", module, design, only_selected, flag_m, flag_n);
 407                 }
 408         }
 409
 410         log_assert(init_autoidx == autoidx);
 411 }
 412
 413 YOSYS_NAMESPACE_END
 414 PRIVATE_NAMESPACE_BEGIN
 415
 416 struct RTLILBackend : public Backend {
 417         RTLILBackend() : Backend("rtlil", "write design to RTLIL file") { }
 418         void help() override
 419         {
 420                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 421                 log("\n");
 422                 log("    write_rtlil [filename]\n");
 423                 log("\n");
 424                 log("Write the current design to an RTLIL file. (RTLIL is a text representation\n");
 425                 log("of a design in yosys's internal format.)\n");
 426                 log("\n");
 427                 log("    -selected\n");
 428                 log("        only write selected parts of the design.\n");
 429                 log("\n");
 430         }
 431         void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
 432         {
 433                 bool selected = false;
 434
 435                 log_header(design, "Executing RTLIL backend.\n");
 436
 437                 size_t argidx;
 438                 for (argidx = 1; argidx < args.size(); argidx++) {
 439                         std::string arg = args[argidx];
 440                         if (arg == "-selected") {
 441                                 selected = true;
 442                                 continue;
 443                         }
 444                         break;
 445                 }
 446                 extra_args(f, filename, args, argidx);
 447
 448                 design->sort();
 449
 450                 log("Output filename: %s\n", filename.c_str());
 451                 *f << stringf("# Generated by %s\n", yosys_version_str);
 452                 RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
 453         }
 454 } RTLILBackend;
 455
 456 struct IlangBackend : public Backend {
 457         IlangBackend() : Backend("ilang", "(deprecated) alias of write_rtlil") { }
 458         void help() override
 459         {
 460                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 461                 log("\n");
 462                 log("See `help write_rtlil`.\n");
 463                 log("\n");
 464         }
 465         void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
 466         {
 467                 RTLILBackend.execute(f, filename, args, design);
 468         }
 469 } IlangBackend;
 470
 471 struct DumpPass : public Pass {
 472         DumpPass() : Pass("dump", "print parts of the design in RTLIL format") { }
 473         void help() override
 474         {
 475                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 476                 log("\n");
 477                 log("    dump [options] [selection]\n");
 478                 log("\n");
 479                 log("Write the selected parts of the design to the console or specified file in\n");
 480                 log("RTLIL format.\n");
 481                 log("\n");
 482                 log("    -m\n");
 483                 log("        also dump the module headers, even if only parts of a single\n");
 484                 log("        module is selected\n");
 485                 log("\n");
 486                 log("    -n\n");
 487                 log("        only dump the module headers if the entire module is selected\n");
 488                 log("\n");
 489                 log("    -o <filename>\n");
 490                 log("        write to the specified file.\n");
 491                 log("\n");
 492                 log("    -a <filename>\n");
 493                 log("        like -outfile but append instead of overwrite\n");
 494                 log("\n");
 495         }
 496         void execute(std::vector<std::string> args, RTLIL::Design *design) override
 497         {
 498                 std::string filename;
 499                 bool flag_m = false, flag_n = false, append = false;
 500
 501                 size_t argidx;
 502                 for (argidx = 1; argidx < args.size(); argidx++)
 503                 {
 504                         std::string arg = args[argidx];
 505                         if ((arg == "-o" || arg == "-outfile") && argidx+1 < args.size()) {
 506                                 filename = args[++argidx];
 507                                 append = false;
 508                                 continue;
 509                         }
 510                         if ((arg == "-a" || arg == "-append") && argidx+1 < args.size()) {
 511                                 filename = args[++argidx];
 512                                 append = true;
 513                                 continue;
 514                         }
 515                         if (arg == "-m") {
 516                                 flag_m = true;
 517                                 continue;
 518                         }
 519                         if (arg == "-n") {
 520                                 flag_n = true;
 521                                 continue;
 522                         }
 523                         break;
 524                 }
 525                 extra_args(args, argidx, design);
 526
 527                 std::ostream *f;
 528                 std::stringstream buf;
 529
 530                 if (!filename.empty()) {
 531                         rewrite_filename(filename);
 532                         std::ofstream *ff = new std::ofstream;
 533                         ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
 534                         if (ff->fail()) {
 535                                 delete ff;
 536                                 log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
 537                         }
 538                         f = ff;
 539                 } else {
 540                         f = &buf;
 541                 }
 542
 543                 RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n);
 544
 545                 if (!filename.empty()) {
 546                         delete f;
 547                 } else {
 548                         log("%s", buf.str().c_str());
 549                 }
 550         }
 551 } DumpPass;
 552
 553 PRIVATE_NAMESPACE_END