5ea35c56442bab591f50c70067a7247c0a914380
2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/utils.h"
25 PRIVATE_NAMESPACE_BEGIN
27 struct HierDirtyFlags
;
34 HierDirtyFlags
*parent
;
35 pool
<SigBit
> dirty_bits
;
36 pool
<Cell
*> dirty_cells
;
37 pool
<SigBit
> sticky_dirty_bits
;
38 dict
<IdString
, HierDirtyFlags
*> children
;
40 HierDirtyFlags(Module
*module
, IdString hiername
, HierDirtyFlags
*parent
) : dirty(0), module(module
), hiername(hiername
), parent(parent
)
42 for (Cell
*cell
: module
->cells()) {
43 Module
*mod
= module
->design
->module(cell
->type
);
44 if (mod
) children
[cell
->name
] = new HierDirtyFlags(mod
, cell
->name
, this);
50 for (auto &child
: children
)
54 void set_dirty(SigBit bit
)
56 if (dirty_bits
.count(bit
))
59 dirty_bits
.insert(bit
);
60 sticky_dirty_bits
.insert(bit
);
62 HierDirtyFlags
*p
= this;
63 while (p
!= nullptr) {
69 void unset_dirty(SigBit bit
)
71 if (dirty_bits
.count(bit
) == 0)
74 dirty_bits
.erase(bit
);
76 HierDirtyFlags
*p
= this;
77 while (p
!= nullptr) {
79 log_assert(p
->dirty
>= 0);
84 void set_dirty(Cell
*cell
)
86 if (dirty_cells
.count(cell
))
89 dirty_cells
.insert(cell
);
91 HierDirtyFlags
*p
= this;
92 while (p
!= nullptr) {
98 void unset_dirty(Cell
*cell
)
100 if (dirty_cells
.count(cell
) == 0)
103 dirty_cells
.erase(cell
);
105 HierDirtyFlags
*p
= this;
106 while (p
!= nullptr) {
108 log_assert(p
->dirty
>= 0);
116 bool verbose
= false;
117 int max_uintsize
= 32;
120 dict
<Module
*, SigMap
> sigmaps
;
122 vector
<string
> signal_declarations
;
123 pool
<int> generated_sigtypes
;
125 vector
<string
> util_declarations
;
126 pool
<string
> generated_utils
;
128 vector
<string
> struct_declarations
;
129 pool
<IdString
> generated_structs
;
131 vector
<string
> funct_declarations
;
133 pool
<string
> reserved_cids
;
134 dict
<IdString
, string
> id2cid
;
136 dict
<Module
*, dict
<SigBit
, pool
<tuple
<Cell
*, IdString
, int>>>> bit2cell
;
137 dict
<Module
*, dict
<SigBit
, pool
<SigBit
>>> bit2output
;
139 dict
<Cell
*, int> topoidx
;
141 pool
<string
> activated_cells
;
142 pool
<string
> reactivated_cells
;
144 SimplecWorker(Design
*design
) : design(design
)
148 string
sigtype(int n
)
150 string struct_name
= stringf("signal%d_t", n
);
152 if (generated_sigtypes
.count(n
) == 0)
154 signal_declarations
.push_back("");
155 signal_declarations
.push_back(stringf("#ifndef YOSYS_SIMPLEC_SIGNAL%d_T", n
));
156 signal_declarations
.push_back(stringf("#define YOSYS_SIMPLEC_SIGNAL%d_T", n
));
157 signal_declarations
.push_back(stringf("typedef struct {"));
159 for (int k
= 8; k
<= max_uintsize
; k
= 2*k
)
160 if (n
<= k
&& k
<= max_uintsize
) {
161 signal_declarations
.push_back(stringf(" uint%d_t value_%d_0 : %d;", k
, n
-1, n
));
165 for (int k
= 0; k
< n
; k
+= max_uintsize
) {
166 int bits
= std::min(max_uintsize
, n
-k
);
167 signal_declarations
.push_back(stringf(" uint%d_t value_%d_%d : %d;", max_uintsize
, k
+bits
-1, k
, bits
));
171 signal_declarations
.push_back(stringf("} signal%d_t;", n
));
172 signal_declarations
.push_back(stringf("#endif"));
173 generated_sigtypes
.insert(n
);
179 void util_ifdef_guard(string s
)
181 for (int i
= 0; i
< GetSize(s
); i
++)
182 if ('a' <= s
[i
] && s
[i
] <= 'z')
185 util_declarations
.push_back("");
186 util_declarations
.push_back(stringf("#ifndef %s", s
.c_str()));
187 util_declarations
.push_back(stringf("#define %s", s
.c_str()));
190 string
util_get_bit(const string
&signame
, int n
, int idx
)
192 if (n
== 1 && idx
== 0)
193 return signame
+ ".value_0_0";
195 string util_name
= stringf("yosys_simplec_get_bit_%d_of_%d", idx
, n
);
197 if (generated_utils
.count(util_name
) == 0)
199 util_ifdef_guard(util_name
);
200 util_declarations
.push_back(stringf("static inline bool %s(const %s *sig)", util_name
.c_str(), sigtype(n
).c_str()));
201 util_declarations
.push_back(stringf("{"));
203 int word_idx
= idx
/ max_uintsize
, word_offset
= idx
% max_uintsize
;
204 string value_name
= stringf("value_%d_%d", std::min(n
-1, (word_idx
+1)*max_uintsize
-1), word_idx
*max_uintsize
);
206 util_declarations
.push_back(stringf(" return (sig->%s >> %d) & 1;", value_name
.c_str(), word_offset
));
208 util_declarations
.push_back(stringf("}"));
209 util_declarations
.push_back(stringf("#endif"));
210 generated_utils
.insert(util_name
);
213 return stringf("%s(&%s)", util_name
.c_str(), signame
.c_str());
216 string
util_set_bit(const string
&signame
, int n
, int idx
, const string
&expr
)
218 if (n
== 1 && idx
== 0)
219 return stringf(" %s.value_0_0 = %s;", signame
.c_str(), expr
.c_str());
221 string util_name
= stringf("yosys_simplec_set_bit_%d_of_%d", idx
, n
);
223 if (generated_utils
.count(util_name
) == 0)
225 util_ifdef_guard(util_name
);
226 util_declarations
.push_back(stringf("static inline void %s(%s *sig, bool value)", util_name
.c_str(), sigtype(n
).c_str()));
227 util_declarations
.push_back(stringf("{"));
229 int word_idx
= idx
/ max_uintsize
, word_offset
= idx
% max_uintsize
;
230 string value_name
= stringf("value_%d_%d", std::min(n
-1, (word_idx
+1)*max_uintsize
-1), word_idx
*max_uintsize
);
233 util_declarations
.push_back(stringf(" if (value)"));
234 util_declarations
.push_back(stringf(" sig->%s |= 1UL << %d;", value_name
.c_str(), word_offset
));
235 util_declarations
.push_back(stringf(" else"));
236 util_declarations
.push_back(stringf(" sig->%s &= ~(1UL << %d);", value_name
.c_str(), word_offset
));
238 util_declarations
.push_back(stringf(" sig->%s = (sig->%s | (uint%d_t)(value & 1) << %d) & ~((uint%d_t)((value & 1) ^ 1) << %d);",
239 value_name
.c_str(), value_name
.c_str(), max_uintsize
, word_offset
, max_uintsize
, word_offset
));
242 util_declarations
.push_back(stringf("}"));
243 util_declarations
.push_back(stringf("#endif"));
244 generated_utils
.insert(util_name
);
247 return stringf(" %s(&%s, %s);", util_name
.c_str(), signame
.c_str(), expr
.c_str());
250 string
cid(IdString id
)
252 if (id2cid
.count(id
) == 0)
255 if (GetSize(s
) < 2) log_abort();
260 if ('0' <= s
[0] && s
[0] <= '9') {
264 for (int i
= 0; i
< GetSize(s
); i
++) {
265 if ('0' <= s
[i
] && s
[i
] <= '9') continue;
266 if ('A' <= s
[i
] && s
[i
] <= 'Z') continue;
267 if ('a' <= s
[i
] && s
[i
] <= 'z') continue;
271 while (reserved_cids
.count(s
))
274 reserved_cids
.insert(s
);
278 return id2cid
.at(id
);
281 void create_module_struct(Module
*mod
)
283 if (generated_structs
.count(mod
->name
))
286 generated_structs
.insert(mod
->name
);
287 sigmaps
[mod
].set(mod
);
289 for (Wire
*w
: mod
->wires())
292 for (auto bit
: SigSpec(w
))
293 bit2output
[mod
][sigmaps
.at(mod
)(bit
)].insert(bit
);
296 for (Cell
*c
: mod
->cells())
298 for (auto &conn
: c
->connections())
300 if (!c
->input(conn
.first
))
304 for (auto bit
: sigmaps
.at(mod
)(conn
.second
))
305 bit2cell
[mod
][bit
].insert(tuple
<Cell
*, IdString
, int>(c
, conn
.first
, idx
++));
308 if (design
->module(c
->type
))
309 create_module_struct(design
->module(c
->type
));
312 TopoSort
<IdString
> topo
;
314 for (Cell
*c
: mod
->cells())
318 for (auto &conn
: c
->connections())
320 if (!c
->input(conn
.first
))
323 for (auto bit
: sigmaps
.at(mod
)(conn
.second
))
324 for (auto &it
: bit2cell
[mod
][bit
])
325 topo
.edge(c
->name
, std::get
<0>(it
)->name
);
329 topo
.analyze_loops
= false;
332 for (int i
= 0; i
< GetSize(topo
.sorted
); i
++)
333 topoidx
[mod
->cell(topo
.sorted
[i
])] = i
;
335 string ifdef_name
= stringf("yosys_simplec_%s_state_t", cid(mod
->name
).c_str());
337 for (int i
= 0; i
< GetSize(ifdef_name
); i
++)
338 if ('a' <= ifdef_name
[i
] && ifdef_name
[i
] <= 'z')
339 ifdef_name
[i
] -= 'a' - 'A';
341 struct_declarations
.push_back("");
342 struct_declarations
.push_back(stringf("#ifndef %s", ifdef_name
.c_str()));
343 struct_declarations
.push_back(stringf("#define %s", ifdef_name
.c_str()));
344 struct_declarations
.push_back(stringf("struct %s_state_t", cid(mod
->name
).c_str()));
345 struct_declarations
.push_back("{");
347 struct_declarations
.push_back(" // Input Ports");
348 for (Wire
*w
: mod
->wires())
350 struct_declarations
.push_back(stringf(" %s %s; // %s", sigtype(w
->width
).c_str(), cid(w
->name
).c_str(), log_id(w
)));
352 struct_declarations
.push_back("");
353 struct_declarations
.push_back(" // Output Ports");
354 for (Wire
*w
: mod
->wires())
355 if (!w
->port_input
&& w
->port_output
)
356 struct_declarations
.push_back(stringf(" %s %s; // %s", sigtype(w
->width
).c_str(), cid(w
->name
).c_str(), log_id(w
)));
358 struct_declarations
.push_back("");
359 struct_declarations
.push_back(" // Internal Wires");
360 for (Wire
*w
: mod
->wires())
361 if (!w
->port_input
&& !w
->port_output
)
362 struct_declarations
.push_back(stringf(" %s %s; // %s", sigtype(w
->width
).c_str(), cid(w
->name
).c_str(), log_id(w
)));
364 for (Cell
*c
: mod
->cells())
365 if (design
->module(c
->type
))
366 struct_declarations
.push_back(stringf(" struct %s_state_t %s; // %s", cid(c
->type
).c_str(), cid(c
->name
).c_str(), log_id(c
)));
368 struct_declarations
.push_back(stringf("};"));
369 struct_declarations
.push_back("#endif");
372 void eval_cell(HierDirtyFlags
*work
, const string
&prefix
, const string
&/* log_prefix */, Cell
*cell
)
374 if (cell
->type
.in("$_BUF_", "$_NOT_"))
376 SigBit a
= sigmaps
.at(work
->module
)(cell
->getPort("\\A"));
377 SigBit y
= sigmaps
.at(work
->module
)(cell
->getPort("\\Y"));
379 string a_expr
= a
.wire
? util_get_bit(prefix
+ cid(a
.wire
->name
), a
.wire
->width
, a
.offset
) : a
.data
? "1" : "0";
382 if (cell
->type
== "$_BUF_") expr
= a_expr
;
383 if (cell
->type
== "$_NOT_") expr
= "!" + a_expr
;
386 funct_declarations
.push_back(util_set_bit(prefix
+ cid(y
.wire
->name
), y
.wire
->width
, y
.offset
, expr
) +
387 stringf(" // %s (%s)", log_id(cell
), log_id(cell
->type
)));
393 if (cell
->type
.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
395 SigBit a
= sigmaps
.at(work
->module
)(cell
->getPort("\\A"));
396 SigBit b
= sigmaps
.at(work
->module
)(cell
->getPort("\\B"));
397 SigBit y
= sigmaps
.at(work
->module
)(cell
->getPort("\\Y"));
399 string a_expr
= a
.wire
? util_get_bit(prefix
+ cid(a
.wire
->name
), a
.wire
->width
, a
.offset
) : a
.data
? "1" : "0";
400 string b_expr
= b
.wire
? util_get_bit(prefix
+ cid(b
.wire
->name
), b
.wire
->width
, b
.offset
) : b
.data
? "1" : "0";
403 if (cell
->type
== "$_AND_") expr
= stringf("%s & %s", a_expr
.c_str(), b_expr
.c_str());
404 if (cell
->type
== "$_NAND_") expr
= stringf("!(%s & %s)", a_expr
.c_str(), b_expr
.c_str());
405 if (cell
->type
== "$_OR_") expr
= stringf("%s | %s", a_expr
.c_str(), b_expr
.c_str());
406 if (cell
->type
== "$_NOR_") expr
= stringf("!(%s | %s)", a_expr
.c_str(), b_expr
.c_str());
407 if (cell
->type
== "$_XOR_") expr
= stringf("%s ^ %s", a_expr
.c_str(), b_expr
.c_str());
408 if (cell
->type
== "$_XNOR_") expr
= stringf("!(%s ^ %s)", a_expr
.c_str(), b_expr
.c_str());
411 funct_declarations
.push_back(util_set_bit(prefix
+ cid(y
.wire
->name
), y
.wire
->width
, y
.offset
, expr
) +
412 stringf(" // %s (%s)", log_id(cell
), log_id(cell
->type
)));
418 if (cell
->type
.in("$_AOI3_", "$_OAI3_"))
420 SigBit a
= sigmaps
.at(work
->module
)(cell
->getPort("\\A"));
421 SigBit b
= sigmaps
.at(work
->module
)(cell
->getPort("\\B"));
422 SigBit c
= sigmaps
.at(work
->module
)(cell
->getPort("\\C"));
423 SigBit y
= sigmaps
.at(work
->module
)(cell
->getPort("\\Y"));
425 string a_expr
= a
.wire
? util_get_bit(prefix
+ cid(a
.wire
->name
), a
.wire
->width
, a
.offset
) : a
.data
? "1" : "0";
426 string b_expr
= b
.wire
? util_get_bit(prefix
+ cid(b
.wire
->name
), b
.wire
->width
, b
.offset
) : b
.data
? "1" : "0";
427 string c_expr
= c
.wire
? util_get_bit(prefix
+ cid(c
.wire
->name
), c
.wire
->width
, c
.offset
) : c
.data
? "1" : "0";
430 if (cell
->type
== "$_AOI3_") expr
= stringf("!((%s & %s) | %s)", a_expr
.c_str(), b_expr
.c_str(), c_expr
.c_str());
431 if (cell
->type
== "$_OAI3_") expr
= stringf("!((%s | %s) & %s)", a_expr
.c_str(), b_expr
.c_str(), c_expr
.c_str());
434 funct_declarations
.push_back(util_set_bit(prefix
+ cid(y
.wire
->name
), y
.wire
->width
, y
.offset
, expr
) +
435 stringf(" // %s (%s)", log_id(cell
), log_id(cell
->type
)));
441 if (cell
->type
.in("$_AOI4_", "$_OAI4_"))
443 SigBit a
= sigmaps
.at(work
->module
)(cell
->getPort("\\A"));
444 SigBit b
= sigmaps
.at(work
->module
)(cell
->getPort("\\B"));
445 SigBit c
= sigmaps
.at(work
->module
)(cell
->getPort("\\C"));
446 SigBit d
= sigmaps
.at(work
->module
)(cell
->getPort("\\D"));
447 SigBit y
= sigmaps
.at(work
->module
)(cell
->getPort("\\Y"));
449 string a_expr
= a
.wire
? util_get_bit(prefix
+ cid(a
.wire
->name
), a
.wire
->width
, a
.offset
) : a
.data
? "1" : "0";
450 string b_expr
= b
.wire
? util_get_bit(prefix
+ cid(b
.wire
->name
), b
.wire
->width
, b
.offset
) : b
.data
? "1" : "0";
451 string c_expr
= c
.wire
? util_get_bit(prefix
+ cid(c
.wire
->name
), c
.wire
->width
, c
.offset
) : c
.data
? "1" : "0";
452 string d_expr
= d
.wire
? util_get_bit(prefix
+ cid(d
.wire
->name
), d
.wire
->width
, d
.offset
) : d
.data
? "1" : "0";
455 if (cell
->type
== "$_AOI4_") expr
= stringf("!((%s & %s) | (%s & %s))", a_expr
.c_str(), b_expr
.c_str(), c_expr
.c_str(), d_expr
.c_str());
456 if (cell
->type
== "$_OAI4_") expr
= stringf("!((%s | %s) & (%s | %s))", a_expr
.c_str(), b_expr
.c_str(), c_expr
.c_str(), d_expr
.c_str());
459 funct_declarations
.push_back(util_set_bit(prefix
+ cid(y
.wire
->name
), y
.wire
->width
, y
.offset
, expr
) +
460 stringf(" // %s (%s)", log_id(cell
), log_id(cell
->type
)));
466 if (cell
->type
== "$_MUX_")
468 SigBit a
= sigmaps
.at(work
->module
)(cell
->getPort("\\A"));
469 SigBit b
= sigmaps
.at(work
->module
)(cell
->getPort("\\B"));
470 SigBit s
= sigmaps
.at(work
->module
)(cell
->getPort("\\S"));
471 SigBit y
= sigmaps
.at(work
->module
)(cell
->getPort("\\Y"));
473 string a_expr
= a
.wire
? util_get_bit(prefix
+ cid(a
.wire
->name
), a
.wire
->width
, a
.offset
) : a
.data
? "1" : "0";
474 string b_expr
= b
.wire
? util_get_bit(prefix
+ cid(b
.wire
->name
), b
.wire
->width
, b
.offset
) : b
.data
? "1" : "0";
475 string s_expr
= s
.wire
? util_get_bit(prefix
+ cid(s
.wire
->name
), s
.wire
->width
, s
.offset
) : s
.data
? "1" : "0";
476 string expr
= stringf("%s ? %s : %s", s_expr
.c_str(), b_expr
.c_str(), a_expr
.c_str());
479 funct_declarations
.push_back(util_set_bit(prefix
+ cid(y
.wire
->name
), y
.wire
->width
, y
.offset
, expr
) +
480 stringf(" // %s (%s)", log_id(cell
), log_id(cell
->type
)));
486 log_error("No C model for %s available at the moment (FIXME).\n", log_id(cell
->type
));
489 void eval_dirty(HierDirtyFlags
*work
, const string
&prefix
, const string
&log_prefix
, const string
&parent_prefix
, const string
&parent_log_prefix
)
493 if (verbose
&& (!work
->dirty_bits
.empty() || !work
->dirty_cells
.empty()))
494 log(" In %s:\n", log_prefix
.c_str());
496 while (!work
->dirty_bits
.empty() || !work
->dirty_cells
.empty())
498 if (!work
->dirty_bits
.empty())
500 SigSpec
dirtysig(work
->dirty_bits
);
501 dirtysig
.sort_and_unify();
503 for (SigChunk chunk
: dirtysig
.chunks()) {
505 log(" Propagating %s.%s[%d:%d].\n", log_prefix
.c_str(), log_id(chunk
.wire
), chunk
.offset
+chunk
.width
-1, chunk
.offset
);
506 funct_declarations
.push_back(stringf(" // Updated signal in %s: %s", log_prefix
.c_str(), log_signal(chunk
)));
509 for (SigBit bit
: dirtysig
)
511 if (bit2output
[work
->module
].count(bit
) && work
->parent
)
512 for (auto outbit
: bit2output
[work
->module
][bit
])
514 Module
*parent_mod
= work
->parent
->module
;
515 Cell
*parent_cell
= parent_mod
->cell(work
->hiername
);
517 IdString port_name
= outbit
.wire
->name
;
518 int port_offset
= outbit
.offset
;
519 SigBit parent_bit
= sigmaps
.at(parent_mod
)(parent_cell
->getPort(port_name
)[port_offset
]);
521 log_assert(bit
.wire
&& parent_bit
.wire
);
522 funct_declarations
.push_back(util_set_bit(parent_prefix
+ cid(parent_bit
.wire
->name
), parent_bit
.wire
->width
, parent_bit
.offset
,
523 util_get_bit(prefix
+ cid(bit
.wire
->name
), bit
.wire
->width
, bit
.offset
)));
524 work
->parent
->set_dirty(parent_bit
);
527 log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", log_prefix
.c_str(), log_id(bit
.wire
), bit
.offset
,
528 parent_log_prefix
.c_str(), log_id(parent_bit
.wire
), parent_bit
.offset
);
531 for (auto &port
: bit2cell
[work
->module
][bit
])
533 if (work
->children
.count(std::get
<0>(port
)->name
))
535 HierDirtyFlags
*child
= work
->children
.at(std::get
<0>(port
)->name
);
536 SigBit child_bit
= sigmaps
.at(child
->module
)(SigBit(child
->module
->wire(std::get
<1>(port
)), std::get
<2>(port
)));
537 log_assert(bit
.wire
&& child_bit
.wire
);
539 funct_declarations
.push_back(util_set_bit(prefix
+ cid(child
->hiername
) + "." + cid(child_bit
.wire
->name
),
540 child_bit
.wire
->width
, child_bit
.offset
, util_get_bit(prefix
+ cid(bit
.wire
->name
), bit
.wire
->width
, bit
.offset
)));
541 child
->set_dirty(child_bit
);
544 log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", log_prefix
.c_str(), log_id(bit
.wire
), bit
.offset
,
545 log_prefix
.c_str(), log_id(std::get
<0>(port
)), log_id(child_bit
.wire
), child_bit
.offset
);
548 log(" Marking cell %s.%s (via %s.%s[%d]).\n", log_prefix
.c_str(), log_id(std::get
<0>(port
)),
549 log_prefix
.c_str(), log_id(bit
.wire
), bit
.offset
);
550 work
->set_dirty(std::get
<0>(port
));
553 work
->unset_dirty(bit
);
557 if (!work
->dirty_cells
.empty())
559 Cell
*cell
= nullptr;
560 for (auto c
: work
->dirty_cells
)
561 if (cell
== nullptr || topoidx
.at(cell
) < topoidx
.at(c
))
564 string hiername
= log_prefix
+ "." + log_id(cell
);
567 log(" Evaluating %s (%s, best of %d).\n", hiername
.c_str(), log_id(cell
->type
), GetSize(work
->dirty_cells
));
569 if (activated_cells
.count(hiername
))
570 reactivated_cells
.insert(hiername
);
571 activated_cells
.insert(hiername
);
573 eval_cell(work
, prefix
, log_prefix
, cell
);
574 work
->unset_dirty(cell
);
578 for (auto &child
: work
->children
)
579 eval_dirty(child
.second
, prefix
+ cid(child
.first
) + ".", log_prefix
+ "." + cid(child
.first
), prefix
, log_prefix
);
583 void eval_sticky_dirty(HierDirtyFlags
*work
, const string
&prefix
, const string
&log_prefix
)
585 Module
*mod
= work
->module
;
587 for (Wire
*w
: mod
->wires())
588 for (SigBit bit
: SigSpec(w
))
590 SigBit canonical_bit
= sigmaps
.at(mod
)(bit
);
592 if (canonical_bit
== bit
)
595 if (work
->sticky_dirty_bits
.count(canonical_bit
) == 0)
598 log_assert(bit
.wire
&& canonical_bit
.wire
);
599 funct_declarations
.push_back(util_set_bit(prefix
+ cid(bit
.wire
->name
), bit
.wire
->width
, bit
.offset
,
600 util_get_bit(prefix
+ cid(canonical_bit
.wire
->name
), canonical_bit
.wire
->width
, canonical_bit
.offset
).c_str()));
603 log(" Propagating alias %s.%s[%d] -> %s.%s[%d].\n",
604 log_prefix
.c_str(), log_id(canonical_bit
.wire
), canonical_bit
.offset
,
605 log_prefix
.c_str(), log_id(bit
.wire
), bit
.offset
);
608 work
->sticky_dirty_bits
.clear();
610 for (auto &child
: work
->children
)
611 eval_sticky_dirty(child
.second
, prefix
+ cid(child
.first
) + ".", log_prefix
+ "." + cid(child
.first
));
614 void make_func(HierDirtyFlags
*work
, const string
&func_name
)
616 log("Generating function %s():\n", func_name
.c_str());
618 activated_cells
.clear();
619 reactivated_cells
.clear();
621 funct_declarations
.push_back("");
622 funct_declarations
.push_back(stringf("static void %s(struct %s_state_t *state)", func_name
.c_str(), cid(work
->module
->name
).c_str()));
623 funct_declarations
.push_back("{");
624 eval_dirty(work
, "state->", log_id(work
->module
->name
), "", "");
625 eval_sticky_dirty(work
, "state->", log_id(work
->module
->name
));
626 funct_declarations
.push_back("}");
628 log(" Activated %d cells (%d activated more than once).\n", GetSize(activated_cells
), GetSize(reactivated_cells
));
631 void make_init_func(HierDirtyFlags
* /* work */)
636 void make_eval_func(HierDirtyFlags
*work
)
638 Module
*mod
= work
->module
;
640 for (Wire
*w
: mod
->wires()) {
642 for (SigBit bit
: sigmaps
.at(mod
)(w
))
643 work
->set_dirty(bit
);
646 make_func(work
, cid(work
->module
->name
) + "_eval");
649 void make_tick_func(HierDirtyFlags
* /* work */)
654 void run(Module
*mod
)
656 create_module_struct(mod
);
658 HierDirtyFlags
work(mod
, IdString(), nullptr);
660 make_init_func(&work
);
661 make_eval_func(&work
);
662 make_tick_func(&work
);
665 void write(std::ostream
&f
)
667 f
<< "#include <stdint.h>" << std::endl
;
668 f
<< "#include <stdbool.h>" << std::endl
;
670 for (auto &line
: signal_declarations
)
671 f
<< line
<< std::endl
;
673 for (auto &line
: util_declarations
)
674 f
<< line
<< std::endl
;
676 for (auto &line
: struct_declarations
)
677 f
<< line
<< std::endl
;
679 for (auto &line
: funct_declarations
)
680 f
<< line
<< std::endl
;
684 struct SimplecBackend
: public Backend
{
685 SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
688 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
690 log(" write_simplec [options] [filename]\n");
692 log("Write simple C code for simulating the design. The C code writen can be used to\n");
693 log("simulate the design in a C environment, but the purpose of this command is to\n");
694 log("generate code that works well with C-based formal verification.\n");
697 log(" this will print the recursive walk used to export the modules.\n");
699 log(" -i8, -i16, -i32, -i64\n");
700 log(" set the maximum integer bit width to use in the generated code.\n");
702 log("THIS COMMAND IS UNDER CONSTRUCTION\n");
705 virtual void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
)
707 SimplecWorker
worker(design
);
709 log_header(design
, "Executing SIMPLEC backend.\n");
712 for (argidx
= 1; argidx
< args
.size(); argidx
++)
714 if (args
[argidx
] == "-verbose") {
715 worker
.verbose
= true;
718 if (args
[argidx
] == "-i8") {
719 worker
.max_uintsize
= 8;
722 if (args
[argidx
] == "-i16") {
723 worker
.max_uintsize
= 16;
726 if (args
[argidx
] == "-i32") {
727 worker
.max_uintsize
= 32;
730 if (args
[argidx
] == "-i64") {
731 worker
.max_uintsize
= 64;
736 extra_args(f
, filename
, args
, argidx
);
738 Module
*topmod
= design
->top_module();
740 if (topmod
== nullptr)
741 log_error("Current design has no top module.\n");
748 PRIVATE_NAMESPACE_END