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Add <modname>_init() function generator to simpleC back-end
[yosys.git] / backends / simplec / simplec.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/utils.h"
23
24 USING_YOSYS_NAMESPACE
25 PRIVATE_NAMESPACE_BEGIN
26
27 struct HierDirtyFlags;
28
29 static pool<string> reserved_cids;
30 static dict<IdString, string> id2cid;
31
32 static string cid(IdString id)
33 {
34 if (id2cid.count(id) == 0)
35 {
36 string s = id.str();
37 if (GetSize(s) < 2) log_abort();
38
39 if (s[0] == '\\')
40 s = s.substr(1);
41
42 if ('0' <= s[0] && s[0] <= '9') {
43 s = "_" + s;
44 }
45
46 for (int i = 0; i < GetSize(s); i++) {
47 if ('0' <= s[i] && s[i] <= '9') continue;
48 if ('A' <= s[i] && s[i] <= 'Z') continue;
49 if ('a' <= s[i] && s[i] <= 'z') continue;
50 s[i] = '_';
51 }
52
53 while (reserved_cids.count(s))
54 s += "_";
55
56 reserved_cids.insert(s);
57 id2cid[id] = s;
58 }
59
60 return id2cid.at(id);
61 }
62
63 struct HierDirtyFlags
64 {
65 int dirty;
66 Module *module;
67 IdString hiername;
68 HierDirtyFlags *parent;
69 pool<SigBit> dirty_bits;
70 pool<Cell*> dirty_cells;
71 pool<SigBit> sticky_dirty_bits;
72 dict<IdString, HierDirtyFlags*> children;
73 string prefix, log_prefix;
74
75 HierDirtyFlags(Module *module, IdString hiername, HierDirtyFlags *parent, const string &prefix, const string &log_prefix) :
76 dirty(0), module(module), hiername(hiername), parent(parent), prefix(prefix), log_prefix(log_prefix)
77 {
78 for (Cell *cell : module->cells()) {
79 Module *mod = module->design->module(cell->type);
80 if (mod) children[cell->name] = new HierDirtyFlags(mod, cell->name, this,
81 prefix + cid(cell->name) + ".", log_prefix + "." + prefix + log_id(cell->name));
82 }
83 }
84
85 ~HierDirtyFlags()
86 {
87 for (auto &child : children)
88 delete child.second;
89 }
90
91 void set_dirty(SigBit bit)
92 {
93 if (dirty_bits.count(bit))
94 return;
95
96 dirty_bits.insert(bit);
97 sticky_dirty_bits.insert(bit);
98
99 HierDirtyFlags *p = this;
100 while (p != nullptr) {
101 p->dirty++;
102 p = p->parent;
103 }
104 }
105
106 void unset_dirty(SigBit bit)
107 {
108 if (dirty_bits.count(bit) == 0)
109 return;
110
111 dirty_bits.erase(bit);
112
113 HierDirtyFlags *p = this;
114 while (p != nullptr) {
115 p->dirty--;
116 log_assert(p->dirty >= 0);
117 p = p->parent;
118 }
119 }
120
121 void set_dirty(Cell *cell)
122 {
123 if (dirty_cells.count(cell))
124 return;
125
126 dirty_cells.insert(cell);
127
128 HierDirtyFlags *p = this;
129 while (p != nullptr) {
130 p->dirty++;
131 p = p->parent;
132 }
133 }
134
135 void unset_dirty(Cell *cell)
136 {
137 if (dirty_cells.count(cell) == 0)
138 return;
139
140 dirty_cells.erase(cell);
141
142 HierDirtyFlags *p = this;
143 while (p != nullptr) {
144 p->dirty--;
145 log_assert(p->dirty >= 0);
146 p = p->parent;
147 }
148 }
149 };
150
151 struct SimplecWorker
152 {
153 bool verbose = false;
154 int max_uintsize = 32;
155
156 Design *design;
157 dict<Module*, SigMap> sigmaps;
158
159 vector<string> signal_declarations;
160 pool<int> generated_sigtypes;
161
162 vector<string> util_declarations;
163 pool<string> generated_utils;
164
165 vector<string> struct_declarations;
166 pool<IdString> generated_structs;
167
168 vector<string> funct_declarations;
169
170 dict<Module*, dict<SigBit, pool<tuple<Cell*, IdString, int>>>> bit2cell;
171 dict<Module*, dict<SigBit, pool<SigBit>>> bit2output;
172 dict<Module*, pool<SigBit>> driven_bits;
173
174 dict<Cell*, int> topoidx;
175
176 pool<string> activated_cells;
177 pool<string> reactivated_cells;
178
179 SimplecWorker(Design *design) : design(design)
180 {
181 }
182
183 string sigtype(int n)
184 {
185 string struct_name = stringf("signal%d_t", n);
186
187 if (generated_sigtypes.count(n) == 0)
188 {
189 signal_declarations.push_back("");
190 signal_declarations.push_back(stringf("#ifndef YOSYS_SIMPLEC_SIGNAL%d_T", n));
191 signal_declarations.push_back(stringf("#define YOSYS_SIMPLEC_SIGNAL%d_T", n));
192 signal_declarations.push_back(stringf("typedef struct {"));
193
194 for (int k = 8; k <= max_uintsize; k = 2*k)
195 if (n <= k && k <= max_uintsize) {
196 signal_declarations.push_back(stringf(" uint%d_t value_%d_0 : %d;", k, n-1, n));
197 goto end_struct;
198 }
199
200 for (int k = 0; k < n; k += max_uintsize) {
201 int bits = std::min(max_uintsize, n-k);
202 signal_declarations.push_back(stringf(" uint%d_t value_%d_%d : %d;", max_uintsize, k+bits-1, k, bits));
203 }
204
205 end_struct:
206 signal_declarations.push_back(stringf("} signal%d_t;", n));
207 signal_declarations.push_back(stringf("#endif"));
208 generated_sigtypes.insert(n);
209 }
210
211 return struct_name;
212 }
213
214 void util_ifdef_guard(string s)
215 {
216 for (int i = 0; i < GetSize(s); i++)
217 if ('a' <= s[i] && s[i] <= 'z')
218 s[i] -= 'a' - 'A';
219
220 util_declarations.push_back("");
221 util_declarations.push_back(stringf("#ifndef %s", s.c_str()));
222 util_declarations.push_back(stringf("#define %s", s.c_str()));
223 }
224
225 string util_get_bit(const string &signame, int n, int idx)
226 {
227 if (n == 1 && idx == 0)
228 return signame + ".value_0_0";
229
230 string util_name = stringf("yosys_simplec_get_bit_%d_of_%d", idx, n);
231
232 if (generated_utils.count(util_name) == 0)
233 {
234 util_ifdef_guard(util_name);
235 util_declarations.push_back(stringf("static inline bool %s(const %s *sig)", util_name.c_str(), sigtype(n).c_str()));
236 util_declarations.push_back(stringf("{"));
237
238 int word_idx = idx / max_uintsize, word_offset = idx % max_uintsize;
239 string value_name = stringf("value_%d_%d", std::min(n-1, (word_idx+1)*max_uintsize-1), word_idx*max_uintsize);
240
241 util_declarations.push_back(stringf(" return (sig->%s >> %d) & 1;", value_name.c_str(), word_offset));
242
243 util_declarations.push_back(stringf("}"));
244 util_declarations.push_back(stringf("#endif"));
245 generated_utils.insert(util_name);
246 }
247
248 return stringf("%s(&%s)", util_name.c_str(), signame.c_str());
249 }
250
251 string util_set_bit(const string &signame, int n, int idx, const string &expr)
252 {
253 if (n == 1 && idx == 0)
254 return stringf(" %s.value_0_0 = %s;", signame.c_str(), expr.c_str());
255
256 string util_name = stringf("yosys_simplec_set_bit_%d_of_%d", idx, n);
257
258 if (generated_utils.count(util_name) == 0)
259 {
260 util_ifdef_guard(util_name);
261 util_declarations.push_back(stringf("static inline void %s(%s *sig, bool value)", util_name.c_str(), sigtype(n).c_str()));
262 util_declarations.push_back(stringf("{"));
263
264 int word_idx = idx / max_uintsize, word_offset = idx % max_uintsize;
265 string value_name = stringf("value_%d_%d", std::min(n-1, (word_idx+1)*max_uintsize-1), word_idx*max_uintsize);
266
267 #if 0
268 util_declarations.push_back(stringf(" if (value)"));
269 util_declarations.push_back(stringf(" sig->%s |= 1UL << %d;", value_name.c_str(), word_offset));
270 util_declarations.push_back(stringf(" else"));
271 util_declarations.push_back(stringf(" sig->%s &= ~(1UL << %d);", value_name.c_str(), word_offset));
272 #else
273 util_declarations.push_back(stringf(" sig->%s = (sig->%s & ~((uint%d_t)1 << %d)) | ((uint%d_t)value << %d);",
274 value_name.c_str(), value_name.c_str(), max_uintsize, word_offset, max_uintsize, word_offset));
275 #endif
276
277 util_declarations.push_back(stringf("}"));
278 util_declarations.push_back(stringf("#endif"));
279 generated_utils.insert(util_name);
280 }
281
282 return stringf(" %s(&%s, %s);", util_name.c_str(), signame.c_str(), expr.c_str());
283 }
284
285 void create_module_struct(Module *mod)
286 {
287 if (generated_structs.count(mod->name))
288 return;
289
290 generated_structs.insert(mod->name);
291 sigmaps[mod].set(mod);
292
293 for (Wire *w : mod->wires())
294 {
295 if (w->port_output)
296 for (auto bit : SigSpec(w))
297 bit2output[mod][sigmaps.at(mod)(bit)].insert(bit);
298 }
299
300 for (Cell *c : mod->cells())
301 {
302 for (auto &conn : c->connections())
303 {
304 if (!c->input(conn.first)) {
305 for (auto bit : sigmaps.at(mod)(conn.second))
306 driven_bits[mod].insert(bit);
307 continue;
308 }
309
310 int idx = 0;
311 for (auto bit : sigmaps.at(mod)(conn.second))
312 bit2cell[mod][bit].insert(tuple<Cell*, IdString, int>(c, conn.first, idx++));
313 }
314
315 if (design->module(c->type))
316 create_module_struct(design->module(c->type));
317 }
318
319 TopoSort<IdString> topo;
320
321 for (Cell *c : mod->cells())
322 {
323 topo.node(c->name);
324
325 for (auto &conn : c->connections())
326 {
327 if (!c->input(conn.first))
328 continue;
329
330 for (auto bit : sigmaps.at(mod)(conn.second))
331 for (auto &it : bit2cell[mod][bit])
332 topo.edge(c->name, std::get<0>(it)->name);
333 }
334 }
335
336 topo.analyze_loops = false;
337 topo.sort();
338
339 for (int i = 0; i < GetSize(topo.sorted); i++)
340 topoidx[mod->cell(topo.sorted[i])] = i;
341
342 string ifdef_name = stringf("yosys_simplec_%s_state_t", cid(mod->name).c_str());
343
344 for (int i = 0; i < GetSize(ifdef_name); i++)
345 if ('a' <= ifdef_name[i] && ifdef_name[i] <= 'z')
346 ifdef_name[i] -= 'a' - 'A';
347
348 struct_declarations.push_back("");
349 struct_declarations.push_back(stringf("#ifndef %s", ifdef_name.c_str()));
350 struct_declarations.push_back(stringf("#define %s", ifdef_name.c_str()));
351 struct_declarations.push_back(stringf("struct %s_state_t", cid(mod->name).c_str()));
352 struct_declarations.push_back("{");
353
354 struct_declarations.push_back(" // Input Ports");
355 for (Wire *w : mod->wires())
356 if (w->port_input)
357 struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));
358
359 struct_declarations.push_back("");
360 struct_declarations.push_back(" // Output Ports");
361 for (Wire *w : mod->wires())
362 if (!w->port_input && w->port_output)
363 struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));
364
365 struct_declarations.push_back("");
366 struct_declarations.push_back(" // Internal Wires");
367 for (Wire *w : mod->wires())
368 if (!w->port_input && !w->port_output)
369 struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));
370
371 for (Cell *c : mod->cells())
372 if (design->module(c->type))
373 struct_declarations.push_back(stringf(" struct %s_state_t %s; // %s", cid(c->type).c_str(), cid(c->name).c_str(), log_id(c)));
374
375 struct_declarations.push_back(stringf("};"));
376 struct_declarations.push_back("#endif");
377 }
378
379 void eval_cell(HierDirtyFlags *work, Cell *cell)
380 {
381 if (cell->type.in("$_BUF_", "$_NOT_"))
382 {
383 SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
384 SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
385
386 string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
387 string expr;
388
389 if (cell->type == "$_BUF_") expr = a_expr;
390 if (cell->type == "$_NOT_") expr = "!" + a_expr;
391
392 log_assert(y.wire);
393 funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
394 stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));
395
396 work->set_dirty(y);
397 return;
398 }
399
400 if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
401 {
402 SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
403 SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
404 SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
405
406 string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
407 string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
408 string expr;
409
410 if (cell->type == "$_AND_") expr = stringf("%s & %s", a_expr.c_str(), b_expr.c_str());
411 if (cell->type == "$_NAND_") expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str());
412 if (cell->type == "$_OR_") expr = stringf("%s | %s", a_expr.c_str(), b_expr.c_str());
413 if (cell->type == "$_NOR_") expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str());
414 if (cell->type == "$_XOR_") expr = stringf("%s ^ %s", a_expr.c_str(), b_expr.c_str());
415 if (cell->type == "$_XNOR_") expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str());
416
417 log_assert(y.wire);
418 funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
419 stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));
420
421 work->set_dirty(y);
422 return;
423 }
424
425 if (cell->type.in("$_AOI3_", "$_OAI3_"))
426 {
427 SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
428 SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
429 SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
430 SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
431
432 string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
433 string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
434 string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
435 string expr;
436
437 if (cell->type == "$_AOI3_") expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
438 if (cell->type == "$_OAI3_") expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
439
440 log_assert(y.wire);
441 funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
442 stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));
443
444 work->set_dirty(y);
445 return;
446 }
447
448 if (cell->type.in("$_AOI4_", "$_OAI4_"))
449 {
450 SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
451 SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
452 SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
453 SigBit d = sigmaps.at(work->module)(cell->getPort("\\D"));
454 SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
455
456 string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
457 string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
458 string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
459 string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0";
460 string expr;
461
462 if (cell->type == "$_AOI4_") expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
463 if (cell->type == "$_OAI4_") expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
464
465 log_assert(y.wire);
466 funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
467 stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));
468
469 work->set_dirty(y);
470 return;
471 }
472
473 if (cell->type == "$_MUX_")
474 {
475 SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
476 SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
477 SigBit s = sigmaps.at(work->module)(cell->getPort("\\S"));
478 SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
479
480 string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
481 string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
482 string s_expr = s.wire ? util_get_bit(work->prefix + cid(s.wire->name), s.wire->width, s.offset) : s.data ? "1" : "0";
483 string expr = stringf("%s ? %s : %s", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
484
485 log_assert(y.wire);
486 funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
487 stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));
488
489 work->set_dirty(y);
490 return;
491 }
492
493 log_error("No C model for %s available at the moment (FIXME).\n", log_id(cell->type));
494 }
495
496 void eval_dirty(HierDirtyFlags *work)
497 {
498 while (work->dirty)
499 {
500 if (verbose && (!work->dirty_bits.empty() || !work->dirty_cells.empty()))
501 log(" In %s:\n", work->log_prefix.c_str());
502
503 while (!work->dirty_bits.empty() || !work->dirty_cells.empty())
504 {
505 if (!work->dirty_bits.empty())
506 {
507 SigSpec dirtysig(work->dirty_bits);
508 dirtysig.sort_and_unify();
509
510 for (SigChunk chunk : dirtysig.chunks()) {
511 if (chunk.wire == nullptr)
512 continue;
513 if (verbose)
514 log(" Propagating %s.%s[%d:%d].\n", work->log_prefix.c_str(), log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset);
515 funct_declarations.push_back(stringf(" // Updated signal in %s: %s", work->log_prefix.c_str(), log_signal(chunk)));
516 }
517
518 for (SigBit bit : dirtysig)
519 {
520 if (bit2output[work->module].count(bit) && work->parent)
521 for (auto outbit : bit2output[work->module][bit])
522 {
523 Module *parent_mod = work->parent->module;
524 Cell *parent_cell = parent_mod->cell(work->hiername);
525
526 IdString port_name = outbit.wire->name;
527 int port_offset = outbit.offset;
528 SigBit parent_bit = sigmaps.at(parent_mod)(parent_cell->getPort(port_name)[port_offset]);
529
530 log_assert(bit.wire && parent_bit.wire);
531 funct_declarations.push_back(util_set_bit(work->parent->prefix + cid(parent_bit.wire->name), parent_bit.wire->width, parent_bit.offset,
532 util_get_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset)));
533 work->parent->set_dirty(parent_bit);
534
535 if (verbose)
536 log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
537 work->parent->log_prefix.c_str(), log_id(parent_bit.wire), parent_bit.offset);
538 }
539
540 for (auto &port : bit2cell[work->module][bit])
541 {
542 if (work->children.count(std::get<0>(port)->name))
543 {
544 HierDirtyFlags *child = work->children.at(std::get<0>(port)->name);
545 SigBit child_bit = sigmaps.at(child->module)(SigBit(child->module->wire(std::get<1>(port)), std::get<2>(port)));
546 log_assert(bit.wire && child_bit.wire);
547
548 funct_declarations.push_back(util_set_bit(work->prefix + cid(child->hiername) + "." + cid(child_bit.wire->name),
549 child_bit.wire->width, child_bit.offset, util_get_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset)));
550 child->set_dirty(child_bit);
551
552 if (verbose)
553 log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
554 work->log_prefix.c_str(), log_id(std::get<0>(port)), log_id(child_bit.wire), child_bit.offset);
555 } else {
556 if (verbose)
557 log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix.c_str(), log_id(std::get<0>(port)),
558 work->log_prefix.c_str(), log_id(bit.wire), bit.offset);
559 work->set_dirty(std::get<0>(port));
560 }
561 }
562 work->unset_dirty(bit);
563 }
564 }
565
566 if (!work->dirty_cells.empty())
567 {
568 Cell *cell = nullptr;
569 for (auto c : work->dirty_cells)
570 if (cell == nullptr || topoidx.at(cell) < topoidx.at(c))
571 cell = c;
572
573 string hiername = work->log_prefix + "." + log_id(cell);
574
575 if (verbose)
576 log(" Evaluating %s (%s, best of %d).\n", hiername.c_str(), log_id(cell->type), GetSize(work->dirty_cells));
577
578 if (activated_cells.count(hiername))
579 reactivated_cells.insert(hiername);
580 activated_cells.insert(hiername);
581
582 eval_cell(work, cell);
583 work->unset_dirty(cell);
584 }
585 }
586
587 for (auto &child : work->children)
588 eval_dirty(child.second);
589 }
590 }
591
592 void eval_sticky_dirty(HierDirtyFlags *work)
593 {
594 Module *mod = work->module;
595
596 for (Wire *w : mod->wires())
597 for (SigBit bit : SigSpec(w))
598 {
599 SigBit canonical_bit = sigmaps.at(mod)(bit);
600
601 if (canonical_bit == bit)
602 continue;
603
604 if (work->sticky_dirty_bits.count(canonical_bit) == 0)
605 continue;
606
607 if (bit.wire == nullptr || canonical_bit.wire == nullptr)
608 continue;
609
610 funct_declarations.push_back(util_set_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset,
611 util_get_bit(work->prefix + cid(canonical_bit.wire->name), canonical_bit.wire->width, canonical_bit.offset).c_str()));
612
613 if (verbose)
614 log(" Propagating alias %s.%s[%d] -> %s.%s[%d].\n",
615 work->log_prefix.c_str(), log_id(canonical_bit.wire), canonical_bit.offset,
616 work->log_prefix.c_str(), log_id(bit.wire), bit.offset);
617 }
618
619 work->sticky_dirty_bits.clear();
620
621 for (auto &child : work->children)
622 eval_sticky_dirty(child.second);
623 }
624
625 void make_func(HierDirtyFlags *work, const string &func_name, const vector<string> &preamble)
626 {
627 log("Generating function %s():\n", func_name.c_str());
628
629 activated_cells.clear();
630 reactivated_cells.clear();
631
632 funct_declarations.push_back("");
633 funct_declarations.push_back(stringf("static void %s(struct %s_state_t *state)", func_name.c_str(), cid(work->module->name).c_str()));
634 funct_declarations.push_back("{");
635 for (auto &line : preamble)
636 funct_declarations.push_back(line);
637 eval_dirty(work);
638 eval_sticky_dirty(work);
639 funct_declarations.push_back("}");
640
641 log(" Activated %d cells (%d activated more than once).\n", GetSize(activated_cells), GetSize(reactivated_cells));
642 }
643
644 void eval_init(HierDirtyFlags *work, vector<string> &preamble)
645 {
646 Module *module = work->module;
647
648 for (Wire *w : module->wires())
649 {
650 if (w->attributes.count("\\init"))
651 {
652 SigSpec sig = sigmaps.at(module)(w);
653 Const val = w->attributes.at("\\init");
654 val.bits.resize(GetSize(sig), State::Sx);
655
656 for (int i = 0; i < GetSize(sig); i++)
657 if (val[i] == State::S0 || val[i] == State::S1) {
658 SigBit bit = sig[i];
659 preamble.push_back(util_set_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset, val == State::S1 ? "true" : "false"));
660 work->set_dirty(bit);
661 }
662 }
663
664 for (SigBit bit : SigSpec(w))
665 {
666 SigBit val = sigmaps.at(module)(bit);
667
668 if (val == State::S0 || val == State::S1)
669 preamble.push_back(util_set_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset, val == State::S1 ? "true" : "false"));
670
671 if (driven_bits.at(module).count(val) == 0)
672 work->set_dirty(val);
673 }
674 }
675
676 work->set_dirty(State::S0);
677 work->set_dirty(State::S1);
678
679 for (auto &child : work->children)
680 eval_init(child.second, preamble);
681 }
682
683 void make_init_func(HierDirtyFlags *work)
684 {
685 vector<string> preamble;
686 eval_init(work, preamble);
687 make_func(work, cid(work->module->name) + "_init", preamble);
688 }
689
690 void make_eval_func(HierDirtyFlags *work)
691 {
692 Module *mod = work->module;
693 vector<string> preamble;
694
695 for (Wire *w : mod->wires()) {
696 if (w->port_input)
697 for (SigBit bit : sigmaps.at(mod)(w))
698 work->set_dirty(bit);
699 }
700
701 make_func(work, cid(work->module->name) + "_eval", preamble);
702 }
703
704 void make_tick_func(HierDirtyFlags* /* work */)
705 {
706 // FIXME
707 }
708
709 void run(Module *mod)
710 {
711 create_module_struct(mod);
712
713 HierDirtyFlags work(mod, IdString(), nullptr, "state->", log_id(mod->name));
714
715 make_init_func(&work);
716 make_eval_func(&work);
717 make_tick_func(&work);
718 }
719
720 void write(std::ostream &f)
721 {
722 f << "#include <stdint.h>" << std::endl;
723 f << "#include <stdbool.h>" << std::endl;
724
725 for (auto &line : signal_declarations)
726 f << line << std::endl;
727
728 for (auto &line : util_declarations)
729 f << line << std::endl;
730
731 for (auto &line : struct_declarations)
732 f << line << std::endl;
733
734 for (auto &line : funct_declarations)
735 f << line << std::endl;
736 }
737 };
738
739 struct SimplecBackend : public Backend {
740 SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
741 virtual void help()
742 {
743 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
744 log("\n");
745 log(" write_simplec [options] [filename]\n");
746 log("\n");
747 log("Write simple C code for simulating the design. The C code writen can be used to\n");
748 log("simulate the design in a C environment, but the purpose of this command is to\n");
749 log("generate code that works well with C-based formal verification.\n");
750 log("\n");
751 log(" -verbose\n");
752 log(" this will print the recursive walk used to export the modules.\n");
753 log("\n");
754 log(" -i8, -i16, -i32, -i64\n");
755 log(" set the maximum integer bit width to use in the generated code.\n");
756 log("\n");
757 log("THIS COMMAND IS UNDER CONSTRUCTION\n");
758 log("\n");
759 }
760 virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
761 {
762 reserved_cids.clear();
763 id2cid.clear();
764
765 SimplecWorker worker(design);
766
767 log_header(design, "Executing SIMPLEC backend.\n");
768
769 size_t argidx;
770 for (argidx = 1; argidx < args.size(); argidx++)
771 {
772 if (args[argidx] == "-verbose") {
773 worker.verbose = true;
774 continue;
775 }
776 if (args[argidx] == "-i8") {
777 worker.max_uintsize = 8;
778 continue;
779 }
780 if (args[argidx] == "-i16") {
781 worker.max_uintsize = 16;
782 continue;
783 }
784 if (args[argidx] == "-i32") {
785 worker.max_uintsize = 32;
786 continue;
787 }
788 if (args[argidx] == "-i64") {
789 worker.max_uintsize = 64;
790 continue;
791 }
792 break;
793 }
794 extra_args(f, filename, args, argidx);
795
796 Module *topmod = design->top_module();
797
798 if (topmod == nullptr)
799 log_error("Current design has no top module.\n");
800
801 worker.run(topmod);
802 worker.write(*f);
803 }
804 } SimplecBackend;
805
806 PRIVATE_NAMESPACE_END