Handle sliced bits as clock inputs (fixes #2542)
[yosys.git] / backends / simplec / test00_uut.v
1 module test(input [31:0] a, b, c, output [31:0] x, y, z, w);
2 unit_x unit_x_inst (.a(a), .b(b), .c(c), .x(x));
3 unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
4 assign z = a ^ b ^ c, w = z;
5 endmodule
6
7 module unit_x(input [31:0] a, b, c, output [31:0] x);
8 assign x = (a & b) | c;
9 endmodule
10
11 module unit_y(input [31:0] a, b, c, output [31:0] y);
12 assign y = a & (b | c);
13 endmodule
14