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3e08ce37be55bef7b3cff66589a712242e8b7e99
[yosys.git] / backends / smt2 / smt2.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
25 #include <string>
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 struct Smt2Worker
31 {
32 CellTypes ct;
33 SigMap sigmap;
34 RTLIL::Module *module;
35 bool bvmode, memmode, wiresmode, verbose, statebv, statedt, forallmode;
36 dict<IdString, int> &mod_stbv_width;
37 int idcounter = 0, statebv_width = 0;
38
39 std::vector<std::string> decls, trans, hier, dtmembers;
40 std::map<RTLIL::SigBit, RTLIL::Cell*> bit_driver;
41 std::set<RTLIL::Cell*> exported_cells, hiercells, hiercells_queue;
42 pool<Cell*> recursive_cells, registers;
43
44 pool<SigBit> clock_posedge, clock_negedge;
45 vector<string> ex_state_eq, ex_input_eq;
46
47 std::map<RTLIL::SigBit, std::pair<int, int>> fcache;
48 std::map<Cell*, int> memarrays;
49 std::map<int, int> bvsizes;
50 dict<IdString, char*> ids;
51
52 const char *get_id(IdString n)
53 {
54 if (ids.count(n) == 0) {
55 std::string str = log_id(n);
56 for (int i = 0; i < GetSize(str); i++) {
57 if (str[i] == '\\')
58 str[i] = '/';
59 }
60 ids[n] = strdup(str.c_str());
61 }
62 return ids[n];
63 }
64
65 template<typename T>
66 const char *get_id(T *obj) {
67 return get_id(obj->name);
68 }
69
70 void makebits(std::string name, int width = 0, std::string comment = std::string())
71 {
72 std::string decl_str;
73
74 if (statebv)
75 {
76 if (width == 0) {
77 decl_str = stringf("(define-fun |%s| ((state |%s_s|)) Bool (= ((_ extract %d %d) state) #b1))", name.c_str(), get_id(module), statebv_width, statebv_width);
78 statebv_width += 1;
79 } else {
80 decl_str = stringf("(define-fun |%s| ((state |%s_s|)) (_ BitVec %d) ((_ extract %d %d) state))", name.c_str(), get_id(module), width, statebv_width+width-1, statebv_width);
81 statebv_width += width;
82 }
83 }
84 else if (statedt)
85 {
86 if (width == 0) {
87 decl_str = stringf(" (|%s| Bool)", name.c_str());
88 } else {
89 decl_str = stringf(" (|%s| (_ BitVec %d))", name.c_str(), width);
90 }
91 }
92 else
93 {
94 if (width == 0) {
95 decl_str = stringf("(declare-fun |%s| (|%s_s|) Bool)", name.c_str(), get_id(module));
96 } else {
97 decl_str = stringf("(declare-fun |%s| (|%s_s|) (_ BitVec %d))", name.c_str(), get_id(module), width);
98 }
99 }
100
101 if (!comment.empty())
102 decl_str += " ; " + comment;
103
104 if (statedt)
105 dtmembers.push_back(decl_str + "\n");
106 else
107 decls.push_back(decl_str + "\n");
108 }
109
110 Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose, bool statebv, bool statedt, bool forallmode,
111 dict<IdString, int> &mod_stbv_width, dict<IdString, dict<IdString, pair<bool, bool>>> &mod_clk_cache) :
112 ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode), wiresmode(wiresmode),
113 verbose(verbose), statebv(statebv), statedt(statedt), forallmode(forallmode), mod_stbv_width(mod_stbv_width)
114 {
115 pool<SigBit> noclock;
116
117 makebits(stringf("%s_is", get_id(module)));
118
119 for (auto cell : module->cells())
120 for (auto &conn : cell->connections())
121 {
122 if (GetSize(conn.second) == 0)
123 continue;
124
125 bool is_input = ct.cell_input(cell->type, conn.first);
126 bool is_output = ct.cell_output(cell->type, conn.first);
127
128 if (is_output && !is_input)
129 for (auto bit : sigmap(conn.second)) {
130 if (bit_driver.count(bit))
131 log_error("Found multiple drivers for %s.\n", log_signal(bit));
132 bit_driver[bit] = cell;
133 }
134 else if (is_output || !is_input)
135 log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
136 log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type));
137
138 if (cell->type.in("$mem") && conn.first.in("\\RD_CLK", "\\WR_CLK"))
139 {
140 SigSpec clk = sigmap(conn.second);
141 for (int i = 0; i < GetSize(clk); i++)
142 {
143 if (clk[i].wire == nullptr)
144 continue;
145
146 if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_ENABLE" : "\\WR_CLK_ENABLE")[i] != State::S1)
147 continue;
148
149 if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_POLARITY" : "\\WR_CLK_POLARITY")[i] == State::S1)
150 clock_posedge.insert(clk[i]);
151 else
152 clock_negedge.insert(clk[i]);
153 }
154 }
155 else
156 if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn.first.in("\\CLK", "\\C"))
157 {
158 bool posedge = (cell->type == "$_DFF_N_") || (cell->type == "$dff" && cell->getParam("\\CLK_POLARITY").as_bool());
159 for (auto bit : sigmap(conn.second)) {
160 if (posedge)
161 clock_posedge.insert(bit);
162 else
163 clock_negedge.insert(bit);
164 }
165 }
166 else
167 if (mod_clk_cache.count(cell->type) && mod_clk_cache.at(cell->type).count(conn.first))
168 {
169 for (auto bit : sigmap(conn.second)) {
170 if (mod_clk_cache.at(cell->type).at(conn.first).first)
171 clock_posedge.insert(bit);
172 if (mod_clk_cache.at(cell->type).at(conn.first).second)
173 clock_negedge.insert(bit);
174 }
175 }
176 else
177 {
178 for (auto bit : sigmap(conn.second))
179 noclock.insert(bit);
180 }
181 }
182
183 for (auto bit : noclock) {
184 clock_posedge.erase(bit);
185 clock_negedge.erase(bit);
186 }
187
188 for (auto wire : module->wires())
189 {
190 if (!wire->port_input || GetSize(wire) != 1)
191 continue;
192 SigBit bit = sigmap(wire);
193 if (clock_posedge.count(bit))
194 mod_clk_cache[module->name][wire->name].first = true;
195 if (clock_negedge.count(bit))
196 mod_clk_cache[module->name][wire->name].second = true;
197 }
198 }
199
200 ~Smt2Worker()
201 {
202 for (auto &it : ids)
203 free(it.second);
204 ids.clear();
205 }
206
207 const char *get_id(Module *m)
208 {
209 return get_id(m->name);
210 }
211
212 const char *get_id(Cell *c)
213 {
214 return get_id(c->name);
215 }
216
217 const char *get_id(Wire *w)
218 {
219 return get_id(w->name);
220 }
221
222 void register_bool(RTLIL::SigBit bit, int id)
223 {
224 if (verbose) log("%*s-> register_bool: %s %d\n", 2+2*GetSize(recursive_cells), "",
225 log_signal(bit), id);
226
227 sigmap.apply(bit);
228 log_assert(fcache.count(bit) == 0);
229 fcache[bit] = std::pair<int, int>(id, -1);
230 }
231
232 void register_bv(RTLIL::SigSpec sig, int id)
233 {
234 if (verbose) log("%*s-> register_bv: %s %d\n", 2+2*GetSize(recursive_cells), "",
235 log_signal(sig), id);
236
237 log_assert(bvmode);
238 sigmap.apply(sig);
239
240 log_assert(bvsizes.count(id) == 0);
241 bvsizes[id] = GetSize(sig);
242
243 for (int i = 0; i < GetSize(sig); i++) {
244 log_assert(fcache.count(sig[i]) == 0);
245 fcache[sig[i]] = std::pair<int, int>(id, i);
246 }
247 }
248
249 void register_boolvec(RTLIL::SigSpec sig, int id)
250 {
251 if (verbose) log("%*s-> register_boolvec: %s %d\n", 2+2*GetSize(recursive_cells), "",
252 log_signal(sig), id);
253
254 log_assert(bvmode);
255 sigmap.apply(sig);
256 register_bool(sig[0], id);
257
258 for (int i = 1; i < GetSize(sig); i++)
259 sigmap.add(sig[i], RTLIL::State::S0);
260 }
261
262 std::string get_bool(RTLIL::SigBit bit, const char *state_name = "state")
263 {
264 sigmap.apply(bit);
265
266 if (bit.wire == nullptr)
267 return bit == RTLIL::State::S1 ? "true" : "false";
268
269 if (bit_driver.count(bit))
270 export_cell(bit_driver.at(bit));
271 sigmap.apply(bit);
272
273 if (fcache.count(bit) == 0) {
274 if (verbose) log("%*s-> external bool: %s\n", 2+2*GetSize(recursive_cells), "",
275 log_signal(bit));
276 makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(bit));
277 register_bool(bit, idcounter++);
278 }
279
280 auto f = fcache.at(bit);
281 if (f.second >= 0)
282 return stringf("(= ((_ extract %d %d) (|%s#%d| %s)) #b1)", f.second, f.second, get_id(module), f.first, state_name);
283 return stringf("(|%s#%d| %s)", get_id(module), f.first, state_name);
284 }
285
286 std::string get_bool(RTLIL::SigSpec sig, const char *state_name = "state")
287 {
288 return get_bool(sig.as_bit(), state_name);
289 }
290
291 std::string get_bv(RTLIL::SigSpec sig, const char *state_name = "state")
292 {
293 log_assert(bvmode);
294 sigmap.apply(sig);
295
296 std::vector<std::string> subexpr;
297
298 SigSpec orig_sig;
299 while (orig_sig != sig) {
300 for (auto bit : sig)
301 if (bit_driver.count(bit))
302 export_cell(bit_driver.at(bit));
303 orig_sig = sig;
304 sigmap.apply(sig);
305 }
306
307 for (int i = 0, j = 1; i < GetSize(sig); i += j, j = 1)
308 {
309 if (sig[i].wire == nullptr) {
310 while (i+j < GetSize(sig) && sig[i+j].wire == nullptr) j++;
311 subexpr.push_back("#b");
312 for (int k = i+j-1; k >= i; k--)
313 subexpr.back() += sig[k] == RTLIL::State::S1 ? "1" : "0";
314 continue;
315 }
316
317 if (fcache.count(sig[i]) && fcache.at(sig[i]).second == -1) {
318 subexpr.push_back(stringf("(ite %s #b1 #b0)", get_bool(sig[i], state_name).c_str()));
319 continue;
320 }
321
322 if (fcache.count(sig[i])) {
323 auto t1 = fcache.at(sig[i]);
324 while (i+j < GetSize(sig)) {
325 if (fcache.count(sig[i+j]) == 0)
326 break;
327 auto t2 = fcache.at(sig[i+j]);
328 if (t1.first != t2.first)
329 break;
330 if (t1.second+j != t2.second)
331 break;
332 j++;
333 }
334 if (t1.second == 0 && j == bvsizes.at(t1.first))
335 subexpr.push_back(stringf("(|%s#%d| %s)", get_id(module), t1.first, state_name));
336 else
337 subexpr.push_back(stringf("((_ extract %d %d) (|%s#%d| %s))",
338 t1.second + j - 1, t1.second, get_id(module), t1.first, state_name));
339 continue;
340 }
341
342 std::set<RTLIL::SigBit> seen_bits = { sig[i] };
343 while (i+j < GetSize(sig) && sig[i+j].wire && !fcache.count(sig[i+j]) && !seen_bits.count(sig[i+j]))
344 seen_bits.insert(sig[i+j]), j++;
345
346 if (verbose) log("%*s-> external bv: %s\n", 2+2*GetSize(recursive_cells), "",
347 log_signal(sig.extract(i, j)));
348 for (auto bit : sig.extract(i, j))
349 log_assert(bit_driver.count(bit) == 0);
350 makebits(stringf("%s#%d", get_id(module), idcounter), j, log_signal(sig.extract(i, j)));
351 subexpr.push_back(stringf("(|%s#%d| %s)", get_id(module), idcounter, state_name));
352 register_bv(sig.extract(i, j), idcounter++);
353 }
354
355 if (GetSize(subexpr) > 1) {
356 std::string expr = "", end_str = "";
357 for (int i = GetSize(subexpr)-1; i >= 0; i--) {
358 if (i > 0) expr += " (concat", end_str += ")";
359 expr += " " + subexpr[i];
360 }
361 return expr.substr(1) + end_str;
362 } else {
363 log_assert(GetSize(subexpr) == 1);
364 return subexpr[0];
365 }
366 }
367
368 void export_gate(RTLIL::Cell *cell, std::string expr)
369 {
370 RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
371 std::string processed_expr;
372
373 for (char ch : expr) {
374 if (ch == 'A') processed_expr += get_bool(cell->getPort("\\A"));
375 else if (ch == 'B') processed_expr += get_bool(cell->getPort("\\B"));
376 else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C"));
377 else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D"));
378 else if (ch == 'S') processed_expr += get_bool(cell->getPort("\\S"));
379 else processed_expr += ch;
380 }
381
382 if (verbose)
383 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell));
384
385 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
386 get_id(module), idcounter, get_id(module), processed_expr.c_str(), log_signal(bit)));
387 register_bool(bit, idcounter++);
388 recursive_cells.erase(cell);
389 }
390
391 void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0)
392 {
393 RTLIL::SigSpec sig_a, sig_b;
394 RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
395 bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
396 int width = GetSize(sig_y);
397
398 if (type == 's' || type == 'd' || type == 'b') {
399 width = max(width, GetSize(cell->getPort("\\A")));
400 if (cell->hasPort("\\B"))
401 width = max(width, GetSize(cell->getPort("\\B")));
402 }
403
404 if (cell->hasPort("\\A")) {
405 sig_a = cell->getPort("\\A");
406 sig_a.extend_u0(width, is_signed);
407 }
408
409 if (cell->hasPort("\\B")) {
410 sig_b = cell->getPort("\\B");
411 sig_b.extend_u0(width, is_signed && !(type == 's'));
412 }
413
414 std::string processed_expr;
415
416 for (char ch : expr) {
417 if (ch == 'A') processed_expr += get_bv(sig_a);
418 else if (ch == 'B') processed_expr += get_bv(sig_b);
419 else if (ch == 'P') processed_expr += get_bv(cell->getPort("\\B"));
420 else if (ch == 'L') processed_expr += is_signed ? "a" : "l";
421 else if (ch == 'U') processed_expr += is_signed ? "s" : "u";
422 else processed_expr += ch;
423 }
424
425 if (width != GetSize(sig_y) && type != 'b')
426 processed_expr = stringf("((_ extract %d 0) %s)", GetSize(sig_y)-1, processed_expr.c_str());
427
428 if (verbose)
429 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell));
430
431 if (type == 'b') {
432 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
433 get_id(module), idcounter, get_id(module), processed_expr.c_str(), log_signal(sig_y)));
434 register_boolvec(sig_y, idcounter++);
435 } else {
436 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
437 get_id(module), idcounter, get_id(module), GetSize(sig_y), processed_expr.c_str(), log_signal(sig_y)));
438 register_bv(sig_y, idcounter++);
439 }
440
441 recursive_cells.erase(cell);
442 }
443
444 void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val)
445 {
446 RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
447 std::string processed_expr;
448
449 for (char ch : expr)
450 if (ch == 'A' || ch == 'B') {
451 RTLIL::SigSpec sig = sigmap(cell->getPort(stringf("\\%c", ch)));
452 for (auto bit : sig)
453 processed_expr += " " + get_bool(bit);
454 if (GetSize(sig) == 1)
455 processed_expr += identity_val ? " true" : " false";
456 } else
457 processed_expr += ch;
458
459 if (verbose)
460 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell));
461
462 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
463 get_id(module), idcounter, get_id(module), processed_expr.c_str(), log_signal(sig_y)));
464 register_boolvec(sig_y, idcounter++);
465 recursive_cells.erase(cell);
466 }
467
468 void export_cell(RTLIL::Cell *cell)
469 {
470 if (verbose)
471 log("%*s=> export_cell %s (%s) [%s]\n", 2+2*GetSize(recursive_cells), "",
472 log_id(cell), log_id(cell->type), exported_cells.count(cell) ? "old" : "new");
473
474 if (recursive_cells.count(cell))
475 log_error("Found logic loop in module %s! See cell %s.\n", get_id(module), get_id(cell));
476
477 if (exported_cells.count(cell))
478 return;
479
480 exported_cells.insert(cell);
481 recursive_cells.insert(cell);
482
483 if (cell->type == "$initstate")
484 {
485 SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
486 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
487 get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit)));
488 register_bool(bit, idcounter++);
489 recursive_cells.erase(cell);
490 return;
491 }
492
493 if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
494 {
495 registers.insert(cell);
496 makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort("\\Q")));
497 register_bool(cell->getPort("\\Q"), idcounter++);
498 recursive_cells.erase(cell);
499 return;
500 }
501
502 if (cell->type == "$_BUF_") return export_gate(cell, "A");
503 if (cell->type == "$_NOT_") return export_gate(cell, "(not A)");
504 if (cell->type == "$_AND_") return export_gate(cell, "(and A B)");
505 if (cell->type == "$_NAND_") return export_gate(cell, "(not (and A B))");
506 if (cell->type == "$_OR_") return export_gate(cell, "(or A B)");
507 if (cell->type == "$_NOR_") return export_gate(cell, "(not (or A B))");
508 if (cell->type == "$_XOR_") return export_gate(cell, "(xor A B)");
509 if (cell->type == "$_XNOR_") return export_gate(cell, "(not (xor A B))");
510 if (cell->type == "$_ANDNOT_") return export_gate(cell, "(and A (not B))");
511 if (cell->type == "$_ORNOT_") return export_gate(cell, "(or A (not B))");
512 if (cell->type == "$_MUX_") return export_gate(cell, "(ite S B A)");
513 if (cell->type == "$_NMUX_") return export_gate(cell, "(not (ite S B A))");
514 if (cell->type == "$_AOI3_") return export_gate(cell, "(not (or (and A B) C))");
515 if (cell->type == "$_OAI3_") return export_gate(cell, "(not (and (or A B) C))");
516 if (cell->type == "$_AOI4_") return export_gate(cell, "(not (or (and A B) (and C D)))");
517 if (cell->type == "$_OAI4_") return export_gate(cell, "(not (and (or A B) (or C D)))");
518
519 // FIXME: $lut
520
521 if (bvmode)
522 {
523 if (cell->type.in("$ff", "$dff"))
524 {
525 registers.insert(cell);
526 makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q")));
527 register_bv(cell->getPort("\\Q"), idcounter++);
528 recursive_cells.erase(cell);
529 return;
530 }
531
532 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq"))
533 {
534 registers.insert(cell);
535 string infostr = cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell);
536 if (cell->attributes.count("\\reg"))
537 infostr += " " + cell->attributes.at("\\reg").decode_string();
538 decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort("\\Y")), infostr.c_str()));
539 if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\maximize")){
540 decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
541 log("Wire %s is maximized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
542 }
543 else if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\minimize")){
544 decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
545 log("Wire %s is minimized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
546 }
547 makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y")));
548 if (cell->type == "$anyseq")
549 ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
550 register_bv(cell->getPort("\\Y"), idcounter++);
551 recursive_cells.erase(cell);
552 return;
553 }
554
555 if (cell->type == "$and") return export_bvop(cell, "(bvand A B)");
556 if (cell->type == "$or") return export_bvop(cell, "(bvor A B)");
557 if (cell->type == "$xor") return export_bvop(cell, "(bvxor A B)");
558 if (cell->type == "$xnor") return export_bvop(cell, "(bvxnor A B)");
559
560 if (cell->type == "$shl") return export_bvop(cell, "(bvshl A B)", 's');
561 if (cell->type == "$shr") return export_bvop(cell, "(bvlshr A B)", 's');
562 if (cell->type == "$sshl") return export_bvop(cell, "(bvshl A B)", 's');
563 if (cell->type == "$sshr") return export_bvop(cell, "(bvLshr A B)", 's');
564
565 if (cell->type.in("$shift", "$shiftx")) {
566 if (cell->getParam("\\B_SIGNED").as_bool()) {
567 return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
568 "(bvlshr A B) (bvlshr A (bvneg B)))",
569 GetSize(cell->getPort("\\B")), 0), 's');
570 } else {
571 return export_bvop(cell, "(bvlshr A B)", 's');
572 }
573 }
574
575 if (cell->type == "$lt") return export_bvop(cell, "(bvUlt A B)", 'b');
576 if (cell->type == "$le") return export_bvop(cell, "(bvUle A B)", 'b');
577 if (cell->type == "$ge") return export_bvop(cell, "(bvUge A B)", 'b');
578 if (cell->type == "$gt") return export_bvop(cell, "(bvUgt A B)", 'b');
579
580 if (cell->type == "$ne") return export_bvop(cell, "(distinct A B)", 'b');
581 if (cell->type == "$nex") return export_bvop(cell, "(distinct A B)", 'b');
582 if (cell->type == "$eq") return export_bvop(cell, "(= A B)", 'b');
583 if (cell->type == "$eqx") return export_bvop(cell, "(= A B)", 'b');
584
585 if (cell->type == "$not") return export_bvop(cell, "(bvnot A)");
586 if (cell->type == "$pos") return export_bvop(cell, "A");
587 if (cell->type == "$neg") return export_bvop(cell, "(bvneg A)");
588
589 if (cell->type == "$add") return export_bvop(cell, "(bvadd A B)");
590 if (cell->type == "$sub") return export_bvop(cell, "(bvsub A B)");
591 if (cell->type == "$mul") return export_bvop(cell, "(bvmul A B)");
592 if (cell->type == "$div") return export_bvop(cell, "(bvUdiv A B)", 'd');
593 if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd');
594
595 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool") &&
596 2*GetSize(cell->getPort("\\A").chunks()) < GetSize(cell->getPort("\\A"))) {
597 bool is_and = cell->type == "$reduce_and";
598 string bits(GetSize(cell->getPort("\\A")), is_and ? '1' : '0');
599 return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b');
600 }
601
602 if (cell->type == "$reduce_and") return export_reduce(cell, "(and A)", true);
603 if (cell->type == "$reduce_or") return export_reduce(cell, "(or A)", false);
604 if (cell->type == "$reduce_xor") return export_reduce(cell, "(xor A)", false);
605 if (cell->type == "$reduce_xnor") return export_reduce(cell, "(not (xor A))", false);
606 if (cell->type == "$reduce_bool") return export_reduce(cell, "(or A)", false);
607
608 if (cell->type == "$logic_not") return export_reduce(cell, "(not (or A))", false);
609 if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false);
610 if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false);
611
612 if (cell->type.in("$mux", "$pmux"))
613 {
614 int width = GetSize(cell->getPort("\\Y"));
615 std::string processed_expr = get_bv(cell->getPort("\\A"));
616
617 RTLIL::SigSpec sig_b = cell->getPort("\\B");
618 RTLIL::SigSpec sig_s = cell->getPort("\\S");
619 get_bv(sig_b);
620 get_bv(sig_s);
621
622 for (int i = 0; i < GetSize(sig_s); i++)
623 processed_expr = stringf("(ite %s %s %s)", get_bool(sig_s[i]).c_str(),
624 get_bv(sig_b.extract(i*width, width)).c_str(), processed_expr.c_str());
625
626 if (verbose)
627 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell));
628
629 RTLIL::SigSpec sig = sigmap(cell->getPort("\\Y"));
630 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
631 get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig)));
632 register_bv(sig, idcounter++);
633 recursive_cells.erase(cell);
634 return;
635 }
636
637 // FIXME: $slice $concat
638 }
639
640 if (memmode && cell->type == "$mem")
641 {
642 int arrayid = idcounter++;
643 memarrays[cell] = arrayid;
644
645 int abits = cell->getParam("\\ABITS").as_int();
646 int width = cell->getParam("\\WIDTH").as_int();
647 int rd_ports = cell->getParam("\\RD_PORTS").as_int();
648 int wr_ports = cell->getParam("\\WR_PORTS").as_int();
649
650 bool async_read = false;
651 if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
652 if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_zero())
653 log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module));
654 async_read = true;
655 }
656
657 decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", get_id(cell), abits, width, rd_ports, wr_ports, async_read ? "async" : "sync"));
658
659 string memstate;
660 if (async_read) {
661 memstate = stringf("%s#%d#final", get_id(module), arrayid);
662 } else {
663 memstate = stringf("%s#%d#0", get_id(module), arrayid);
664 }
665
666 if (statebv)
667 {
668 int mem_size = cell->getParam("\\SIZE").as_int();
669 int mem_offset = cell->getParam("\\OFFSET").as_int();
670
671 makebits(memstate, width*mem_size, get_id(cell));
672 decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n",
673 get_id(module), get_id(cell), get_id(module), width*mem_size, memstate.c_str()));
674
675 for (int i = 0; i < rd_ports; i++)
676 {
677 SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
678 SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
679 std::string addr = get_bv(addr_sig);
680
681 if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
682 log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
683 "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
684
685 decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
686 get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
687
688 std::string read_expr = "#b";
689 for (int k = 0; k < width; k++)
690 read_expr += "0";
691
692 for (int k = 0; k < mem_size; k++)
693 read_expr = stringf("(ite (= (|%s_m:R%dA %s| state) #b%s) ((_ extract %d %d) (|%s| state))\n %s)",
694 get_id(module), i, get_id(cell), Const(k+mem_offset, abits).as_string().c_str(),
695 width*(k+1)-1, width*k, memstate.c_str(), read_expr.c_str());
696
697 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d)\n %s) ; %s\n",
698 get_id(module), idcounter, get_id(module), width, read_expr.c_str(), log_signal(data_sig)));
699
700 decls.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
701 get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
702
703 register_bv(data_sig, idcounter++);
704 }
705 }
706 else
707 {
708 if (statedt)
709 dtmembers.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
710 memstate.c_str(), abits, width, get_id(cell)));
711 else
712 decls.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
713 memstate.c_str(), get_id(module), abits, width, get_id(cell)));
714
715 decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s| state))\n",
716 get_id(module), get_id(cell), get_id(module), abits, width, memstate.c_str()));
717
718 for (int i = 0; i < rd_ports; i++)
719 {
720 SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
721 SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
722 std::string addr = get_bv(addr_sig);
723
724 if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
725 log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
726 "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
727
728 decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
729 get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
730
731 decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s| state) (|%s_m:R%dA %s| state))) ; %s\n",
732 get_id(module), idcounter, get_id(module), width, memstate.c_str(), get_id(module), i, get_id(cell), log_signal(data_sig)));
733
734 decls.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
735 get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
736
737 register_bv(data_sig, idcounter++);
738 }
739 }
740
741 registers.insert(cell);
742 recursive_cells.erase(cell);
743 return;
744 }
745
746 Module *m = module->design->module(cell->type);
747
748 if (m != nullptr)
749 {
750 decls.push_back(stringf("; yosys-smt2-cell %s %s\n", get_id(cell->type), get_id(cell->name)));
751 string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
752
753 for (auto &conn : cell->connections())
754 {
755 if (GetSize(conn.second) == 0)
756 continue;
757
758 Wire *w = m->wire(conn.first);
759 SigSpec sig = sigmap(conn.second);
760
761 if (w->port_output && !w->port_input) {
762 if (GetSize(w) > 1) {
763 if (bvmode) {
764 makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(w), log_signal(sig));
765 register_bv(sig, idcounter++);
766 } else {
767 for (int i = 0; i < GetSize(w); i++) {
768 makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(sig[i]));
769 register_bool(sig[i], idcounter++);
770 }
771 }
772 } else {
773 makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(sig));
774 register_bool(sig, idcounter++);
775 }
776 }
777 }
778
779 if (statebv)
780 makebits(stringf("%s_h %s", get_id(module), get_id(cell->name)), mod_stbv_width.at(cell->type));
781 else if (statedt)
782 dtmembers.push_back(stringf(" (|%s_h %s| |%s_s|)\n",
783 get_id(module), get_id(cell->name), get_id(cell->type)));
784 else
785 decls.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
786 get_id(module), get_id(cell->name), get_id(module), get_id(cell->type)));
787
788 hiercells.insert(cell);
789 hiercells_queue.insert(cell);
790 recursive_cells.erase(cell);
791 return;
792 }
793
794 log_error("Unsupported cell type %s for cell %s.%s.\n",
795 log_id(cell->type), log_id(module), log_id(cell));
796 }
797
798 void run()
799 {
800 if (verbose) log("=> export logic driving outputs\n");
801
802 pool<SigBit> reg_bits;
803 for (auto cell : module->cells())
804 if (cell->type.in("$ff", "$dff", "$_FF_", "$_DFF_P_", "$_DFF_N_")) {
805 // not using sigmap -- we want the net directly at the dff output
806 for (auto bit : cell->getPort("\\Q"))
807 reg_bits.insert(bit);
808 }
809
810 for (auto wire : module->wires()) {
811 bool is_register = false;
812 for (auto bit : SigSpec(wire))
813 if (reg_bits.count(bit))
814 is_register = true;
815 if (wire->port_id || is_register || wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\')) {
816 RTLIL::SigSpec sig = sigmap(wire);
817 if (wire->port_input)
818 decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width));
819 if (wire->port_output)
820 decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width));
821 if (is_register)
822 decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width));
823 if (wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\'))
824 decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width));
825 if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig)))
826 decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),
827 clock_posedge.count(sig) ? " posedge" : "", clock_negedge.count(sig) ? " negedge" : ""));
828 if (bvmode && GetSize(sig) > 1) {
829 decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
830 get_id(module), get_id(wire), get_id(module), GetSize(sig), get_bv(sig).c_str()));
831 if (wire->port_input)
832 ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
833 get_id(module), get_id(wire), get_id(module), get_id(wire)));
834 } else {
835 for (int i = 0; i < GetSize(sig); i++)
836 if (GetSize(sig) > 1) {
837 decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
838 get_id(module), get_id(wire), i, get_id(module), get_bool(sig[i]).c_str()));
839 if (wire->port_input)
840 ex_input_eq.push_back(stringf(" (= (|%s_n %s %d| state) (|%s_n %s %d| other_state))",
841 get_id(module), get_id(wire), i, get_id(module), get_id(wire), i));
842 } else {
843 decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
844 get_id(module), get_id(wire), get_id(module), get_bool(sig[i]).c_str()));
845 if (wire->port_input)
846 ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
847 get_id(module), get_id(wire), get_id(module), get_id(wire)));
848 }
849 }
850 }
851 }
852
853 if (verbose) log("=> export logic associated with the initial state\n");
854
855 vector<string> init_list;
856 for (auto wire : module->wires())
857 if (wire->attributes.count("\\init")) {
858 RTLIL::SigSpec sig = sigmap(wire);
859 Const val = wire->attributes.at("\\init");
860 val.bits.resize(GetSize(sig), State::Sx);
861 if (bvmode && GetSize(sig) > 1) {
862 Const mask(State::S1, GetSize(sig));
863 bool use_mask = false;
864 for (int i = 0; i < GetSize(sig); i++)
865 if (val[i] != State::S0 && val[i] != State::S1) {
866 val[i] = State::S0;
867 mask[i] = State::S0;
868 use_mask = true;
869 }
870 if (use_mask)
871 init_list.push_back(stringf("(= (bvand %s #b%s) #b%s) ; %s", get_bv(sig).c_str(), mask.as_string().c_str(), val.as_string().c_str(), get_id(wire)));
872 else
873 init_list.push_back(stringf("(= %s #b%s) ; %s", get_bv(sig).c_str(), val.as_string().c_str(), get_id(wire)));
874 } else {
875 for (int i = 0; i < GetSize(sig); i++)
876 if (val[i] == State::S0 || val[i] == State::S1)
877 init_list.push_back(stringf("(= %s %s) ; %s", get_bool(sig[i]).c_str(), val[i] == State::S1 ? "true" : "false", get_id(wire)));
878 }
879 }
880
881 if (verbose) log("=> export logic driving asserts\n");
882
883 int assert_id = 0, assume_id = 0, cover_id = 0;
884 vector<string> assert_list, assume_list, cover_list;
885
886 for (auto cell : module->cells())
887 {
888 if (cell->type.in("$assert", "$assume", "$cover"))
889 {
890 int &id = cell->type == "$assert" ? assert_id :
891 cell->type == "$assume" ? assume_id :
892 cell->type == "$cover" ? cover_id : *(int*)nullptr;
893
894 char postfix = cell->type == "$assert" ? 'a' :
895 cell->type == "$assume" ? 'u' :
896 cell->type == "$cover" ? 'c' : 0;
897
898 string name_a = get_bool(cell->getPort("\\A"));
899 string name_en = get_bool(cell->getPort("\\EN"));
900 string infostr = (cell->name[0] == '$' && cell->attributes.count("\\src")) ? cell->attributes.at("\\src").decode_string() : get_id(cell);
901 decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str()));
902
903 if (cell->type == "$cover")
904 decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
905 get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
906 else
907 decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n",
908 get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
909
910 if (cell->type == "$assert")
911 assert_list.push_back(stringf("(|%s_a %d| state)", get_id(module), id));
912 else if (cell->type == "$assume")
913 assume_list.push_back(stringf("(|%s_u %d| state)", get_id(module), id));
914
915 id++;
916 }
917 }
918
919 if (verbose) log("=> export logic driving hierarchical cells\n");
920
921 for (auto cell : module->cells())
922 if (module->design->module(cell->type) != nullptr)
923 export_cell(cell);
924
925 while (!hiercells_queue.empty())
926 {
927 std::set<RTLIL::Cell*> queue;
928 queue.swap(hiercells_queue);
929
930 for (auto cell : queue)
931 {
932 string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
933 Module *m = module->design->module(cell->type);
934 log_assert(m != nullptr);
935
936 hier.push_back(stringf(" (= (|%s_is| state) (|%s_is| %s))\n",
937 get_id(module), get_id(cell->type), cell_state.c_str()));
938
939 for (auto &conn : cell->connections())
940 {
941 if (GetSize(conn.second) == 0)
942 continue;
943
944 Wire *w = m->wire(conn.first);
945 SigSpec sig = sigmap(conn.second);
946
947 if (bvmode || GetSize(w) == 1) {
948 hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(),
949 get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w)));
950 } else {
951 for (int i = 0; i < GetSize(w); i++)
952 hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(),
953 get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i));
954 }
955 }
956 }
957 }
958
959 for (int iter = 1; !registers.empty(); iter++)
960 {
961 pool<Cell*> this_regs;
962 this_regs.swap(registers);
963
964 if (verbose) log("=> export logic driving registers [iteration %d]\n", iter);
965
966 for (auto cell : this_regs)
967 {
968 if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
969 {
970 std::string expr_d = get_bool(cell->getPort("\\D"));
971 std::string expr_q = get_bool(cell->getPort("\\Q"), "next_state");
972 trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q"))));
973 ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort("\\Q")).c_str(), get_bool(cell->getPort("\\Q"), "other_state").c_str()));
974 }
975
976 if (cell->type.in("$ff", "$dff"))
977 {
978 std::string expr_d = get_bv(cell->getPort("\\D"));
979 std::string expr_q = get_bv(cell->getPort("\\Q"), "next_state");
980 trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q"))));
981 ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Q")).c_str(), get_bv(cell->getPort("\\Q"), "other_state").c_str()));
982 }
983
984 if (cell->type.in("$anyconst", "$allconst"))
985 {
986 std::string expr_d = get_bv(cell->getPort("\\Y"));
987 std::string expr_q = get_bv(cell->getPort("\\Y"), "next_state");
988 trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Y"))));
989 if (cell->type == "$anyconst")
990 ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Y")).c_str(), get_bv(cell->getPort("\\Y"), "other_state").c_str()));
991 }
992
993 if (cell->type == "$mem")
994 {
995 int arrayid = memarrays.at(cell);
996
997 int abits = cell->getParam("\\ABITS").as_int();
998 int width = cell->getParam("\\WIDTH").as_int();
999 int wr_ports = cell->getParam("\\WR_PORTS").as_int();
1000
1001 bool async_read = false;
1002 string initial_memstate, final_memstate;
1003
1004 if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
1005 log_assert(cell->getParam("\\WR_CLK_ENABLE").is_fully_zero());
1006 async_read = true;
1007 initial_memstate = stringf("%s#%d#0", get_id(module), arrayid);
1008 final_memstate = stringf("%s#%d#final", get_id(module), arrayid);
1009 }
1010
1011 if (statebv)
1012 {
1013 int mem_size = cell->getParam("\\SIZE").as_int();
1014 int mem_offset = cell->getParam("\\OFFSET").as_int();
1015
1016 if (async_read) {
1017 makebits(final_memstate, width*mem_size, get_id(cell));
1018 }
1019
1020 for (int i = 0; i < wr_ports; i++)
1021 {
1022 SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
1023 SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
1024 SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
1025
1026 std::string addr = get_bv(addr_sig);
1027 std::string data = get_bv(data_sig);
1028 std::string mask = get_bv(mask_sig);
1029
1030 decls.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1031 get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
1032 addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(cell));
1033
1034 decls.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1035 get_id(module), i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
1036 data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(cell));
1037
1038 decls.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1039 get_id(module), i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
1040 mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(cell));
1041
1042 std::string data_expr;
1043
1044 for (int k = mem_size-1; k >= 0; k--) {
1045 std::string new_data = stringf("(bvor (bvand %s %s) (bvand ((_ extract %d %d) (|%s#%d#%d| state)) (bvnot %s)))",
1046 data.c_str(), mask.c_str(), width*(k+1)-1, width*k, get_id(module), arrayid, i, mask.c_str());
1047 data_expr += stringf("\n (ite (= %s #b%s) %s ((_ extract %d %d) (|%s#%d#%d| state)))",
1048 addr.c_str(), Const(k+mem_offset, abits).as_string().c_str(), new_data.c_str(),
1049 width*(k+1)-1, width*k, get_id(module), arrayid, i);
1050 }
1051
1052 decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (_ BitVec %d) (concat%s)) ; %s\n",
1053 get_id(module), arrayid, i+1, get_id(module), width*mem_size, data_expr.c_str(), get_id(cell)));
1054 }
1055 }
1056 else
1057 {
1058 if (async_read) {
1059 if (statedt)
1060 dtmembers.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
1061 initial_memstate.c_str(), abits, width, get_id(cell)));
1062 else
1063 decls.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
1064 initial_memstate.c_str(), get_id(module), abits, width, get_id(cell)));
1065 }
1066
1067 for (int i = 0; i < wr_ports; i++)
1068 {
1069 SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
1070 SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
1071 SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
1072
1073 std::string addr = get_bv(addr_sig);
1074 std::string data = get_bv(data_sig);
1075 std::string mask = get_bv(mask_sig);
1076
1077 decls.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1078 get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
1079 addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(cell));
1080
1081 decls.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1082 get_id(module), i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
1083 data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(cell));
1084
1085 decls.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1086 get_id(module), i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
1087 mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(cell));
1088
1089 data = stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
1090 data.c_str(), mask.c_str(), get_id(module), arrayid, i, addr.c_str(), mask.c_str());
1091
1092 decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
1093 "(store (|%s#%d#%d| state) %s %s)) ; %s\n",
1094 get_id(module), arrayid, i+1, get_id(module), abits, width,
1095 get_id(module), arrayid, i, addr.c_str(), data.c_str(), get_id(cell)));
1096 }
1097 }
1098
1099 std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, wr_ports);
1100 std::string expr_q = stringf("(|%s#%d#0| next_state)", get_id(module), arrayid);
1101 trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell)));
1102 ex_state_eq.push_back(stringf("(= (|%s#%d#0| state) (|%s#%d#0| other_state))", get_id(module), arrayid, get_id(module), arrayid));
1103
1104 if (async_read)
1105 hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(cell)));
1106
1107 Const init_data = cell->getParam("\\INIT");
1108 int memsize = cell->getParam("\\SIZE").as_int();
1109
1110 for (int i = 0; i < memsize; i++)
1111 {
1112 if (i*width >= GetSize(init_data))
1113 break;
1114
1115 Const initword = init_data.extract(i*width, width, State::Sx);
1116 Const initmask = initword;
1117 bool gen_init_constr = false;
1118
1119 for (int k = 0; k < GetSize(initword); k++) {
1120 if (initword[k] == State::S0 || initword[k] == State::S1) {
1121 gen_init_constr = true;
1122 initmask[k] = State::S1;
1123 } else {
1124 initmask[k] = State::S0;
1125 initword[k] = State::S0;
1126 }
1127 }
1128
1129 if (gen_init_constr)
1130 {
1131 if (statebv)
1132 /* FIXME */;
1133 else
1134 init_list.push_back(stringf("(= (bvand (select (|%s#%d#0| state) #b%s) #b%s) #b%s) ; %s[%d]",
1135 get_id(module), arrayid, Const(i, abits).as_string().c_str(),
1136 initmask.as_string().c_str(), initword.as_string().c_str(), get_id(cell), i));
1137 }
1138 }
1139 }
1140 }
1141 }
1142
1143 if (verbose) log("=> finalizing SMT2 representation of %s.\n", log_id(module));
1144
1145 for (auto c : hiercells) {
1146 assert_list.push_back(stringf("(|%s_a| (|%s_h %s| state))", get_id(c->type), get_id(module), get_id(c->name)));
1147 assume_list.push_back(stringf("(|%s_u| (|%s_h %s| state))", get_id(c->type), get_id(module), get_id(c->name)));
1148 init_list.push_back(stringf("(|%s_i| (|%s_h %s| state))", get_id(c->type), get_id(module), get_id(c->name)));
1149 hier.push_back(stringf(" (|%s_h| (|%s_h %s| state))\n", get_id(c->type), get_id(module), get_id(c->name)));
1150 trans.push_back(stringf(" (|%s_t| (|%s_h %s| state) (|%s_h %s| next_state))\n",
1151 get_id(c->type), get_id(module), get_id(c->name), get_id(module), get_id(c->name)));
1152 ex_state_eq.push_back(stringf("(|%s_ex_state_eq| (|%s_h %s| state) (|%s_h %s| other_state))\n",
1153 get_id(c->type), get_id(module), get_id(c->name), get_id(module), get_id(c->name)));
1154 }
1155
1156 if (forallmode)
1157 {
1158 string expr = ex_state_eq.empty() ? "true" : "(and";
1159 if (!ex_state_eq.empty()) {
1160 if (GetSize(ex_state_eq) == 1) {
1161 expr = "\n " + ex_state_eq.front() + "\n";
1162 } else {
1163 for (auto &str : ex_state_eq)
1164 expr += stringf("\n %s", str.c_str());
1165 expr += "\n)";
1166 }
1167 }
1168 decls.push_back(stringf("(define-fun |%s_ex_state_eq| ((state |%s_s|) (other_state |%s_s|)) Bool %s)\n",
1169 get_id(module), get_id(module), get_id(module), expr.c_str()));
1170
1171 expr = ex_input_eq.empty() ? "true" : "(and";
1172 if (!ex_input_eq.empty()) {
1173 if (GetSize(ex_input_eq) == 1) {
1174 expr = "\n " + ex_input_eq.front() + "\n";
1175 } else {
1176 for (auto &str : ex_input_eq)
1177 expr += stringf("\n %s", str.c_str());
1178 expr += "\n)";
1179 }
1180 }
1181 decls.push_back(stringf("(define-fun |%s_ex_input_eq| ((state |%s_s|) (other_state |%s_s|)) Bool %s)\n",
1182 get_id(module), get_id(module), get_id(module), expr.c_str()));
1183 }
1184
1185 string assert_expr = assert_list.empty() ? "true" : "(and";
1186 if (!assert_list.empty()) {
1187 if (GetSize(assert_list) == 1) {
1188 assert_expr = "\n " + assert_list.front() + "\n";
1189 } else {
1190 for (auto &str : assert_list)
1191 assert_expr += stringf("\n %s", str.c_str());
1192 assert_expr += "\n)";
1193 }
1194 }
1195 decls.push_back(stringf("(define-fun |%s_a| ((state |%s_s|)) Bool %s)\n",
1196 get_id(module), get_id(module), assert_expr.c_str()));
1197
1198 string assume_expr = assume_list.empty() ? "true" : "(and";
1199 if (!assume_list.empty()) {
1200 if (GetSize(assume_list) == 1) {
1201 assume_expr = "\n " + assume_list.front() + "\n";
1202 } else {
1203 for (auto &str : assume_list)
1204 assume_expr += stringf("\n %s", str.c_str());
1205 assume_expr += "\n)";
1206 }
1207 }
1208 decls.push_back(stringf("(define-fun |%s_u| ((state |%s_s|)) Bool %s)\n",
1209 get_id(module), get_id(module), assume_expr.c_str()));
1210
1211 string init_expr = init_list.empty() ? "true" : "(and";
1212 if (!init_list.empty()) {
1213 if (GetSize(init_list) == 1) {
1214 init_expr = "\n " + init_list.front() + "\n";
1215 } else {
1216 for (auto &str : init_list)
1217 init_expr += stringf("\n %s", str.c_str());
1218 init_expr += "\n)";
1219 }
1220 }
1221 decls.push_back(stringf("(define-fun |%s_i| ((state |%s_s|)) Bool %s)\n",
1222 get_id(module), get_id(module), init_expr.c_str()));
1223 }
1224
1225 void write(std::ostream &f)
1226 {
1227 f << stringf("; yosys-smt2-module %s\n", get_id(module));
1228
1229 if (statebv) {
1230 f << stringf("(define-sort |%s_s| () (_ BitVec %d))\n", get_id(module), statebv_width);
1231 mod_stbv_width[module->name] = statebv_width;
1232 } else
1233 if (statedt) {
1234 f << stringf("(declare-datatype |%s_s| ((|%s_mk|\n", get_id(module), get_id(module));
1235 for (auto it : dtmembers)
1236 f << it;
1237 f << stringf(")))\n");
1238 } else
1239 f << stringf("(declare-sort |%s_s| 0)\n", get_id(module));
1240
1241 for (auto it : decls)
1242 f << it;
1243
1244 f << stringf("(define-fun |%s_h| ((state |%s_s|)) Bool ", get_id(module), get_id(module));
1245 if (GetSize(hier) > 1) {
1246 f << "(and\n";
1247 for (auto it : hier)
1248 f << it;
1249 f << "))\n";
1250 } else
1251 if (GetSize(hier) == 1)
1252 f << "\n" + hier.front() + ")\n";
1253 else
1254 f << "true)\n";
1255
1256 f << stringf("(define-fun |%s_t| ((state |%s_s|) (next_state |%s_s|)) Bool ", get_id(module), get_id(module), get_id(module));
1257 if (GetSize(trans) > 1) {
1258 f << "(and\n";
1259 for (auto it : trans)
1260 f << it;
1261 f << "))";
1262 } else
1263 if (GetSize(trans) == 1)
1264 f << "\n" + trans.front() + ")";
1265 else
1266 f << "true)";
1267 f << stringf(" ; end of module %s\n", get_id(module));
1268 }
1269 };
1270
1271 struct Smt2Backend : public Backend {
1272 Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
1273 void help() YS_OVERRIDE
1274 {
1275 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1276 log("\n");
1277 log(" write_smt2 [options] [filename]\n");
1278 log("\n");
1279 log("Write a SMT-LIBv2 [1] description of the current design. For a module with name\n");
1280 log("'<mod>' this will declare the sort '<mod>_s' (state of the module) and will\n");
1281 log("define and declare functions operating on that state.\n");
1282 log("\n");
1283 log("The following SMT2 functions are generated for a module with name '<mod>'.\n");
1284 log("Some declarations/definitions are printed with a special comment. A prover\n");
1285 log("using the SMT2 files can use those comments to collect all relevant metadata\n");
1286 log("about the design.\n");
1287 log("\n");
1288 log(" ; yosys-smt2-module <mod>\n");
1289 log(" (declare-sort |<mod>_s| 0)\n");
1290 log(" The sort representing a state of module <mod>.\n");
1291 log("\n");
1292 log(" (define-fun |<mod>_h| ((state |<mod>_s|)) Bool (...))\n");
1293 log(" This function must be asserted for each state to establish the\n");
1294 log(" design hierarchy.\n");
1295 log("\n");
1296 log(" ; yosys-smt2-input <wirename> <width>\n");
1297 log(" ; yosys-smt2-output <wirename> <width>\n");
1298 log(" ; yosys-smt2-register <wirename> <width>\n");
1299 log(" ; yosys-smt2-wire <wirename> <width>\n");
1300 log(" (define-fun |<mod>_n <wirename>| (|<mod>_s|) (_ BitVec <width>))\n");
1301 log(" (define-fun |<mod>_n <wirename>| (|<mod>_s|) Bool)\n");
1302 log(" For each port, register, and wire with the 'keep' attribute set an\n");
1303 log(" accessor function is generated. Single-bit wires are returned as Bool,\n");
1304 log(" multi-bit wires as BitVec.\n");
1305 log("\n");
1306 log(" ; yosys-smt2-cell <submod> <instancename>\n");
1307 log(" (declare-fun |<mod>_h <instancename>| (|<mod>_s|) |<submod>_s|)\n");
1308 log(" There is a function like that for each hierarchical instance. It\n");
1309 log(" returns the sort that represents the state of the sub-module that\n");
1310 log(" implements the instance.\n");
1311 log("\n");
1312 log(" (declare-fun |<mod>_is| (|<mod>_s|) Bool)\n");
1313 log(" This function must be asserted 'true' for initial states, and 'false'\n");
1314 log(" otherwise.\n");
1315 log("\n");
1316 log(" (define-fun |<mod>_i| ((state |<mod>_s|)) Bool (...))\n");
1317 log(" This function must be asserted 'true' for initial states. For\n");
1318 log(" non-initial states it must be left unconstrained.\n");
1319 log("\n");
1320 log(" (define-fun |<mod>_t| ((state |<mod>_s|) (next_state |<mod>_s|)) Bool (...))\n");
1321 log(" This function evaluates to 'true' if the states 'state' and\n");
1322 log(" 'next_state' form a valid state transition.\n");
1323 log("\n");
1324 log(" (define-fun |<mod>_a| ((state |<mod>_s|)) Bool (...))\n");
1325 log(" This function evaluates to 'true' if all assertions hold in the state.\n");
1326 log("\n");
1327 log(" (define-fun |<mod>_u| ((state |<mod>_s|)) Bool (...))\n");
1328 log(" This function evaluates to 'true' if all assumptions hold in the state.\n");
1329 log("\n");
1330 log(" ; yosys-smt2-assert <id> <filename:linenum>\n");
1331 log(" (define-fun |<mod>_a <id>| ((state |<mod>_s|)) Bool (...))\n");
1332 log(" Each $assert cell is converted into one of this functions. The function\n");
1333 log(" evaluates to 'true' if the assert statement holds in the state.\n");
1334 log("\n");
1335 log(" ; yosys-smt2-assume <id> <filename:linenum>\n");
1336 log(" (define-fun |<mod>_u <id>| ((state |<mod>_s|)) Bool (...))\n");
1337 log(" Each $assume cell is converted into one of this functions. The function\n");
1338 log(" evaluates to 'true' if the assume statement holds in the state.\n");
1339 log("\n");
1340 log(" ; yosys-smt2-cover <id> <filename:linenum>\n");
1341 log(" (define-fun |<mod>_c <id>| ((state |<mod>_s|)) Bool (...))\n");
1342 log(" Each $cover cell is converted into one of this functions. The function\n");
1343 log(" evaluates to 'true' if the cover statement is activated in the state.\n");
1344 log("\n");
1345 log("Options:\n");
1346 log("\n");
1347 log(" -verbose\n");
1348 log(" this will print the recursive walk used to export the modules.\n");
1349 log("\n");
1350 log(" -stbv\n");
1351 log(" Use a BitVec sort to represent a state instead of an uninterpreted\n");
1352 log(" sort. As a side-effect this will prevent use of arrays to model\n");
1353 log(" memories.\n");
1354 log("\n");
1355 log(" -stdt\n");
1356 log(" Use SMT-LIB 2.6 style datatypes to represent a state instead of an\n");
1357 log(" uninterpreted sort.\n");
1358 log("\n");
1359 log(" -nobv\n");
1360 log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
1361 log(" option multi-bit wires are represented using the BitVec sort and\n");
1362 log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
1363 log("\n");
1364 log(" -nomem\n");
1365 log(" disable support for memories (via ArraysEx theory). this option is\n");
1366 log(" implied by -nobv. only $mem cells without merged registers in\n");
1367 log(" read ports are supported. call \"memory\" with -nordff to make sure\n");
1368 log(" that no registers are merged into $mem read ports. '<mod>_m' functions\n");
1369 log(" will be generated for accessing the arrays that are used to represent\n");
1370 log(" memories.\n");
1371 log("\n");
1372 log(" -wires\n");
1373 log(" create '<mod>_n' functions for all public wires. by default only ports,\n");
1374 log(" registers, and wires with the 'keep' attribute are exported.\n");
1375 log("\n");
1376 log(" -tpl <template_file>\n");
1377 log(" use the given template file. the line containing only the token '%%%%'\n");
1378 log(" is replaced with the regular output of this command.\n");
1379 log("\n");
1380 log("[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David\n");
1381 log("R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf\n");
1382 log("\n");
1383 log("---------------------------------------------------------------------------\n");
1384 log("\n");
1385 log("Example:\n");
1386 log("\n");
1387 log("Consider the following module (test.v). We want to prove that the output can\n");
1388 log("never transition from a non-zero value to a zero value.\n");
1389 log("\n");
1390 log(" module test(input clk, output reg [3:0] y);\n");
1391 log(" always @(posedge clk)\n");
1392 log(" y <= (y << 1) | ^y;\n");
1393 log(" endmodule\n");
1394 log("\n");
1395 log("For this proof we create the following template (test.tpl).\n");
1396 log("\n");
1397 log(" ; we need QF_UFBV for this poof\n");
1398 log(" (set-logic QF_UFBV)\n");
1399 log("\n");
1400 log(" ; insert the auto-generated code here\n");
1401 log(" %%%%\n");
1402 log("\n");
1403 log(" ; declare two state variables s1 and s2\n");
1404 log(" (declare-fun s1 () test_s)\n");
1405 log(" (declare-fun s2 () test_s)\n");
1406 log("\n");
1407 log(" ; state s2 is the successor of state s1\n");
1408 log(" (assert (test_t s1 s2))\n");
1409 log("\n");
1410 log(" ; we are looking for a model with y non-zero in s1\n");
1411 log(" (assert (distinct (|test_n y| s1) #b0000))\n");
1412 log("\n");
1413 log(" ; we are looking for a model with y zero in s2\n");
1414 log(" (assert (= (|test_n y| s2) #b0000))\n");
1415 log("\n");
1416 log(" ; is there such a model?\n");
1417 log(" (check-sat)\n");
1418 log("\n");
1419 log("The following yosys script will create a 'test.smt2' file for our proof:\n");
1420 log("\n");
1421 log(" read_verilog test.v\n");
1422 log(" hierarchy -check; proc; opt; check -assert\n");
1423 log(" write_smt2 -bv -tpl test.tpl test.smt2\n");
1424 log("\n");
1425 log("Running 'cvc4 test.smt2' will print 'unsat' because y can never transition\n");
1426 log("from non-zero to zero in the test design.\n");
1427 log("\n");
1428 }
1429 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1430 {
1431 std::ifstream template_f;
1432 bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false;
1433 bool forallmode = false;
1434
1435 log_header(design, "Executing SMT2 backend.\n");
1436
1437 size_t argidx;
1438 for (argidx = 1; argidx < args.size(); argidx++)
1439 {
1440 if (args[argidx] == "-tpl" && argidx+1 < args.size()) {
1441 template_f.open(args[++argidx]);
1442 if (template_f.fail())
1443 log_error("Can't open template file `%s'.\n", args[argidx].c_str());
1444 continue;
1445 }
1446 if (args[argidx] == "-bv" || args[argidx] == "-mem") {
1447 log_warning("Options -bv and -mem are now the default. Support for -bv and -mem will be removed in the future.\n");
1448 continue;
1449 }
1450 if (args[argidx] == "-stbv") {
1451 statebv = true;
1452 statedt = false;
1453 continue;
1454 }
1455 if (args[argidx] == "-stdt") {
1456 statebv = false;
1457 statedt = true;
1458 continue;
1459 }
1460 if (args[argidx] == "-nobv") {
1461 bvmode = false;
1462 memmode = false;
1463 continue;
1464 }
1465 if (args[argidx] == "-nomem") {
1466 memmode = false;
1467 continue;
1468 }
1469 if (args[argidx] == "-wires") {
1470 wiresmode = true;
1471 continue;
1472 }
1473 if (args[argidx] == "-verbose") {
1474 verbose = true;
1475 continue;
1476 }
1477 break;
1478 }
1479 extra_args(f, filename, args, argidx);
1480
1481 if (template_f.is_open()) {
1482 std::string line;
1483 while (std::getline(template_f, line)) {
1484 int indent = 0;
1485 while (indent < GetSize(line) && (line[indent] == ' ' || line[indent] == '\t'))
1486 indent++;
1487 if (line.compare(indent, 2, "%%") == 0)
1488 break;
1489 *f << line << std::endl;
1490 }
1491 }
1492
1493 *f << stringf("; SMT-LIBv2 description generated by %s\n", yosys_version_str);
1494
1495 if (!bvmode)
1496 *f << stringf("; yosys-smt2-nobv\n");
1497
1498 if (!memmode)
1499 *f << stringf("; yosys-smt2-nomem\n");
1500
1501 if (statebv)
1502 *f << stringf("; yosys-smt2-stbv\n");
1503
1504 if (statedt)
1505 *f << stringf("; yosys-smt2-stdt\n");
1506
1507 std::vector<RTLIL::Module*> sorted_modules;
1508
1509 // extract module dependencies
1510 std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
1511 for (auto &mod_it : design->modules_) {
1512 module_deps[mod_it.second] = std::set<RTLIL::Module*>();
1513 for (auto &cell_it : mod_it.second->cells_)
1514 if (design->modules_.count(cell_it.second->type) > 0)
1515 module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
1516 }
1517
1518 // simple good-enough topological sort
1519 // (O(n*m) on n elements and depth m)
1520 while (module_deps.size() > 0) {
1521 size_t sorted_modules_idx = sorted_modules.size();
1522 for (auto &it : module_deps) {
1523 for (auto &dep : it.second)
1524 if (module_deps.count(dep) > 0)
1525 goto not_ready_yet;
1526 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
1527 sorted_modules.push_back(it.first);
1528 not_ready_yet:;
1529 }
1530 if (sorted_modules_idx == sorted_modules.size())
1531 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
1532 while (sorted_modules_idx < sorted_modules.size())
1533 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
1534 }
1535
1536 dict<IdString, int> mod_stbv_width;
1537 dict<IdString, dict<IdString, pair<bool, bool>>> mod_clk_cache;
1538 Module *topmod = design->top_module();
1539 std::string topmod_id;
1540
1541 for (auto module : sorted_modules)
1542 for (auto cell : module->cells())
1543 if (cell->type.in("$allconst", "$allseq"))
1544 goto found_forall;
1545 if (0) {
1546 found_forall:
1547 forallmode = true;
1548 *f << stringf("; yosys-smt2-forall\n");
1549 if (!statebv && !statedt)
1550 log_error("Forall-exists problems are only supported in -stbv or -stdt mode.\n");
1551 }
1552
1553 for (auto module : sorted_modules)
1554 {
1555 if (module->get_blackbox_attribute() || module->has_memories_warn() || module->has_processes_warn())
1556 continue;
1557
1558 log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
1559
1560 Smt2Worker worker(module, bvmode, memmode, wiresmode, verbose, statebv, statedt, forallmode, mod_stbv_width, mod_clk_cache);
1561 worker.run();
1562 worker.write(*f);
1563
1564 if (module == topmod)
1565 topmod_id = worker.get_id(module);
1566 }
1567
1568 if (topmod)
1569 *f << stringf("; yosys-smt2-topmod %s\n", topmod_id.c_str());
1570
1571 *f << stringf("; end of yosys output\n");
1572
1573 if (template_f.is_open()) {
1574 std::string line;
1575 while (std::getline(template_f, line))
1576 *f << line << std::endl;
1577 }
1578 }
1579 } Smt2Backend;
1580
1581 PRIVATE_NAMESPACE_END