2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
28 PRIVATE_NAMESPACE_BEGIN
34 RTLIL::Module
*module
;
35 bool bvmode
, memmode
, wiresmode
, verbose
, statebv
, statedt
, forallmode
;
36 dict
<IdString
, int> &mod_stbv_width
;
37 int idcounter
= 0, statebv_width
= 0;
39 std::vector
<std::string
> decls
, trans
, hier
, dtmembers
;
40 std::map
<RTLIL::SigBit
, RTLIL::Cell
*> bit_driver
;
41 std::set
<RTLIL::Cell
*> exported_cells
, hiercells
, hiercells_queue
;
42 pool
<Cell
*> recursive_cells
, registers
;
44 pool
<SigBit
> clock_posedge
, clock_negedge
;
45 vector
<string
> ex_state_eq
, ex_input_eq
;
47 std::map
<RTLIL::SigBit
, std::pair
<int, int>> fcache
;
48 std::map
<Cell
*, int> memarrays
;
49 std::map
<int, int> bvsizes
;
50 dict
<IdString
, char*> ids
;
52 const char *get_id(IdString n
)
54 if (ids
.count(n
) == 0) {
55 std::string str
= log_id(n
);
56 for (int i
= 0; i
< GetSize(str
); i
++) {
60 ids
[n
] = strdup(str
.c_str());
66 const char *get_id(T
*obj
) {
67 return get_id(obj
->name
);
70 void makebits(std::string name
, int width
= 0, std::string comment
= std::string())
77 decl_str
= stringf("(define-fun |%s| ((state |%s_s|)) Bool (= ((_ extract %d %d) state) #b1))", name
.c_str(), get_id(module
), statebv_width
, statebv_width
);
80 decl_str
= stringf("(define-fun |%s| ((state |%s_s|)) (_ BitVec %d) ((_ extract %d %d) state))", name
.c_str(), get_id(module
), width
, statebv_width
+width
-1, statebv_width
);
81 statebv_width
+= width
;
87 decl_str
= stringf(" (|%s| Bool)", name
.c_str());
89 decl_str
= stringf(" (|%s| (_ BitVec %d))", name
.c_str(), width
);
95 decl_str
= stringf("(declare-fun |%s| (|%s_s|) Bool)", name
.c_str(), get_id(module
));
97 decl_str
= stringf("(declare-fun |%s| (|%s_s|) (_ BitVec %d))", name
.c_str(), get_id(module
), width
);
101 if (!comment
.empty())
102 decl_str
+= " ; " + comment
;
105 dtmembers
.push_back(decl_str
+ "\n");
107 decls
.push_back(decl_str
+ "\n");
110 Smt2Worker(RTLIL::Module
*module
, bool bvmode
, bool memmode
, bool wiresmode
, bool verbose
, bool statebv
, bool statedt
, bool forallmode
,
111 dict
<IdString
, int> &mod_stbv_width
, dict
<IdString
, dict
<IdString
, pair
<bool, bool>>> &mod_clk_cache
) :
112 ct(module
->design
), sigmap(module
), module(module
), bvmode(bvmode
), memmode(memmode
), wiresmode(wiresmode
),
113 verbose(verbose
), statebv(statebv
), statedt(statedt
), forallmode(forallmode
), mod_stbv_width(mod_stbv_width
)
115 pool
<SigBit
> noclock
;
117 makebits(stringf("%s_is", get_id(module
)));
119 for (auto cell
: module
->cells())
120 for (auto &conn
: cell
->connections())
122 if (GetSize(conn
.second
) == 0)
125 bool is_input
= ct
.cell_input(cell
->type
, conn
.first
);
126 bool is_output
= ct
.cell_output(cell
->type
, conn
.first
);
128 if (is_output
&& !is_input
)
129 for (auto bit
: sigmap(conn
.second
)) {
130 if (bit_driver
.count(bit
))
131 log_error("Found multiple drivers for %s.\n", log_signal(bit
));
132 bit_driver
[bit
] = cell
;
134 else if (is_output
|| !is_input
)
135 log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
136 log_id(conn
.first
), log_id(module
), log_id(cell
), log_id(cell
->type
));
138 if (cell
->type
.in("$mem") && conn
.first
.in("\\RD_CLK", "\\WR_CLK"))
140 SigSpec clk
= sigmap(conn
.second
);
141 for (int i
= 0; i
< GetSize(clk
); i
++)
143 if (clk
[i
].wire
== nullptr)
146 if (cell
->getParam(conn
.first
== "\\RD_CLK" ? "\\RD_CLK_ENABLE" : "\\WR_CLK_ENABLE")[i
] != State::S1
)
149 if (cell
->getParam(conn
.first
== "\\RD_CLK" ? "\\RD_CLK_POLARITY" : "\\WR_CLK_POLARITY")[i
] == State::S1
)
150 clock_posedge
.insert(clk
[i
]);
152 clock_negedge
.insert(clk
[i
]);
156 if (cell
->type
.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn
.first
.in("\\CLK", "\\C"))
158 bool posedge
= (cell
->type
== "$_DFF_N_") || (cell
->type
== "$dff" && cell
->getParam("\\CLK_POLARITY").as_bool());
159 for (auto bit
: sigmap(conn
.second
)) {
161 clock_posedge
.insert(bit
);
163 clock_negedge
.insert(bit
);
167 if (mod_clk_cache
.count(cell
->type
) && mod_clk_cache
.at(cell
->type
).count(conn
.first
))
169 for (auto bit
: sigmap(conn
.second
)) {
170 if (mod_clk_cache
.at(cell
->type
).at(conn
.first
).first
)
171 clock_posedge
.insert(bit
);
172 if (mod_clk_cache
.at(cell
->type
).at(conn
.first
).second
)
173 clock_negedge
.insert(bit
);
178 for (auto bit
: sigmap(conn
.second
))
183 for (auto bit
: noclock
) {
184 clock_posedge
.erase(bit
);
185 clock_negedge
.erase(bit
);
188 for (auto wire
: module
->wires())
190 if (!wire
->port_input
|| GetSize(wire
) != 1)
192 SigBit bit
= sigmap(wire
);
193 if (clock_posedge
.count(bit
))
194 mod_clk_cache
[module
->name
][wire
->name
].first
= true;
195 if (clock_negedge
.count(bit
))
196 mod_clk_cache
[module
->name
][wire
->name
].second
= true;
207 const char *get_id(Module
*m
)
209 return get_id(m
->name
);
212 const char *get_id(Cell
*c
)
214 return get_id(c
->name
);
217 const char *get_id(Wire
*w
)
219 return get_id(w
->name
);
222 void register_bool(RTLIL::SigBit bit
, int id
)
224 if (verbose
) log("%*s-> register_bool: %s %d\n", 2+2*GetSize(recursive_cells
), "",
225 log_signal(bit
), id
);
228 log_assert(fcache
.count(bit
) == 0);
229 fcache
[bit
] = std::pair
<int, int>(id
, -1);
232 void register_bv(RTLIL::SigSpec sig
, int id
)
234 if (verbose
) log("%*s-> register_bv: %s %d\n", 2+2*GetSize(recursive_cells
), "",
235 log_signal(sig
), id
);
240 log_assert(bvsizes
.count(id
) == 0);
241 bvsizes
[id
] = GetSize(sig
);
243 for (int i
= 0; i
< GetSize(sig
); i
++) {
244 log_assert(fcache
.count(sig
[i
]) == 0);
245 fcache
[sig
[i
]] = std::pair
<int, int>(id
, i
);
249 void register_boolvec(RTLIL::SigSpec sig
, int id
)
251 if (verbose
) log("%*s-> register_boolvec: %s %d\n", 2+2*GetSize(recursive_cells
), "",
252 log_signal(sig
), id
);
256 register_bool(sig
[0], id
);
258 for (int i
= 1; i
< GetSize(sig
); i
++)
259 sigmap
.add(sig
[i
], RTLIL::State::S0
);
262 std::string
get_bool(RTLIL::SigBit bit
, const char *state_name
= "state")
266 if (bit
.wire
== nullptr)
267 return bit
== RTLIL::State::S1
? "true" : "false";
269 if (bit_driver
.count(bit
))
270 export_cell(bit_driver
.at(bit
));
273 if (fcache
.count(bit
) == 0) {
274 if (verbose
) log("%*s-> external bool: %s\n", 2+2*GetSize(recursive_cells
), "",
276 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(bit
));
277 register_bool(bit
, idcounter
++);
280 auto f
= fcache
.at(bit
);
282 return stringf("(= ((_ extract %d %d) (|%s#%d| %s)) #b1)", f
.second
, f
.second
, get_id(module
), f
.first
, state_name
);
283 return stringf("(|%s#%d| %s)", get_id(module
), f
.first
, state_name
);
286 std::string
get_bool(RTLIL::SigSpec sig
, const char *state_name
= "state")
288 return get_bool(sig
.as_bit(), state_name
);
291 std::string
get_bv(RTLIL::SigSpec sig
, const char *state_name
= "state")
296 std::vector
<std::string
> subexpr
;
299 while (orig_sig
!= sig
) {
301 if (bit_driver
.count(bit
))
302 export_cell(bit_driver
.at(bit
));
307 for (int i
= 0, j
= 1; i
< GetSize(sig
); i
+= j
, j
= 1)
309 if (sig
[i
].wire
== nullptr) {
310 while (i
+j
< GetSize(sig
) && sig
[i
+j
].wire
== nullptr) j
++;
311 subexpr
.push_back("#b");
312 for (int k
= i
+j
-1; k
>= i
; k
--)
313 subexpr
.back() += sig
[k
] == RTLIL::State::S1
? "1" : "0";
317 if (fcache
.count(sig
[i
]) && fcache
.at(sig
[i
]).second
== -1) {
318 subexpr
.push_back(stringf("(ite %s #b1 #b0)", get_bool(sig
[i
], state_name
).c_str()));
322 if (fcache
.count(sig
[i
])) {
323 auto t1
= fcache
.at(sig
[i
]);
324 while (i
+j
< GetSize(sig
)) {
325 if (fcache
.count(sig
[i
+j
]) == 0)
327 auto t2
= fcache
.at(sig
[i
+j
]);
328 if (t1
.first
!= t2
.first
)
330 if (t1
.second
+j
!= t2
.second
)
334 if (t1
.second
== 0 && j
== bvsizes
.at(t1
.first
))
335 subexpr
.push_back(stringf("(|%s#%d| %s)", get_id(module
), t1
.first
, state_name
));
337 subexpr
.push_back(stringf("((_ extract %d %d) (|%s#%d| %s))",
338 t1
.second
+ j
- 1, t1
.second
, get_id(module
), t1
.first
, state_name
));
342 std::set
<RTLIL::SigBit
> seen_bits
= { sig
[i
] };
343 while (i
+j
< GetSize(sig
) && sig
[i
+j
].wire
&& !fcache
.count(sig
[i
+j
]) && !seen_bits
.count(sig
[i
+j
]))
344 seen_bits
.insert(sig
[i
+j
]), j
++;
346 if (verbose
) log("%*s-> external bv: %s\n", 2+2*GetSize(recursive_cells
), "",
347 log_signal(sig
.extract(i
, j
)));
348 for (auto bit
: sig
.extract(i
, j
))
349 log_assert(bit_driver
.count(bit
) == 0);
350 makebits(stringf("%s#%d", get_id(module
), idcounter
), j
, log_signal(sig
.extract(i
, j
)));
351 subexpr
.push_back(stringf("(|%s#%d| %s)", get_id(module
), idcounter
, state_name
));
352 register_bv(sig
.extract(i
, j
), idcounter
++);
355 if (GetSize(subexpr
) > 1) {
356 std::string expr
= "", end_str
= "";
357 for (int i
= GetSize(subexpr
)-1; i
>= 0; i
--) {
358 if (i
> 0) expr
+= " (concat", end_str
+= ")";
359 expr
+= " " + subexpr
[i
];
361 return expr
.substr(1) + end_str
;
363 log_assert(GetSize(subexpr
) == 1);
368 void export_gate(RTLIL::Cell
*cell
, std::string expr
)
370 RTLIL::SigBit bit
= sigmap(cell
->getPort("\\Y").as_bit());
371 std::string processed_expr
;
373 for (char ch
: expr
) {
374 if (ch
== 'A') processed_expr
+= get_bool(cell
->getPort("\\A"));
375 else if (ch
== 'B') processed_expr
+= get_bool(cell
->getPort("\\B"));
376 else if (ch
== 'C') processed_expr
+= get_bool(cell
->getPort("\\C"));
377 else if (ch
== 'D') processed_expr
+= get_bool(cell
->getPort("\\D"));
378 else if (ch
== 'S') processed_expr
+= get_bool(cell
->getPort("\\S"));
379 else processed_expr
+= ch
;
383 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
385 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
386 get_id(module
), idcounter
, get_id(module
), processed_expr
.c_str(), log_signal(bit
)));
387 register_bool(bit
, idcounter
++);
388 recursive_cells
.erase(cell
);
391 void export_bvop(RTLIL::Cell
*cell
, std::string expr
, char type
= 0)
393 RTLIL::SigSpec sig_a
, sig_b
;
394 RTLIL::SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
395 bool is_signed
= cell
->getParam("\\A_SIGNED").as_bool();
396 int width
= GetSize(sig_y
);
398 if (type
== 's' || type
== 'd' || type
== 'b') {
399 width
= max(width
, GetSize(cell
->getPort("\\A")));
400 if (cell
->hasPort("\\B"))
401 width
= max(width
, GetSize(cell
->getPort("\\B")));
404 if (cell
->hasPort("\\A")) {
405 sig_a
= cell
->getPort("\\A");
406 sig_a
.extend_u0(width
, is_signed
);
409 if (cell
->hasPort("\\B")) {
410 sig_b
= cell
->getPort("\\B");
411 sig_b
.extend_u0(width
, is_signed
&& !(type
== 's'));
414 std::string processed_expr
;
416 for (char ch
: expr
) {
417 if (ch
== 'A') processed_expr
+= get_bv(sig_a
);
418 else if (ch
== 'B') processed_expr
+= get_bv(sig_b
);
419 else if (ch
== 'L') processed_expr
+= is_signed
? "a" : "l";
420 else if (ch
== 'U') processed_expr
+= is_signed
? "s" : "u";
421 else processed_expr
+= ch
;
424 if (width
!= GetSize(sig_y
) && type
!= 'b')
425 processed_expr
= stringf("((_ extract %d 0) %s)", GetSize(sig_y
)-1, processed_expr
.c_str());
428 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
431 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
432 get_id(module
), idcounter
, get_id(module
), processed_expr
.c_str(), log_signal(sig_y
)));
433 register_boolvec(sig_y
, idcounter
++);
435 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
436 get_id(module
), idcounter
, get_id(module
), GetSize(sig_y
), processed_expr
.c_str(), log_signal(sig_y
)));
437 register_bv(sig_y
, idcounter
++);
440 recursive_cells
.erase(cell
);
443 void export_reduce(RTLIL::Cell
*cell
, std::string expr
, bool identity_val
)
445 RTLIL::SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
446 std::string processed_expr
;
449 if (ch
== 'A' || ch
== 'B') {
450 RTLIL::SigSpec sig
= sigmap(cell
->getPort(stringf("\\%c", ch
)));
452 processed_expr
+= " " + get_bool(bit
);
453 if (GetSize(sig
) == 1)
454 processed_expr
+= identity_val
? " true" : " false";
456 processed_expr
+= ch
;
459 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
461 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
462 get_id(module
), idcounter
, get_id(module
), processed_expr
.c_str(), log_signal(sig_y
)));
463 register_boolvec(sig_y
, idcounter
++);
464 recursive_cells
.erase(cell
);
467 void export_cell(RTLIL::Cell
*cell
)
470 log("%*s=> export_cell %s (%s) [%s]\n", 2+2*GetSize(recursive_cells
), "",
471 log_id(cell
), log_id(cell
->type
), exported_cells
.count(cell
) ? "old" : "new");
473 if (recursive_cells
.count(cell
))
474 log_error("Found logic loop in module %s! See cell %s.\n", get_id(module
), get_id(cell
));
476 if (exported_cells
.count(cell
))
479 exported_cells
.insert(cell
);
480 recursive_cells
.insert(cell
);
482 if (cell
->type
== "$initstate")
484 SigBit bit
= sigmap(cell
->getPort("\\Y").as_bit());
485 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
486 get_id(module
), idcounter
, get_id(module
), get_id(module
), log_signal(bit
)));
487 register_bool(bit
, idcounter
++);
488 recursive_cells
.erase(cell
);
492 if (cell
->type
.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
494 registers
.insert(cell
);
495 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(cell
->getPort("\\Q")));
496 register_bool(cell
->getPort("\\Q"), idcounter
++);
497 recursive_cells
.erase(cell
);
501 if (cell
->type
== "$_BUF_") return export_gate(cell
, "A");
502 if (cell
->type
== "$_NOT_") return export_gate(cell
, "(not A)");
503 if (cell
->type
== "$_AND_") return export_gate(cell
, "(and A B)");
504 if (cell
->type
== "$_NAND_") return export_gate(cell
, "(not (and A B))");
505 if (cell
->type
== "$_OR_") return export_gate(cell
, "(or A B)");
506 if (cell
->type
== "$_NOR_") return export_gate(cell
, "(not (or A B))");
507 if (cell
->type
== "$_XOR_") return export_gate(cell
, "(xor A B)");
508 if (cell
->type
== "$_XNOR_") return export_gate(cell
, "(not (xor A B))");
509 if (cell
->type
== "$_ANDNOT_") return export_gate(cell
, "(and A (not B))");
510 if (cell
->type
== "$_ORNOT_") return export_gate(cell
, "(or A (not B))");
511 if (cell
->type
== "$_MUX_") return export_gate(cell
, "(ite S B A)");
512 if (cell
->type
== "$_AOI3_") return export_gate(cell
, "(not (or (and A B) C))");
513 if (cell
->type
== "$_OAI3_") return export_gate(cell
, "(not (and (or A B) C))");
514 if (cell
->type
== "$_AOI4_") return export_gate(cell
, "(not (or (and A B) (and C D)))");
515 if (cell
->type
== "$_OAI4_") return export_gate(cell
, "(not (and (or A B) (or C D)))");
521 if (cell
->type
.in("$ff", "$dff"))
523 registers
.insert(cell
);
524 makebits(stringf("%s#%d", get_id(module
), idcounter
), GetSize(cell
->getPort("\\Q")), log_signal(cell
->getPort("\\Q")));
525 register_bv(cell
->getPort("\\Q"), idcounter
++);
526 recursive_cells
.erase(cell
);
530 if (cell
->type
.in("$anyconst", "$anyseq", "$allconst", "$allseq"))
532 registers
.insert(cell
);
533 string infostr
= cell
->attributes
.count("\\src") ? cell
->attributes
.at("\\src").decode_string().c_str() : get_id(cell
);
534 if (cell
->attributes
.count("\\reg"))
535 infostr
+= " " + cell
->attributes
.at("\\reg").decode_string();
536 decls
.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell
->type
.c_str() + 1, get_id(module
), idcounter
, GetSize(cell
->getPort("\\Y")), infostr
.c_str()));
537 makebits(stringf("%s#%d", get_id(module
), idcounter
), GetSize(cell
->getPort("\\Y")), log_signal(cell
->getPort("\\Y")));
538 if (cell
->type
== "$anyseq")
539 ex_input_eq
.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module
), idcounter
, get_id(module
), idcounter
));
540 register_bv(cell
->getPort("\\Y"), idcounter
++);
541 recursive_cells
.erase(cell
);
545 if (cell
->type
== "$and") return export_bvop(cell
, "(bvand A B)");
546 if (cell
->type
== "$or") return export_bvop(cell
, "(bvor A B)");
547 if (cell
->type
== "$xor") return export_bvop(cell
, "(bvxor A B)");
548 if (cell
->type
== "$xnor") return export_bvop(cell
, "(bvxnor A B)");
550 if (cell
->type
== "$shl") return export_bvop(cell
, "(bvshl A B)", 's');
551 if (cell
->type
== "$shr") return export_bvop(cell
, "(bvlshr A B)", 's');
552 if (cell
->type
== "$sshl") return export_bvop(cell
, "(bvshl A B)", 's');
553 if (cell
->type
== "$sshr") return export_bvop(cell
, "(bvLshr A B)", 's');
555 if (cell
->type
.in("$shift", "$shiftx")) {
556 if (cell
->getParam("\\B_SIGNED").as_bool()) {
559 return export_bvop(cell
, "(bvlshr A B)", 's');
563 if (cell
->type
== "$lt") return export_bvop(cell
, "(bvUlt A B)", 'b');
564 if (cell
->type
== "$le") return export_bvop(cell
, "(bvUle A B)", 'b');
565 if (cell
->type
== "$ge") return export_bvop(cell
, "(bvUge A B)", 'b');
566 if (cell
->type
== "$gt") return export_bvop(cell
, "(bvUgt A B)", 'b');
568 if (cell
->type
== "$ne") return export_bvop(cell
, "(distinct A B)", 'b');
569 if (cell
->type
== "$nex") return export_bvop(cell
, "(distinct A B)", 'b');
570 if (cell
->type
== "$eq") return export_bvop(cell
, "(= A B)", 'b');
571 if (cell
->type
== "$eqx") return export_bvop(cell
, "(= A B)", 'b');
573 if (cell
->type
== "$not") return export_bvop(cell
, "(bvnot A)");
574 if (cell
->type
== "$pos") return export_bvop(cell
, "A");
575 if (cell
->type
== "$neg") return export_bvop(cell
, "(bvneg A)");
577 if (cell
->type
== "$add") return export_bvop(cell
, "(bvadd A B)");
578 if (cell
->type
== "$sub") return export_bvop(cell
, "(bvsub A B)");
579 if (cell
->type
== "$mul") return export_bvop(cell
, "(bvmul A B)");
580 if (cell
->type
== "$div") return export_bvop(cell
, "(bvUdiv A B)", 'd');
581 if (cell
->type
== "$mod") return export_bvop(cell
, "(bvUrem A B)", 'd');
583 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_bool") &&
584 2*GetSize(cell
->getPort("\\A").chunks()) < GetSize(cell
->getPort("\\A"))) {
585 bool is_and
= cell
->type
== "$reduce_and";
586 string
bits(GetSize(cell
->getPort("\\A")), is_and
? '1' : '0');
587 return export_bvop(cell
, stringf("(%s A #b%s)", is_and
? "=" : "distinct", bits
.c_str()), 'b');
590 if (cell
->type
== "$reduce_and") return export_reduce(cell
, "(and A)", true);
591 if (cell
->type
== "$reduce_or") return export_reduce(cell
, "(or A)", false);
592 if (cell
->type
== "$reduce_xor") return export_reduce(cell
, "(xor A)", false);
593 if (cell
->type
== "$reduce_xnor") return export_reduce(cell
, "(not (xor A))", false);
594 if (cell
->type
== "$reduce_bool") return export_reduce(cell
, "(or A)", false);
596 if (cell
->type
== "$logic_not") return export_reduce(cell
, "(not (or A))", false);
597 if (cell
->type
== "$logic_and") return export_reduce(cell
, "(and (or A) (or B))", false);
598 if (cell
->type
== "$logic_or") return export_reduce(cell
, "(or A B)", false);
600 if (cell
->type
== "$mux" || cell
->type
== "$pmux")
602 int width
= GetSize(cell
->getPort("\\Y"));
603 std::string processed_expr
= get_bv(cell
->getPort("\\A"));
605 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
606 RTLIL::SigSpec sig_s
= cell
->getPort("\\S");
610 for (int i
= 0; i
< GetSize(sig_s
); i
++)
611 processed_expr
= stringf("(ite %s %s %s)", get_bool(sig_s
[i
]).c_str(),
612 get_bv(sig_b
.extract(i
*width
, width
)).c_str(), processed_expr
.c_str());
615 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
617 RTLIL::SigSpec sig
= sigmap(cell
->getPort("\\Y"));
618 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
619 get_id(module
), idcounter
, get_id(module
), width
, processed_expr
.c_str(), log_signal(sig
)));
620 register_bv(sig
, idcounter
++);
621 recursive_cells
.erase(cell
);
625 // FIXME: $slice $concat
628 if (memmode
&& cell
->type
== "$mem")
630 int arrayid
= idcounter
++;
631 memarrays
[cell
] = arrayid
;
633 int abits
= cell
->getParam("\\ABITS").as_int();
634 int width
= cell
->getParam("\\WIDTH").as_int();
635 int rd_ports
= cell
->getParam("\\RD_PORTS").as_int();
636 int wr_ports
= cell
->getParam("\\WR_PORTS").as_int();
638 bool async_read
= false;
639 if (!cell
->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
640 if (!cell
->getParam("\\WR_CLK_ENABLE").is_fully_zero())
641 log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell
), log_id(module
));
645 decls
.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", get_id(cell
), abits
, width
, rd_ports
, wr_ports
, async_read
? "async" : "sync"));
649 memstate
= stringf("%s#%d#final", get_id(module
), arrayid
);
651 memstate
= stringf("%s#%d#0", get_id(module
), arrayid
);
656 int mem_size
= cell
->getParam("\\SIZE").as_int();
657 int mem_offset
= cell
->getParam("\\OFFSET").as_int();
659 makebits(memstate
, width
*mem_size
, get_id(cell
));
660 decls
.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n",
661 get_id(module
), get_id(cell
), get_id(module
), width
*mem_size
, memstate
.c_str()));
663 for (int i
= 0; i
< rd_ports
; i
++)
665 SigSpec addr_sig
= cell
->getPort("\\RD_ADDR").extract(abits
*i
, abits
);
666 SigSpec data_sig
= cell
->getPort("\\RD_DATA").extract(width
*i
, width
);
667 std::string addr
= get_bv(addr_sig
);
669 if (cell
->getParam("\\RD_CLK_ENABLE").extract(i
).as_bool())
670 log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
671 "Call \"memory\" with -nordff to avoid this error.\n", i
, log_signal(data_sig
), log_id(cell
), log_id(module
));
673 decls
.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
674 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
676 std::string read_expr
= "#b";
677 for (int k
= 0; k
< width
; k
++)
680 for (int k
= 0; k
< mem_size
; k
++)
681 read_expr
= stringf("(ite (= (|%s_m:R%dA %s| state) #b%s) ((_ extract %d %d) (|%s| state))\n %s)",
682 get_id(module
), i
, get_id(cell
), Const(k
+mem_offset
, abits
).as_string().c_str(),
683 width
*(k
+1)-1, width
*k
, memstate
.c_str(), read_expr
.c_str());
685 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d)\n %s) ; %s\n",
686 get_id(module
), idcounter
, get_id(module
), width
, read_expr
.c_str(), log_signal(data_sig
)));
688 decls
.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
689 get_id(module
), i
, get_id(cell
), get_id(module
), width
, get_id(module
), idcounter
));
691 register_bv(data_sig
, idcounter
++);
697 dtmembers
.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
698 memstate
.c_str(), abits
, width
, get_id(cell
)));
700 decls
.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
701 memstate
.c_str(), get_id(module
), abits
, width
, get_id(cell
)));
703 decls
.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s| state))\n",
704 get_id(module
), get_id(cell
), get_id(module
), abits
, width
, memstate
.c_str()));
706 for (int i
= 0; i
< rd_ports
; i
++)
708 SigSpec addr_sig
= cell
->getPort("\\RD_ADDR").extract(abits
*i
, abits
);
709 SigSpec data_sig
= cell
->getPort("\\RD_DATA").extract(width
*i
, width
);
710 std::string addr
= get_bv(addr_sig
);
712 if (cell
->getParam("\\RD_CLK_ENABLE").extract(i
).as_bool())
713 log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
714 "Call \"memory\" with -nordff to avoid this error.\n", i
, log_signal(data_sig
), log_id(cell
), log_id(module
));
716 decls
.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
717 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
719 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s| state) (|%s_m:R%dA %s| state))) ; %s\n",
720 get_id(module
), idcounter
, get_id(module
), width
, memstate
.c_str(), get_id(module
), i
, get_id(cell
), log_signal(data_sig
)));
722 decls
.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
723 get_id(module
), i
, get_id(cell
), get_id(module
), width
, get_id(module
), idcounter
));
725 register_bv(data_sig
, idcounter
++);
729 registers
.insert(cell
);
730 recursive_cells
.erase(cell
);
734 Module
*m
= module
->design
->module(cell
->type
);
738 decls
.push_back(stringf("; yosys-smt2-cell %s %s\n", get_id(cell
->type
), get_id(cell
->name
)));
739 string cell_state
= stringf("(|%s_h %s| state)", get_id(module
), get_id(cell
->name
));
741 for (auto &conn
: cell
->connections())
743 if (GetSize(conn
.second
) == 0)
746 Wire
*w
= m
->wire(conn
.first
);
747 SigSpec sig
= sigmap(conn
.second
);
749 if (w
->port_output
&& !w
->port_input
) {
750 if (GetSize(w
) > 1) {
752 makebits(stringf("%s#%d", get_id(module
), idcounter
), GetSize(w
), log_signal(sig
));
753 register_bv(sig
, idcounter
++);
755 for (int i
= 0; i
< GetSize(w
); i
++) {
756 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(sig
[i
]));
757 register_bool(sig
[i
], idcounter
++);
761 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(sig
));
762 register_bool(sig
, idcounter
++);
768 makebits(stringf("%s_h %s", get_id(module
), get_id(cell
->name
)), mod_stbv_width
.at(cell
->type
));
770 dtmembers
.push_back(stringf(" (|%s_h %s| |%s_s|)\n",
771 get_id(module
), get_id(cell
->name
), get_id(cell
->type
)));
773 decls
.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
774 get_id(module
), get_id(cell
->name
), get_id(module
), get_id(cell
->type
)));
776 hiercells
.insert(cell
);
777 hiercells_queue
.insert(cell
);
778 recursive_cells
.erase(cell
);
782 log_error("Unsupported cell type %s for cell %s.%s.\n",
783 log_id(cell
->type
), log_id(module
), log_id(cell
));
788 if (verbose
) log("=> export logic driving outputs\n");
790 pool
<SigBit
> reg_bits
;
791 for (auto cell
: module
->cells())
792 if (cell
->type
.in("$ff", "$dff", "$_FF_", "$_DFF_P_", "$_DFF_N_")) {
793 // not using sigmap -- we want the net directly at the dff output
794 for (auto bit
: cell
->getPort("\\Q"))
795 reg_bits
.insert(bit
);
798 for (auto wire
: module
->wires()) {
799 bool is_register
= false;
800 for (auto bit
: SigSpec(wire
))
801 if (reg_bits
.count(bit
))
803 if (wire
->port_id
|| is_register
|| wire
->get_bool_attribute("\\keep") || (wiresmode
&& wire
->name
[0] == '\\')) {
804 RTLIL::SigSpec sig
= sigmap(wire
);
805 if (wire
->port_input
)
806 decls
.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire
), wire
->width
));
807 if (wire
->port_output
)
808 decls
.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire
), wire
->width
));
810 decls
.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire
), wire
->width
));
811 if (wire
->get_bool_attribute("\\keep") || (wiresmode
&& wire
->name
[0] == '\\'))
812 decls
.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire
), wire
->width
));
813 if (GetSize(wire
) == 1 && (clock_posedge
.count(sig
) || clock_negedge
.count(sig
)))
814 decls
.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire
),
815 clock_posedge
.count(sig
) ? " posedge" : "", clock_negedge
.count(sig
) ? " negedge" : ""));
816 if (bvmode
&& GetSize(sig
) > 1) {
817 decls
.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
818 get_id(module
), get_id(wire
), get_id(module
), GetSize(sig
), get_bv(sig
).c_str()));
819 if (wire
->port_input
)
820 ex_input_eq
.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
821 get_id(module
), get_id(wire
), get_id(module
), get_id(wire
)));
823 for (int i
= 0; i
< GetSize(sig
); i
++)
824 if (GetSize(sig
) > 1) {
825 decls
.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
826 get_id(module
), get_id(wire
), i
, get_id(module
), get_bool(sig
[i
]).c_str()));
827 if (wire
->port_input
)
828 ex_input_eq
.push_back(stringf(" (= (|%s_n %s %d| state) (|%s_n %s %d| other_state))",
829 get_id(module
), get_id(wire
), i
, get_id(module
), get_id(wire
), i
));
831 decls
.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
832 get_id(module
), get_id(wire
), get_id(module
), get_bool(sig
[i
]).c_str()));
833 if (wire
->port_input
)
834 ex_input_eq
.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
835 get_id(module
), get_id(wire
), get_id(module
), get_id(wire
)));
841 if (verbose
) log("=> export logic associated with the initial state\n");
843 vector
<string
> init_list
;
844 for (auto wire
: module
->wires())
845 if (wire
->attributes
.count("\\init")) {
846 RTLIL::SigSpec sig
= sigmap(wire
);
847 Const val
= wire
->attributes
.at("\\init");
848 val
.bits
.resize(GetSize(sig
), State::Sx
);
849 if (bvmode
&& GetSize(sig
) > 1) {
850 Const
mask(State::S1
, GetSize(sig
));
851 bool use_mask
= false;
852 for (int i
= 0; i
< GetSize(sig
); i
++)
853 if (val
[i
] != State::S0
&& val
[i
] != State::S1
) {
859 init_list
.push_back(stringf("(= (bvand %s #b%s) #b%s) ; %s", get_bv(sig
).c_str(), mask
.as_string().c_str(), val
.as_string().c_str(), get_id(wire
)));
861 init_list
.push_back(stringf("(= %s #b%s) ; %s", get_bv(sig
).c_str(), val
.as_string().c_str(), get_id(wire
)));
863 for (int i
= 0; i
< GetSize(sig
); i
++)
864 if (val
[i
] == State::S0
|| val
[i
] == State::S1
)
865 init_list
.push_back(stringf("(= %s %s) ; %s", get_bool(sig
[i
]).c_str(), val
[i
] == State::S1
? "true" : "false", get_id(wire
)));
869 if (verbose
) log("=> export logic driving asserts\n");
871 int assert_id
= 0, assume_id
= 0, cover_id
= 0;
872 vector
<string
> assert_list
, assume_list
, cover_list
;
874 for (auto cell
: module
->cells())
876 if (cell
->type
.in("$assert", "$assume", "$cover"))
878 int &id
= cell
->type
== "$assert" ? assert_id
:
879 cell
->type
== "$assume" ? assume_id
:
880 cell
->type
== "$cover" ? cover_id
: *(int*)nullptr;
882 char postfix
= cell
->type
== "$assert" ? 'a' :
883 cell
->type
== "$assume" ? 'u' :
884 cell
->type
== "$cover" ? 'c' : 0;
886 string name_a
= get_bool(cell
->getPort("\\A"));
887 string name_en
= get_bool(cell
->getPort("\\EN"));
888 decls
.push_back(stringf("; yosys-smt2-%s %d %s\n", cell
->type
.c_str() + 1, id
,
889 cell
->attributes
.count("\\src") ? cell
->attributes
.at("\\src").decode_string().c_str() : get_id(cell
)));
891 if (cell
->type
== "$cover")
892 decls
.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
893 get_id(module
), postfix
, id
, get_id(module
), name_a
.c_str(), name_en
.c_str(), get_id(cell
)));
895 decls
.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n",
896 get_id(module
), postfix
, id
, get_id(module
), name_a
.c_str(), name_en
.c_str(), get_id(cell
)));
898 if (cell
->type
== "$assert")
899 assert_list
.push_back(stringf("(|%s_a %d| state)", get_id(module
), id
));
900 else if (cell
->type
== "$assume")
901 assume_list
.push_back(stringf("(|%s_u %d| state)", get_id(module
), id
));
907 if (verbose
) log("=> export logic driving hierarchical cells\n");
909 for (auto cell
: module
->cells())
910 if (module
->design
->module(cell
->type
) != nullptr)
913 while (!hiercells_queue
.empty())
915 std::set
<RTLIL::Cell
*> queue
;
916 queue
.swap(hiercells_queue
);
918 for (auto cell
: queue
)
920 string cell_state
= stringf("(|%s_h %s| state)", get_id(module
), get_id(cell
->name
));
921 Module
*m
= module
->design
->module(cell
->type
);
922 log_assert(m
!= nullptr);
924 hier
.push_back(stringf(" (= (|%s_is| state) (|%s_is| %s))\n",
925 get_id(module
), get_id(cell
->type
), cell_state
.c_str()));
927 for (auto &conn
: cell
->connections())
929 if (GetSize(conn
.second
) == 0)
932 Wire
*w
= m
->wire(conn
.first
);
933 SigSpec sig
= sigmap(conn
.second
);
935 if (bvmode
|| GetSize(w
) == 1) {
936 hier
.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w
) > 1 ? get_bv(sig
) : get_bool(sig
)).c_str(),
937 get_id(cell
->type
), get_id(w
), cell_state
.c_str(), get_id(cell
->type
), get_id(w
)));
939 for (int i
= 0; i
< GetSize(w
); i
++)
940 hier
.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig
[i
]).c_str(),
941 get_id(cell
->type
), get_id(w
), i
, cell_state
.c_str(), get_id(cell
->type
), get_id(w
), i
));
947 for (int iter
= 1; !registers
.empty(); iter
++)
949 pool
<Cell
*> this_regs
;
950 this_regs
.swap(registers
);
952 if (verbose
) log("=> export logic driving registers [iteration %d]\n", iter
);
954 for (auto cell
: this_regs
)
956 if (cell
->type
.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
958 std::string expr_d
= get_bool(cell
->getPort("\\D"));
959 std::string expr_q
= get_bool(cell
->getPort("\\Q"), "next_state");
960 trans
.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
), log_signal(cell
->getPort("\\Q"))));
961 ex_state_eq
.push_back(stringf("(= %s %s)", get_bool(cell
->getPort("\\Q")).c_str(), get_bool(cell
->getPort("\\Q"), "other_state").c_str()));
964 if (cell
->type
.in("$ff", "$dff"))
966 std::string expr_d
= get_bv(cell
->getPort("\\D"));
967 std::string expr_q
= get_bv(cell
->getPort("\\Q"), "next_state");
968 trans
.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
), log_signal(cell
->getPort("\\Q"))));
969 ex_state_eq
.push_back(stringf("(= %s %s)", get_bv(cell
->getPort("\\Q")).c_str(), get_bv(cell
->getPort("\\Q"), "other_state").c_str()));
972 if (cell
->type
.in("$anyconst", "$allconst"))
974 std::string expr_d
= get_bv(cell
->getPort("\\Y"));
975 std::string expr_q
= get_bv(cell
->getPort("\\Y"), "next_state");
976 trans
.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
), log_signal(cell
->getPort("\\Y"))));
977 if (cell
->type
== "$anyconst")
978 ex_state_eq
.push_back(stringf("(= %s %s)", get_bv(cell
->getPort("\\Y")).c_str(), get_bv(cell
->getPort("\\Y"), "other_state").c_str()));
981 if (cell
->type
== "$mem")
983 int arrayid
= memarrays
.at(cell
);
985 int abits
= cell
->getParam("\\ABITS").as_int();
986 int width
= cell
->getParam("\\WIDTH").as_int();
987 int wr_ports
= cell
->getParam("\\WR_PORTS").as_int();
989 bool async_read
= false;
990 string initial_memstate
, final_memstate
;
992 if (!cell
->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
993 log_assert(cell
->getParam("\\WR_CLK_ENABLE").is_fully_zero());
995 initial_memstate
= stringf("%s#%d#0", get_id(module
), arrayid
);
996 final_memstate
= stringf("%s#%d#final", get_id(module
), arrayid
);
1001 int mem_size
= cell
->getParam("\\SIZE").as_int();
1002 int mem_offset
= cell
->getParam("\\OFFSET").as_int();
1005 makebits(final_memstate
, width
*mem_size
, get_id(cell
));
1008 for (int i
= 0; i
< wr_ports
; i
++)
1010 SigSpec addr_sig
= cell
->getPort("\\WR_ADDR").extract(abits
*i
, abits
);
1011 SigSpec data_sig
= cell
->getPort("\\WR_DATA").extract(width
*i
, width
);
1012 SigSpec mask_sig
= cell
->getPort("\\WR_EN").extract(width
*i
, width
);
1014 std::string addr
= get_bv(addr_sig
);
1015 std::string data
= get_bv(data_sig
);
1016 std::string mask
= get_bv(mask_sig
);
1018 decls
.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1019 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
1020 addr
= stringf("(|%s_m:W%dA %s| state)", get_id(module
), i
, get_id(cell
));
1022 decls
.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1023 get_id(module
), i
, get_id(cell
), get_id(module
), width
, data
.c_str(), log_signal(data_sig
)));
1024 data
= stringf("(|%s_m:W%dD %s| state)", get_id(module
), i
, get_id(cell
));
1026 decls
.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1027 get_id(module
), i
, get_id(cell
), get_id(module
), width
, mask
.c_str(), log_signal(mask_sig
)));
1028 mask
= stringf("(|%s_m:W%dM %s| state)", get_id(module
), i
, get_id(cell
));
1030 std::string data_expr
;
1032 for (int k
= mem_size
-1; k
>= 0; k
--) {
1033 std::string new_data
= stringf("(bvor (bvand %s %s) (bvand ((_ extract %d %d) (|%s#%d#%d| state)) (bvnot %s)))",
1034 data
.c_str(), mask
.c_str(), width
*(k
+1)-1, width
*k
, get_id(module
), arrayid
, i
, mask
.c_str());
1035 data_expr
+= stringf("\n (ite (= %s #b%s) %s ((_ extract %d %d) (|%s#%d#%d| state)))",
1036 addr
.c_str(), Const(k
+mem_offset
, abits
).as_string().c_str(), new_data
.c_str(),
1037 width
*(k
+1)-1, width
*k
, get_id(module
), arrayid
, i
);
1040 decls
.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (_ BitVec %d) (concat%s)) ; %s\n",
1041 get_id(module
), arrayid
, i
+1, get_id(module
), width
*mem_size
, data_expr
.c_str(), get_id(cell
)));
1048 dtmembers
.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
1049 initial_memstate
.c_str(), abits
, width
, get_id(cell
)));
1051 decls
.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
1052 initial_memstate
.c_str(), get_id(module
), abits
, width
, get_id(cell
)));
1055 for (int i
= 0; i
< wr_ports
; i
++)
1057 SigSpec addr_sig
= cell
->getPort("\\WR_ADDR").extract(abits
*i
, abits
);
1058 SigSpec data_sig
= cell
->getPort("\\WR_DATA").extract(width
*i
, width
);
1059 SigSpec mask_sig
= cell
->getPort("\\WR_EN").extract(width
*i
, width
);
1061 std::string addr
= get_bv(addr_sig
);
1062 std::string data
= get_bv(data_sig
);
1063 std::string mask
= get_bv(mask_sig
);
1065 decls
.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1066 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
1067 addr
= stringf("(|%s_m:W%dA %s| state)", get_id(module
), i
, get_id(cell
));
1069 decls
.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1070 get_id(module
), i
, get_id(cell
), get_id(module
), width
, data
.c_str(), log_signal(data_sig
)));
1071 data
= stringf("(|%s_m:W%dD %s| state)", get_id(module
), i
, get_id(cell
));
1073 decls
.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1074 get_id(module
), i
, get_id(cell
), get_id(module
), width
, mask
.c_str(), log_signal(mask_sig
)));
1075 mask
= stringf("(|%s_m:W%dM %s| state)", get_id(module
), i
, get_id(cell
));
1077 data
= stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
1078 data
.c_str(), mask
.c_str(), get_id(module
), arrayid
, i
, addr
.c_str(), mask
.c_str());
1080 decls
.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
1081 "(store (|%s#%d#%d| state) %s %s)) ; %s\n",
1082 get_id(module
), arrayid
, i
+1, get_id(module
), abits
, width
,
1083 get_id(module
), arrayid
, i
, addr
.c_str(), data
.c_str(), get_id(cell
)));
1087 std::string expr_d
= stringf("(|%s#%d#%d| state)", get_id(module
), arrayid
, wr_ports
);
1088 std::string expr_q
= stringf("(|%s#%d#0| next_state)", get_id(module
), arrayid
);
1089 trans
.push_back(stringf(" (= %s %s) ; %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
)));
1090 ex_state_eq
.push_back(stringf("(= (|%s#%d#0| state) (|%s#%d#0| other_state))", get_id(module
), arrayid
, get_id(module
), arrayid
));
1093 hier
.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d
.c_str(), final_memstate
.c_str(), get_id(cell
)));
1095 Const init_data
= cell
->getParam("\\INIT");
1096 int memsize
= cell
->getParam("\\SIZE").as_int();
1098 for (int i
= 0; i
< memsize
; i
++)
1100 if (i
*width
>= GetSize(init_data
))
1103 Const initword
= init_data
.extract(i
*width
, width
, State::Sx
);
1104 bool gen_init_constr
= false;
1106 for (auto bit
: initword
.bits
)
1107 if (bit
== State::S0
|| bit
== State::S1
)
1108 gen_init_constr
= true;
1110 if (gen_init_constr
)
1115 init_list
.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
1116 get_id(module
), arrayid
, Const(i
, abits
).as_string().c_str(),
1117 initword
.as_string().c_str(), get_id(cell
), i
));
1124 if (verbose
) log("=> finalizing SMT2 representation of %s.\n", log_id(module
));
1126 for (auto c
: hiercells
) {
1127 assert_list
.push_back(stringf("(|%s_a| (|%s_h %s| state))", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1128 assume_list
.push_back(stringf("(|%s_u| (|%s_h %s| state))", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1129 init_list
.push_back(stringf("(|%s_i| (|%s_h %s| state))", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1130 hier
.push_back(stringf(" (|%s_h| (|%s_h %s| state))\n", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1131 trans
.push_back(stringf(" (|%s_t| (|%s_h %s| state) (|%s_h %s| next_state))\n",
1132 get_id(c
->type
), get_id(module
), get_id(c
->name
), get_id(module
), get_id(c
->name
)));
1133 ex_state_eq
.push_back(stringf("(|%s_ex_state_eq| (|%s_h %s| state) (|%s_h %s| other_state))\n",
1134 get_id(c
->type
), get_id(module
), get_id(c
->name
), get_id(module
), get_id(c
->name
)));
1139 string expr
= ex_state_eq
.empty() ? "true" : "(and";
1140 if (!ex_state_eq
.empty()) {
1141 if (GetSize(ex_state_eq
) == 1) {
1142 expr
= "\n " + ex_state_eq
.front() + "\n";
1144 for (auto &str
: ex_state_eq
)
1145 expr
+= stringf("\n %s", str
.c_str());
1149 decls
.push_back(stringf("(define-fun |%s_ex_state_eq| ((state |%s_s|) (other_state |%s_s|)) Bool %s)\n",
1150 get_id(module
), get_id(module
), get_id(module
), expr
.c_str()));
1152 expr
= ex_input_eq
.empty() ? "true" : "(and";
1153 if (!ex_input_eq
.empty()) {
1154 if (GetSize(ex_input_eq
) == 1) {
1155 expr
= "\n " + ex_input_eq
.front() + "\n";
1157 for (auto &str
: ex_input_eq
)
1158 expr
+= stringf("\n %s", str
.c_str());
1162 decls
.push_back(stringf("(define-fun |%s_ex_input_eq| ((state |%s_s|) (other_state |%s_s|)) Bool %s)\n",
1163 get_id(module
), get_id(module
), get_id(module
), expr
.c_str()));
1166 string assert_expr
= assert_list
.empty() ? "true" : "(and";
1167 if (!assert_list
.empty()) {
1168 if (GetSize(assert_list
) == 1) {
1169 assert_expr
= "\n " + assert_list
.front() + "\n";
1171 for (auto &str
: assert_list
)
1172 assert_expr
+= stringf("\n %s", str
.c_str());
1173 assert_expr
+= "\n)";
1176 decls
.push_back(stringf("(define-fun |%s_a| ((state |%s_s|)) Bool %s)\n",
1177 get_id(module
), get_id(module
), assert_expr
.c_str()));
1179 string assume_expr
= assume_list
.empty() ? "true" : "(and";
1180 if (!assume_list
.empty()) {
1181 if (GetSize(assume_list
) == 1) {
1182 assume_expr
= "\n " + assume_list
.front() + "\n";
1184 for (auto &str
: assume_list
)
1185 assume_expr
+= stringf("\n %s", str
.c_str());
1186 assume_expr
+= "\n)";
1189 decls
.push_back(stringf("(define-fun |%s_u| ((state |%s_s|)) Bool %s)\n",
1190 get_id(module
), get_id(module
), assume_expr
.c_str()));
1192 string init_expr
= init_list
.empty() ? "true" : "(and";
1193 if (!init_list
.empty()) {
1194 if (GetSize(init_list
) == 1) {
1195 init_expr
= "\n " + init_list
.front() + "\n";
1197 for (auto &str
: init_list
)
1198 init_expr
+= stringf("\n %s", str
.c_str());
1202 decls
.push_back(stringf("(define-fun |%s_i| ((state |%s_s|)) Bool %s)\n",
1203 get_id(module
), get_id(module
), init_expr
.c_str()));
1206 void write(std::ostream
&f
)
1208 f
<< stringf("; yosys-smt2-module %s\n", get_id(module
));
1211 f
<< stringf("(define-sort |%s_s| () (_ BitVec %d))\n", get_id(module
), statebv_width
);
1212 mod_stbv_width
[module
->name
] = statebv_width
;
1215 f
<< stringf("(declare-datatype |%s_s| ((|%s_mk|\n", get_id(module
), get_id(module
));
1216 for (auto it
: dtmembers
)
1218 f
<< stringf(")))\n");
1220 f
<< stringf("(declare-sort |%s_s| 0)\n", get_id(module
));
1222 for (auto it
: decls
)
1225 f
<< stringf("(define-fun |%s_h| ((state |%s_s|)) Bool ", get_id(module
), get_id(module
));
1226 if (GetSize(hier
) > 1) {
1228 for (auto it
: hier
)
1232 if (GetSize(hier
) == 1)
1233 f
<< "\n" + hier
.front() + ")\n";
1237 f
<< stringf("(define-fun |%s_t| ((state |%s_s|) (next_state |%s_s|)) Bool ", get_id(module
), get_id(module
), get_id(module
));
1238 if (GetSize(trans
) > 1) {
1240 for (auto it
: trans
)
1244 if (GetSize(trans
) == 1)
1245 f
<< "\n" + trans
.front() + ")";
1248 f
<< stringf(" ; end of module %s\n", get_id(module
));
1252 struct Smt2Backend
: public Backend
{
1253 Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
1256 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1258 log(" write_smt2 [options] [filename]\n");
1260 log("Write a SMT-LIBv2 [1] description of the current design. For a module with name\n");
1261 log("'<mod>' this will declare the sort '<mod>_s' (state of the module) and will\n");
1262 log("define and declare functions operating on that state.\n");
1264 log("The following SMT2 functions are generated for a module with name '<mod>'.\n");
1265 log("Some declarations/definitions are printed with a special comment. A prover\n");
1266 log("using the SMT2 files can use those comments to collect all relevant metadata\n");
1267 log("about the design.\n");
1269 log(" ; yosys-smt2-module <mod>\n");
1270 log(" (declare-sort |<mod>_s| 0)\n");
1271 log(" The sort representing a state of module <mod>.\n");
1273 log(" (define-fun |<mod>_h| ((state |<mod>_s|)) Bool (...))\n");
1274 log(" This function must be asserted for each state to establish the\n");
1275 log(" design hierarchy.\n");
1277 log(" ; yosys-smt2-input <wirename> <width>\n");
1278 log(" ; yosys-smt2-output <wirename> <width>\n");
1279 log(" ; yosys-smt2-register <wirename> <width>\n");
1280 log(" ; yosys-smt2-wire <wirename> <width>\n");
1281 log(" (define-fun |<mod>_n <wirename>| (|<mod>_s|) (_ BitVec <width>))\n");
1282 log(" (define-fun |<mod>_n <wirename>| (|<mod>_s|) Bool)\n");
1283 log(" For each port, register, and wire with the 'keep' attribute set an\n");
1284 log(" accessor function is generated. Single-bit wires are returned as Bool,\n");
1285 log(" multi-bit wires as BitVec.\n");
1287 log(" ; yosys-smt2-cell <submod> <instancename>\n");
1288 log(" (declare-fun |<mod>_h <instancename>| (|<mod>_s|) |<submod>_s|)\n");
1289 log(" There is a function like that for each hierarchical instance. It\n");
1290 log(" returns the sort that represents the state of the sub-module that\n");
1291 log(" implements the instance.\n");
1293 log(" (declare-fun |<mod>_is| (|<mod>_s|) Bool)\n");
1294 log(" This function must be asserted 'true' for initial states, and 'false'\n");
1295 log(" otherwise.\n");
1297 log(" (define-fun |<mod>_i| ((state |<mod>_s|)) Bool (...))\n");
1298 log(" This function must be asserted 'true' for initial states. For\n");
1299 log(" non-initial states it must be left unconstrained.\n");
1301 log(" (define-fun |<mod>_t| ((state |<mod>_s|) (next_state |<mod>_s|)) Bool (...))\n");
1302 log(" This function evaluates to 'true' if the states 'state' and\n");
1303 log(" 'next_state' form a valid state transition.\n");
1305 log(" (define-fun |<mod>_a| ((state |<mod>_s|)) Bool (...))\n");
1306 log(" This function evaluates to 'true' if all assertions hold in the state.\n");
1308 log(" (define-fun |<mod>_u| ((state |<mod>_s|)) Bool (...))\n");
1309 log(" This function evaluates to 'true' if all assumptions hold in the state.\n");
1311 log(" ; yosys-smt2-assert <id> <filename:linenum>\n");
1312 log(" (define-fun |<mod>_a <id>| ((state |<mod>_s|)) Bool (...))\n");
1313 log(" Each $assert cell is converted into one of this functions. The function\n");
1314 log(" evaluates to 'true' if the assert statement holds in the state.\n");
1316 log(" ; yosys-smt2-assume <id> <filename:linenum>\n");
1317 log(" (define-fun |<mod>_u <id>| ((state |<mod>_s|)) Bool (...))\n");
1318 log(" Each $assume cell is converted into one of this functions. The function\n");
1319 log(" evaluates to 'true' if the assume statement holds in the state.\n");
1321 log(" ; yosys-smt2-cover <id> <filename:linenum>\n");
1322 log(" (define-fun |<mod>_c <id>| ((state |<mod>_s|)) Bool (...))\n");
1323 log(" Each $cover cell is converted into one of this functions. The function\n");
1324 log(" evaluates to 'true' if the cover statement is activated in the state.\n");
1329 log(" this will print the recursive walk used to export the modules.\n");
1332 log(" Use a BitVec sort to represent a state instead of an uninterpreted\n");
1333 log(" sort. As a side-effect this will prevent use of arrays to model\n");
1334 log(" memories.\n");
1337 log(" Use SMT-LIB 2.6 style datatypes to represent a state instead of an\n");
1338 log(" uninterpreted sort.\n");
1341 log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
1342 log(" option multi-bit wires are represented using the BitVec sort and\n");
1343 log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
1346 log(" disable support for memories (via ArraysEx theory). this option is\n");
1347 log(" implied by -nobv. only $mem cells without merged registers in\n");
1348 log(" read ports are supported. call \"memory\" with -nordff to make sure\n");
1349 log(" that no registers are merged into $mem read ports. '<mod>_m' functions\n");
1350 log(" will be generated for accessing the arrays that are used to represent\n");
1351 log(" memories.\n");
1354 log(" create '<mod>_n' functions for all public wires. by default only ports,\n");
1355 log(" registers, and wires with the 'keep' attribute are exported.\n");
1357 log(" -tpl <template_file>\n");
1358 log(" use the given template file. the line containing only the token '%%%%'\n");
1359 log(" is replaced with the regular output of this command.\n");
1361 log("[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David\n");
1362 log("R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf\n");
1364 log("---------------------------------------------------------------------------\n");
1368 log("Consider the following module (test.v). We want to prove that the output can\n");
1369 log("never transition from a non-zero value to a zero value.\n");
1371 log(" module test(input clk, output reg [3:0] y);\n");
1372 log(" always @(posedge clk)\n");
1373 log(" y <= (y << 1) | ^y;\n");
1374 log(" endmodule\n");
1376 log("For this proof we create the following template (test.tpl).\n");
1378 log(" ; we need QF_UFBV for this poof\n");
1379 log(" (set-logic QF_UFBV)\n");
1381 log(" ; insert the auto-generated code here\n");
1384 log(" ; declare two state variables s1 and s2\n");
1385 log(" (declare-fun s1 () test_s)\n");
1386 log(" (declare-fun s2 () test_s)\n");
1388 log(" ; state s2 is the successor of state s1\n");
1389 log(" (assert (test_t s1 s2))\n");
1391 log(" ; we are looking for a model with y non-zero in s1\n");
1392 log(" (assert (distinct (|test_n y| s1) #b0000))\n");
1394 log(" ; we are looking for a model with y zero in s2\n");
1395 log(" (assert (= (|test_n y| s2) #b0000))\n");
1397 log(" ; is there such a model?\n");
1398 log(" (check-sat)\n");
1400 log("The following yosys script will create a 'test.smt2' file for our proof:\n");
1402 log(" read_verilog test.v\n");
1403 log(" hierarchy -check; proc; opt; check -assert\n");
1404 log(" write_smt2 -bv -tpl test.tpl test.smt2\n");
1406 log("Running 'cvc4 test.smt2' will print 'unsat' because y can never transition\n");
1407 log("from non-zero to zero in the test design.\n");
1410 virtual void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
)
1412 std::ifstream template_f
;
1413 bool bvmode
= true, memmode
= true, wiresmode
= false, verbose
= false, statebv
= false, statedt
= false;
1414 bool forallmode
= false;
1416 log_header(design
, "Executing SMT2 backend.\n");
1419 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1421 if (args
[argidx
] == "-tpl" && argidx
+1 < args
.size()) {
1422 template_f
.open(args
[++argidx
]);
1423 if (template_f
.fail())
1424 log_error("Can't open template file `%s'.\n", args
[argidx
].c_str());
1427 if (args
[argidx
] == "-bv" || args
[argidx
] == "-mem") {
1428 log_warning("Options -bv and -mem are now the default. Support for -bv and -mem will be removed in the future.\n");
1431 if (args
[argidx
] == "-stbv") {
1436 if (args
[argidx
] == "-stdt") {
1441 if (args
[argidx
] == "-nobv") {
1446 if (args
[argidx
] == "-nomem") {
1450 if (args
[argidx
] == "-wires") {
1454 if (args
[argidx
] == "-verbose") {
1460 extra_args(f
, filename
, args
, argidx
);
1462 if (template_f
.is_open()) {
1464 while (std::getline(template_f
, line
)) {
1466 while (indent
< GetSize(line
) && (line
[indent
] == ' ' || line
[indent
] == '\t'))
1468 if (line
.substr(indent
, 2) == "%%")
1470 *f
<< line
<< std::endl
;
1474 *f
<< stringf("; SMT-LIBv2 description generated by %s\n", yosys_version_str
);
1477 *f
<< stringf("; yosys-smt2-nobv\n");
1480 *f
<< stringf("; yosys-smt2-nomem\n");
1483 *f
<< stringf("; yosys-smt2-stbv\n");
1486 *f
<< stringf("; yosys-smt2-stdt\n");
1488 std::vector
<RTLIL::Module
*> sorted_modules
;
1490 // extract module dependencies
1491 std::map
<RTLIL::Module
*, std::set
<RTLIL::Module
*>> module_deps
;
1492 for (auto &mod_it
: design
->modules_
) {
1493 module_deps
[mod_it
.second
] = std::set
<RTLIL::Module
*>();
1494 for (auto &cell_it
: mod_it
.second
->cells_
)
1495 if (design
->modules_
.count(cell_it
.second
->type
) > 0)
1496 module_deps
[mod_it
.second
].insert(design
->modules_
.at(cell_it
.second
->type
));
1499 // simple good-enough topological sort
1500 // (O(n*m) on n elements and depth m)
1501 while (module_deps
.size() > 0) {
1502 size_t sorted_modules_idx
= sorted_modules
.size();
1503 for (auto &it
: module_deps
) {
1504 for (auto &dep
: it
.second
)
1505 if (module_deps
.count(dep
) > 0)
1507 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
1508 sorted_modules
.push_back(it
.first
);
1511 if (sorted_modules_idx
== sorted_modules
.size())
1512 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps
.begin()->first
->name
));
1513 while (sorted_modules_idx
< sorted_modules
.size())
1514 module_deps
.erase(sorted_modules
.at(sorted_modules_idx
++));
1517 dict
<IdString
, int> mod_stbv_width
;
1518 dict
<IdString
, dict
<IdString
, pair
<bool, bool>>> mod_clk_cache
;
1519 Module
*topmod
= design
->top_module();
1520 std::string topmod_id
;
1522 for (auto module
: sorted_modules
)
1523 for (auto cell
: module
->cells())
1524 if (cell
->type
.in("$allconst", "$allseq"))
1529 *f
<< stringf("; yosys-smt2-forall\n");
1530 if (!statebv
&& !statedt
)
1531 log_error("Forall-exists problems are only supported in -stbv or -stdt mode.\n");
1534 for (auto module
: sorted_modules
)
1536 if (module
->get_bool_attribute("\\blackbox") || module
->has_memories_warn() || module
->has_processes_warn())
1539 log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module
));
1541 Smt2Worker
worker(module
, bvmode
, memmode
, wiresmode
, verbose
, statebv
, statedt
, forallmode
, mod_stbv_width
, mod_clk_cache
);
1545 if (module
== topmod
)
1546 topmod_id
= worker
.get_id(module
);
1550 *f
<< stringf("; yosys-smt2-topmod %s\n", topmod_id
.c_str());
1552 *f
<< stringf("; end of yosys output\n");
1554 if (template_f
.is_open()) {
1556 while (std::getline(template_f
, line
))
1557 *f
<< line
<< std::endl
;
1562 PRIVATE_NAMESPACE_END