2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
28 PRIVATE_NAMESPACE_BEGIN
34 RTLIL::Module
*module
;
35 bool bvmode
, memmode
, wiresmode
, verbose
, statebv
, statedt
, forallmode
;
36 dict
<IdString
, int> &mod_stbv_width
;
37 int idcounter
= 0, statebv_width
= 0;
39 std::vector
<std::string
> decls
, trans
, hier
, dtmembers
;
40 std::map
<RTLIL::SigBit
, RTLIL::Cell
*> bit_driver
;
41 std::set
<RTLIL::Cell
*> exported_cells
, hiercells
, hiercells_queue
;
42 pool
<Cell
*> recursive_cells
, registers
;
44 pool
<SigBit
> clock_posedge
, clock_negedge
;
45 vector
<string
> ex_state_eq
, ex_input_eq
;
47 std::map
<RTLIL::SigBit
, std::pair
<int, int>> fcache
;
48 std::map
<Cell
*, int> memarrays
;
49 std::map
<int, int> bvsizes
;
50 dict
<IdString
, char*> ids
;
52 const char *get_id(IdString n
)
54 if (ids
.count(n
) == 0) {
55 std::string str
= log_id(n
);
56 for (int i
= 0; i
< GetSize(str
); i
++) {
60 ids
[n
] = strdup(str
.c_str());
66 const char *get_id(T
*obj
) {
67 return get_id(obj
->name
);
70 void makebits(std::string name
, int width
= 0, std::string comment
= std::string())
77 decl_str
= stringf("(define-fun |%s| ((state |%s_s|)) Bool (= ((_ extract %d %d) state) #b1))", name
.c_str(), get_id(module
), statebv_width
, statebv_width
);
80 decl_str
= stringf("(define-fun |%s| ((state |%s_s|)) (_ BitVec %d) ((_ extract %d %d) state))", name
.c_str(), get_id(module
), width
, statebv_width
+width
-1, statebv_width
);
81 statebv_width
+= width
;
87 decl_str
= stringf(" (|%s| Bool)", name
.c_str());
89 decl_str
= stringf(" (|%s| (_ BitVec %d))", name
.c_str(), width
);
95 decl_str
= stringf("(declare-fun |%s| (|%s_s|) Bool)", name
.c_str(), get_id(module
));
97 decl_str
= stringf("(declare-fun |%s| (|%s_s|) (_ BitVec %d))", name
.c_str(), get_id(module
), width
);
101 if (!comment
.empty())
102 decl_str
+= " ; " + comment
;
105 dtmembers
.push_back(decl_str
+ "\n");
107 decls
.push_back(decl_str
+ "\n");
110 Smt2Worker(RTLIL::Module
*module
, bool bvmode
, bool memmode
, bool wiresmode
, bool verbose
, bool statebv
, bool statedt
, bool forallmode
,
111 dict
<IdString
, int> &mod_stbv_width
, dict
<IdString
, dict
<IdString
, pair
<bool, bool>>> &mod_clk_cache
) :
112 ct(module
->design
), sigmap(module
), module(module
), bvmode(bvmode
), memmode(memmode
), wiresmode(wiresmode
),
113 verbose(verbose
), statebv(statebv
), statedt(statedt
), forallmode(forallmode
), mod_stbv_width(mod_stbv_width
)
115 pool
<SigBit
> noclock
;
117 makebits(stringf("%s_is", get_id(module
)));
119 for (auto cell
: module
->cells())
120 for (auto &conn
: cell
->connections())
122 if (GetSize(conn
.second
) == 0)
125 bool is_input
= ct
.cell_input(cell
->type
, conn
.first
);
126 bool is_output
= ct
.cell_output(cell
->type
, conn
.first
);
128 if (is_output
&& !is_input
)
129 for (auto bit
: sigmap(conn
.second
)) {
130 if (bit_driver
.count(bit
))
131 log_error("Found multiple drivers for %s.\n", log_signal(bit
));
132 bit_driver
[bit
] = cell
;
134 else if (is_output
|| !is_input
)
135 log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
136 log_id(conn
.first
), log_id(module
), log_id(cell
), log_id(cell
->type
));
138 if (cell
->type
.in("$mem") && conn
.first
.in("\\RD_CLK", "\\WR_CLK"))
140 SigSpec clk
= sigmap(conn
.second
);
141 for (int i
= 0; i
< GetSize(clk
); i
++)
143 if (clk
[i
].wire
== nullptr)
146 if (cell
->getParam(conn
.first
== "\\RD_CLK" ? "\\RD_CLK_ENABLE" : "\\WR_CLK_ENABLE")[i
] != State::S1
)
149 if (cell
->getParam(conn
.first
== "\\RD_CLK" ? "\\RD_CLK_POLARITY" : "\\WR_CLK_POLARITY")[i
] == State::S1
)
150 clock_posedge
.insert(clk
[i
]);
152 clock_negedge
.insert(clk
[i
]);
156 if (cell
->type
.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn
.first
.in("\\CLK", "\\C"))
158 bool posedge
= (cell
->type
== "$_DFF_N_") || (cell
->type
== "$dff" && cell
->getParam("\\CLK_POLARITY").as_bool());
159 for (auto bit
: sigmap(conn
.second
)) {
161 clock_posedge
.insert(bit
);
163 clock_negedge
.insert(bit
);
167 if (mod_clk_cache
.count(cell
->type
) && mod_clk_cache
.at(cell
->type
).count(conn
.first
))
169 for (auto bit
: sigmap(conn
.second
)) {
170 if (mod_clk_cache
.at(cell
->type
).at(conn
.first
).first
)
171 clock_posedge
.insert(bit
);
172 if (mod_clk_cache
.at(cell
->type
).at(conn
.first
).second
)
173 clock_negedge
.insert(bit
);
178 for (auto bit
: sigmap(conn
.second
))
183 for (auto bit
: noclock
) {
184 clock_posedge
.erase(bit
);
185 clock_negedge
.erase(bit
);
188 for (auto wire
: module
->wires())
190 if (!wire
->port_input
|| GetSize(wire
) != 1)
192 SigBit bit
= sigmap(wire
);
193 if (clock_posedge
.count(bit
))
194 mod_clk_cache
[module
->name
][wire
->name
].first
= true;
195 if (clock_negedge
.count(bit
))
196 mod_clk_cache
[module
->name
][wire
->name
].second
= true;
207 const char *get_id(Module
*m
)
209 return get_id(m
->name
);
212 const char *get_id(Cell
*c
)
214 return get_id(c
->name
);
217 const char *get_id(Wire
*w
)
219 return get_id(w
->name
);
222 void register_bool(RTLIL::SigBit bit
, int id
)
224 if (verbose
) log("%*s-> register_bool: %s %d\n", 2+2*GetSize(recursive_cells
), "",
225 log_signal(bit
), id
);
228 log_assert(fcache
.count(bit
) == 0);
229 fcache
[bit
] = std::pair
<int, int>(id
, -1);
232 void register_bv(RTLIL::SigSpec sig
, int id
)
234 if (verbose
) log("%*s-> register_bv: %s %d\n", 2+2*GetSize(recursive_cells
), "",
235 log_signal(sig
), id
);
240 log_assert(bvsizes
.count(id
) == 0);
241 bvsizes
[id
] = GetSize(sig
);
243 for (int i
= 0; i
< GetSize(sig
); i
++) {
244 log_assert(fcache
.count(sig
[i
]) == 0);
245 fcache
[sig
[i
]] = std::pair
<int, int>(id
, i
);
249 void register_boolvec(RTLIL::SigSpec sig
, int id
)
251 if (verbose
) log("%*s-> register_boolvec: %s %d\n", 2+2*GetSize(recursive_cells
), "",
252 log_signal(sig
), id
);
256 register_bool(sig
[0], id
);
258 for (int i
= 1; i
< GetSize(sig
); i
++)
259 sigmap
.add(sig
[i
], RTLIL::State::S0
);
262 std::string
get_bool(RTLIL::SigBit bit
, const char *state_name
= "state")
266 if (bit
.wire
== nullptr)
267 return bit
== RTLIL::State::S1
? "true" : "false";
269 if (bit_driver
.count(bit
))
270 export_cell(bit_driver
.at(bit
));
273 if (fcache
.count(bit
) == 0) {
274 if (verbose
) log("%*s-> external bool: %s\n", 2+2*GetSize(recursive_cells
), "",
276 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(bit
));
277 register_bool(bit
, idcounter
++);
280 auto f
= fcache
.at(bit
);
282 return stringf("(= ((_ extract %d %d) (|%s#%d| %s)) #b1)", f
.second
, f
.second
, get_id(module
), f
.first
, state_name
);
283 return stringf("(|%s#%d| %s)", get_id(module
), f
.first
, state_name
);
286 std::string
get_bool(RTLIL::SigSpec sig
, const char *state_name
= "state")
288 return get_bool(sig
.as_bit(), state_name
);
291 std::string
get_bv(RTLIL::SigSpec sig
, const char *state_name
= "state")
296 std::vector
<std::string
> subexpr
;
299 while (orig_sig
!= sig
) {
301 if (bit_driver
.count(bit
))
302 export_cell(bit_driver
.at(bit
));
307 for (int i
= 0, j
= 1; i
< GetSize(sig
); i
+= j
, j
= 1)
309 if (sig
[i
].wire
== nullptr) {
310 while (i
+j
< GetSize(sig
) && sig
[i
+j
].wire
== nullptr) j
++;
311 subexpr
.push_back("#b");
312 for (int k
= i
+j
-1; k
>= i
; k
--)
313 subexpr
.back() += sig
[k
] == RTLIL::State::S1
? "1" : "0";
317 if (fcache
.count(sig
[i
]) && fcache
.at(sig
[i
]).second
== -1) {
318 subexpr
.push_back(stringf("(ite %s #b1 #b0)", get_bool(sig
[i
], state_name
).c_str()));
322 if (fcache
.count(sig
[i
])) {
323 auto t1
= fcache
.at(sig
[i
]);
324 while (i
+j
< GetSize(sig
)) {
325 if (fcache
.count(sig
[i
+j
]) == 0)
327 auto t2
= fcache
.at(sig
[i
+j
]);
328 if (t1
.first
!= t2
.first
)
330 if (t1
.second
+j
!= t2
.second
)
334 if (t1
.second
== 0 && j
== bvsizes
.at(t1
.first
))
335 subexpr
.push_back(stringf("(|%s#%d| %s)", get_id(module
), t1
.first
, state_name
));
337 subexpr
.push_back(stringf("((_ extract %d %d) (|%s#%d| %s))",
338 t1
.second
+ j
- 1, t1
.second
, get_id(module
), t1
.first
, state_name
));
342 std::set
<RTLIL::SigBit
> seen_bits
= { sig
[i
] };
343 while (i
+j
< GetSize(sig
) && sig
[i
+j
].wire
&& !fcache
.count(sig
[i
+j
]) && !seen_bits
.count(sig
[i
+j
]))
344 seen_bits
.insert(sig
[i
+j
]), j
++;
346 if (verbose
) log("%*s-> external bv: %s\n", 2+2*GetSize(recursive_cells
), "",
347 log_signal(sig
.extract(i
, j
)));
348 for (auto bit
: sig
.extract(i
, j
))
349 log_assert(bit_driver
.count(bit
) == 0);
350 makebits(stringf("%s#%d", get_id(module
), idcounter
), j
, log_signal(sig
.extract(i
, j
)));
351 subexpr
.push_back(stringf("(|%s#%d| %s)", get_id(module
), idcounter
, state_name
));
352 register_bv(sig
.extract(i
, j
), idcounter
++);
355 if (GetSize(subexpr
) > 1) {
356 std::string expr
= "", end_str
= "";
357 for (int i
= GetSize(subexpr
)-1; i
>= 0; i
--) {
358 if (i
> 0) expr
+= " (concat", end_str
+= ")";
359 expr
+= " " + subexpr
[i
];
361 return expr
.substr(1) + end_str
;
363 log_assert(GetSize(subexpr
) == 1);
368 void export_gate(RTLIL::Cell
*cell
, std::string expr
)
370 RTLIL::SigBit bit
= sigmap(cell
->getPort("\\Y").as_bit());
371 std::string processed_expr
;
373 for (char ch
: expr
) {
374 if (ch
== 'A') processed_expr
+= get_bool(cell
->getPort("\\A"));
375 else if (ch
== 'B') processed_expr
+= get_bool(cell
->getPort("\\B"));
376 else if (ch
== 'C') processed_expr
+= get_bool(cell
->getPort("\\C"));
377 else if (ch
== 'D') processed_expr
+= get_bool(cell
->getPort("\\D"));
378 else if (ch
== 'S') processed_expr
+= get_bool(cell
->getPort("\\S"));
379 else processed_expr
+= ch
;
383 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
385 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
386 get_id(module
), idcounter
, get_id(module
), processed_expr
.c_str(), log_signal(bit
)));
387 register_bool(bit
, idcounter
++);
388 recursive_cells
.erase(cell
);
391 void export_bvop(RTLIL::Cell
*cell
, std::string expr
, char type
= 0)
393 RTLIL::SigSpec sig_a
, sig_b
;
394 RTLIL::SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
395 bool is_signed
= cell
->getParam("\\A_SIGNED").as_bool();
396 int width
= GetSize(sig_y
);
398 if (type
== 's' || type
== 'd' || type
== 'b') {
399 width
= max(width
, GetSize(cell
->getPort("\\A")));
400 if (cell
->hasPort("\\B"))
401 width
= max(width
, GetSize(cell
->getPort("\\B")));
404 if (cell
->hasPort("\\A")) {
405 sig_a
= cell
->getPort("\\A");
406 sig_a
.extend_u0(width
, is_signed
);
409 if (cell
->hasPort("\\B")) {
410 sig_b
= cell
->getPort("\\B");
411 sig_b
.extend_u0(width
, is_signed
&& !(type
== 's'));
414 std::string processed_expr
;
416 for (char ch
: expr
) {
417 if (ch
== 'A') processed_expr
+= get_bv(sig_a
);
418 else if (ch
== 'B') processed_expr
+= get_bv(sig_b
);
419 else if (ch
== 'P') processed_expr
+= get_bv(cell
->getPort("\\B"));
420 else if (ch
== 'L') processed_expr
+= is_signed
? "a" : "l";
421 else if (ch
== 'U') processed_expr
+= is_signed
? "s" : "u";
422 else processed_expr
+= ch
;
425 if (width
!= GetSize(sig_y
) && type
!= 'b')
426 processed_expr
= stringf("((_ extract %d 0) %s)", GetSize(sig_y
)-1, processed_expr
.c_str());
429 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
432 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
433 get_id(module
), idcounter
, get_id(module
), processed_expr
.c_str(), log_signal(sig_y
)));
434 register_boolvec(sig_y
, idcounter
++);
436 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
437 get_id(module
), idcounter
, get_id(module
), GetSize(sig_y
), processed_expr
.c_str(), log_signal(sig_y
)));
438 register_bv(sig_y
, idcounter
++);
441 recursive_cells
.erase(cell
);
444 void export_reduce(RTLIL::Cell
*cell
, std::string expr
, bool identity_val
)
446 RTLIL::SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
447 std::string processed_expr
;
450 if (ch
== 'A' || ch
== 'B') {
451 RTLIL::SigSpec sig
= sigmap(cell
->getPort(stringf("\\%c", ch
)));
453 processed_expr
+= " " + get_bool(bit
);
454 if (GetSize(sig
) == 1)
455 processed_expr
+= identity_val
? " true" : " false";
457 processed_expr
+= ch
;
460 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
462 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
463 get_id(module
), idcounter
, get_id(module
), processed_expr
.c_str(), log_signal(sig_y
)));
464 register_boolvec(sig_y
, idcounter
++);
465 recursive_cells
.erase(cell
);
468 void export_cell(RTLIL::Cell
*cell
)
471 log("%*s=> export_cell %s (%s) [%s]\n", 2+2*GetSize(recursive_cells
), "",
472 log_id(cell
), log_id(cell
->type
), exported_cells
.count(cell
) ? "old" : "new");
474 if (recursive_cells
.count(cell
))
475 log_error("Found logic loop in module %s! See cell %s.\n", get_id(module
), get_id(cell
));
477 if (exported_cells
.count(cell
))
480 exported_cells
.insert(cell
);
481 recursive_cells
.insert(cell
);
483 if (cell
->type
== "$initstate")
485 SigBit bit
= sigmap(cell
->getPort("\\Y").as_bit());
486 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
487 get_id(module
), idcounter
, get_id(module
), get_id(module
), log_signal(bit
)));
488 register_bool(bit
, idcounter
++);
489 recursive_cells
.erase(cell
);
493 if (cell
->type
.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
495 registers
.insert(cell
);
496 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(cell
->getPort("\\Q")));
497 register_bool(cell
->getPort("\\Q"), idcounter
++);
498 recursive_cells
.erase(cell
);
502 if (cell
->type
== "$_BUF_") return export_gate(cell
, "A");
503 if (cell
->type
== "$_NOT_") return export_gate(cell
, "(not A)");
504 if (cell
->type
== "$_AND_") return export_gate(cell
, "(and A B)");
505 if (cell
->type
== "$_NAND_") return export_gate(cell
, "(not (and A B))");
506 if (cell
->type
== "$_OR_") return export_gate(cell
, "(or A B)");
507 if (cell
->type
== "$_NOR_") return export_gate(cell
, "(not (or A B))");
508 if (cell
->type
== "$_XOR_") return export_gate(cell
, "(xor A B)");
509 if (cell
->type
== "$_XNOR_") return export_gate(cell
, "(not (xor A B))");
510 if (cell
->type
== "$_ANDNOT_") return export_gate(cell
, "(and A (not B))");
511 if (cell
->type
== "$_ORNOT_") return export_gate(cell
, "(or A (not B))");
512 if (cell
->type
== "$_MUX_") return export_gate(cell
, "(ite S B A)");
513 if (cell
->type
== "$_NMUX_") return export_gate(cell
, "(not (ite S B A))");
514 if (cell
->type
== "$_AOI3_") return export_gate(cell
, "(not (or (and A B) C))");
515 if (cell
->type
== "$_OAI3_") return export_gate(cell
, "(not (and (or A B) C))");
516 if (cell
->type
== "$_AOI4_") return export_gate(cell
, "(not (or (and A B) (and C D)))");
517 if (cell
->type
== "$_OAI4_") return export_gate(cell
, "(not (and (or A B) (or C D)))");
523 if (cell
->type
.in("$ff", "$dff"))
525 registers
.insert(cell
);
526 makebits(stringf("%s#%d", get_id(module
), idcounter
), GetSize(cell
->getPort("\\Q")), log_signal(cell
->getPort("\\Q")));
527 register_bv(cell
->getPort("\\Q"), idcounter
++);
528 recursive_cells
.erase(cell
);
532 if (cell
->type
.in("$anyconst", "$anyseq", "$allconst", "$allseq"))
534 registers
.insert(cell
);
535 string infostr
= cell
->attributes
.count("\\src") ? cell
->attributes
.at("\\src").decode_string().c_str() : get_id(cell
);
536 if (cell
->attributes
.count("\\reg"))
537 infostr
+= " " + cell
->attributes
.at("\\reg").decode_string();
538 decls
.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell
->type
.c_str() + 1, get_id(module
), idcounter
, GetSize(cell
->getPort("\\Y")), infostr
.c_str()));
539 makebits(stringf("%s#%d", get_id(module
), idcounter
), GetSize(cell
->getPort("\\Y")), log_signal(cell
->getPort("\\Y")));
540 if (cell
->type
== "$anyseq")
541 ex_input_eq
.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module
), idcounter
, get_id(module
), idcounter
));
542 register_bv(cell
->getPort("\\Y"), idcounter
++);
543 recursive_cells
.erase(cell
);
547 if (cell
->type
== "$and") return export_bvop(cell
, "(bvand A B)");
548 if (cell
->type
== "$or") return export_bvop(cell
, "(bvor A B)");
549 if (cell
->type
== "$xor") return export_bvop(cell
, "(bvxor A B)");
550 if (cell
->type
== "$xnor") return export_bvop(cell
, "(bvxnor A B)");
552 if (cell
->type
== "$shl") return export_bvop(cell
, "(bvshl A B)", 's');
553 if (cell
->type
== "$shr") return export_bvop(cell
, "(bvlshr A B)", 's');
554 if (cell
->type
== "$sshl") return export_bvop(cell
, "(bvshl A B)", 's');
555 if (cell
->type
== "$sshr") return export_bvop(cell
, "(bvLshr A B)", 's');
557 if (cell
->type
.in("$shift", "$shiftx")) {
558 if (cell
->getParam("\\B_SIGNED").as_bool()) {
559 return export_bvop(cell
, stringf("(ite (bvsge P #b%0*d) "
560 "(bvlshr A B) (bvlshr A (bvneg B)))",
561 GetSize(cell
->getPort("\\B")), 0), 's');
563 return export_bvop(cell
, "(bvlshr A B)", 's');
567 if (cell
->type
== "$lt") return export_bvop(cell
, "(bvUlt A B)", 'b');
568 if (cell
->type
== "$le") return export_bvop(cell
, "(bvUle A B)", 'b');
569 if (cell
->type
== "$ge") return export_bvop(cell
, "(bvUge A B)", 'b');
570 if (cell
->type
== "$gt") return export_bvop(cell
, "(bvUgt A B)", 'b');
572 if (cell
->type
== "$ne") return export_bvop(cell
, "(distinct A B)", 'b');
573 if (cell
->type
== "$nex") return export_bvop(cell
, "(distinct A B)", 'b');
574 if (cell
->type
== "$eq") return export_bvop(cell
, "(= A B)", 'b');
575 if (cell
->type
== "$eqx") return export_bvop(cell
, "(= A B)", 'b');
577 if (cell
->type
== "$not") return export_bvop(cell
, "(bvnot A)");
578 if (cell
->type
== "$pos") return export_bvop(cell
, "A");
579 if (cell
->type
== "$neg") return export_bvop(cell
, "(bvneg A)");
581 if (cell
->type
== "$add") return export_bvop(cell
, "(bvadd A B)");
582 if (cell
->type
== "$sub") return export_bvop(cell
, "(bvsub A B)");
583 if (cell
->type
== "$mul") return export_bvop(cell
, "(bvmul A B)");
584 if (cell
->type
== "$div") return export_bvop(cell
, "(bvUdiv A B)", 'd');
585 if (cell
->type
== "$mod") return export_bvop(cell
, "(bvUrem A B)", 'd');
587 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_bool") &&
588 2*GetSize(cell
->getPort("\\A").chunks()) < GetSize(cell
->getPort("\\A"))) {
589 bool is_and
= cell
->type
== "$reduce_and";
590 string
bits(GetSize(cell
->getPort("\\A")), is_and
? '1' : '0');
591 return export_bvop(cell
, stringf("(%s A #b%s)", is_and
? "=" : "distinct", bits
.c_str()), 'b');
594 if (cell
->type
== "$reduce_and") return export_reduce(cell
, "(and A)", true);
595 if (cell
->type
== "$reduce_or") return export_reduce(cell
, "(or A)", false);
596 if (cell
->type
== "$reduce_xor") return export_reduce(cell
, "(xor A)", false);
597 if (cell
->type
== "$reduce_xnor") return export_reduce(cell
, "(not (xor A))", false);
598 if (cell
->type
== "$reduce_bool") return export_reduce(cell
, "(or A)", false);
600 if (cell
->type
== "$logic_not") return export_reduce(cell
, "(not (or A))", false);
601 if (cell
->type
== "$logic_and") return export_reduce(cell
, "(and (or A) (or B))", false);
602 if (cell
->type
== "$logic_or") return export_reduce(cell
, "(or A B)", false);
604 if (cell
->type
.in("$mux", "$pmux"))
606 int width
= GetSize(cell
->getPort("\\Y"));
607 std::string processed_expr
= get_bv(cell
->getPort("\\A"));
609 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
610 RTLIL::SigSpec sig_s
= cell
->getPort("\\S");
614 for (int i
= 0; i
< GetSize(sig_s
); i
++)
615 processed_expr
= stringf("(ite %s %s %s)", get_bool(sig_s
[i
]).c_str(),
616 get_bv(sig_b
.extract(i
*width
, width
)).c_str(), processed_expr
.c_str());
619 log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells
), "", log_id(cell
));
621 RTLIL::SigSpec sig
= sigmap(cell
->getPort("\\Y"));
622 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
623 get_id(module
), idcounter
, get_id(module
), width
, processed_expr
.c_str(), log_signal(sig
)));
624 register_bv(sig
, idcounter
++);
625 recursive_cells
.erase(cell
);
629 // FIXME: $slice $concat
632 if (memmode
&& cell
->type
== "$mem")
634 int arrayid
= idcounter
++;
635 memarrays
[cell
] = arrayid
;
637 int abits
= cell
->getParam("\\ABITS").as_int();
638 int width
= cell
->getParam("\\WIDTH").as_int();
639 int rd_ports
= cell
->getParam("\\RD_PORTS").as_int();
640 int wr_ports
= cell
->getParam("\\WR_PORTS").as_int();
642 bool async_read
= false;
643 if (!cell
->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
644 if (!cell
->getParam("\\WR_CLK_ENABLE").is_fully_zero())
645 log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell
), log_id(module
));
649 decls
.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", get_id(cell
), abits
, width
, rd_ports
, wr_ports
, async_read
? "async" : "sync"));
653 memstate
= stringf("%s#%d#final", get_id(module
), arrayid
);
655 memstate
= stringf("%s#%d#0", get_id(module
), arrayid
);
660 int mem_size
= cell
->getParam("\\SIZE").as_int();
661 int mem_offset
= cell
->getParam("\\OFFSET").as_int();
663 makebits(memstate
, width
*mem_size
, get_id(cell
));
664 decls
.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n",
665 get_id(module
), get_id(cell
), get_id(module
), width
*mem_size
, memstate
.c_str()));
667 for (int i
= 0; i
< rd_ports
; i
++)
669 SigSpec addr_sig
= cell
->getPort("\\RD_ADDR").extract(abits
*i
, abits
);
670 SigSpec data_sig
= cell
->getPort("\\RD_DATA").extract(width
*i
, width
);
671 std::string addr
= get_bv(addr_sig
);
673 if (cell
->getParam("\\RD_CLK_ENABLE").extract(i
).as_bool())
674 log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
675 "Call \"memory\" with -nordff to avoid this error.\n", i
, log_signal(data_sig
), log_id(cell
), log_id(module
));
677 decls
.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
678 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
680 std::string read_expr
= "#b";
681 for (int k
= 0; k
< width
; k
++)
684 for (int k
= 0; k
< mem_size
; k
++)
685 read_expr
= stringf("(ite (= (|%s_m:R%dA %s| state) #b%s) ((_ extract %d %d) (|%s| state))\n %s)",
686 get_id(module
), i
, get_id(cell
), Const(k
+mem_offset
, abits
).as_string().c_str(),
687 width
*(k
+1)-1, width
*k
, memstate
.c_str(), read_expr
.c_str());
689 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d)\n %s) ; %s\n",
690 get_id(module
), idcounter
, get_id(module
), width
, read_expr
.c_str(), log_signal(data_sig
)));
692 decls
.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
693 get_id(module
), i
, get_id(cell
), get_id(module
), width
, get_id(module
), idcounter
));
695 register_bv(data_sig
, idcounter
++);
701 dtmembers
.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
702 memstate
.c_str(), abits
, width
, get_id(cell
)));
704 decls
.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
705 memstate
.c_str(), get_id(module
), abits
, width
, get_id(cell
)));
707 decls
.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s| state))\n",
708 get_id(module
), get_id(cell
), get_id(module
), abits
, width
, memstate
.c_str()));
710 for (int i
= 0; i
< rd_ports
; i
++)
712 SigSpec addr_sig
= cell
->getPort("\\RD_ADDR").extract(abits
*i
, abits
);
713 SigSpec data_sig
= cell
->getPort("\\RD_DATA").extract(width
*i
, width
);
714 std::string addr
= get_bv(addr_sig
);
716 if (cell
->getParam("\\RD_CLK_ENABLE").extract(i
).as_bool())
717 log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
718 "Call \"memory\" with -nordff to avoid this error.\n", i
, log_signal(data_sig
), log_id(cell
), log_id(module
));
720 decls
.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
721 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
723 decls
.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s| state) (|%s_m:R%dA %s| state))) ; %s\n",
724 get_id(module
), idcounter
, get_id(module
), width
, memstate
.c_str(), get_id(module
), i
, get_id(cell
), log_signal(data_sig
)));
726 decls
.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
727 get_id(module
), i
, get_id(cell
), get_id(module
), width
, get_id(module
), idcounter
));
729 register_bv(data_sig
, idcounter
++);
733 registers
.insert(cell
);
734 recursive_cells
.erase(cell
);
738 Module
*m
= module
->design
->module(cell
->type
);
742 decls
.push_back(stringf("; yosys-smt2-cell %s %s\n", get_id(cell
->type
), get_id(cell
->name
)));
743 string cell_state
= stringf("(|%s_h %s| state)", get_id(module
), get_id(cell
->name
));
745 for (auto &conn
: cell
->connections())
747 if (GetSize(conn
.second
) == 0)
750 Wire
*w
= m
->wire(conn
.first
);
751 SigSpec sig
= sigmap(conn
.second
);
753 if (w
->port_output
&& !w
->port_input
) {
754 if (GetSize(w
) > 1) {
756 makebits(stringf("%s#%d", get_id(module
), idcounter
), GetSize(w
), log_signal(sig
));
757 register_bv(sig
, idcounter
++);
759 for (int i
= 0; i
< GetSize(w
); i
++) {
760 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(sig
[i
]));
761 register_bool(sig
[i
], idcounter
++);
765 makebits(stringf("%s#%d", get_id(module
), idcounter
), 0, log_signal(sig
));
766 register_bool(sig
, idcounter
++);
772 makebits(stringf("%s_h %s", get_id(module
), get_id(cell
->name
)), mod_stbv_width
.at(cell
->type
));
774 dtmembers
.push_back(stringf(" (|%s_h %s| |%s_s|)\n",
775 get_id(module
), get_id(cell
->name
), get_id(cell
->type
)));
777 decls
.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
778 get_id(module
), get_id(cell
->name
), get_id(module
), get_id(cell
->type
)));
780 hiercells
.insert(cell
);
781 hiercells_queue
.insert(cell
);
782 recursive_cells
.erase(cell
);
786 log_error("Unsupported cell type %s for cell %s.%s.\n",
787 log_id(cell
->type
), log_id(module
), log_id(cell
));
792 if (verbose
) log("=> export logic driving outputs\n");
794 pool
<SigBit
> reg_bits
;
795 for (auto cell
: module
->cells())
796 if (cell
->type
.in("$ff", "$dff", "$_FF_", "$_DFF_P_", "$_DFF_N_")) {
797 // not using sigmap -- we want the net directly at the dff output
798 for (auto bit
: cell
->getPort("\\Q"))
799 reg_bits
.insert(bit
);
802 for (auto wire
: module
->wires()) {
803 bool is_register
= false;
804 for (auto bit
: SigSpec(wire
))
805 if (reg_bits
.count(bit
))
807 if (wire
->port_id
|| is_register
|| wire
->get_bool_attribute("\\keep") || (wiresmode
&& wire
->name
[0] == '\\')) {
808 RTLIL::SigSpec sig
= sigmap(wire
);
809 if (wire
->port_input
)
810 decls
.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire
), wire
->width
));
811 if (wire
->port_output
)
812 decls
.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire
), wire
->width
));
814 decls
.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire
), wire
->width
));
815 if (wire
->get_bool_attribute("\\keep") || (wiresmode
&& wire
->name
[0] == '\\'))
816 decls
.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire
), wire
->width
));
817 if (GetSize(wire
) == 1 && (clock_posedge
.count(sig
) || clock_negedge
.count(sig
)))
818 decls
.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire
),
819 clock_posedge
.count(sig
) ? " posedge" : "", clock_negedge
.count(sig
) ? " negedge" : ""));
820 if (bvmode
&& GetSize(sig
) > 1) {
821 decls
.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
822 get_id(module
), get_id(wire
), get_id(module
), GetSize(sig
), get_bv(sig
).c_str()));
823 if (wire
->port_input
)
824 ex_input_eq
.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
825 get_id(module
), get_id(wire
), get_id(module
), get_id(wire
)));
827 for (int i
= 0; i
< GetSize(sig
); i
++)
828 if (GetSize(sig
) > 1) {
829 decls
.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
830 get_id(module
), get_id(wire
), i
, get_id(module
), get_bool(sig
[i
]).c_str()));
831 if (wire
->port_input
)
832 ex_input_eq
.push_back(stringf(" (= (|%s_n %s %d| state) (|%s_n %s %d| other_state))",
833 get_id(module
), get_id(wire
), i
, get_id(module
), get_id(wire
), i
));
835 decls
.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
836 get_id(module
), get_id(wire
), get_id(module
), get_bool(sig
[i
]).c_str()));
837 if (wire
->port_input
)
838 ex_input_eq
.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
839 get_id(module
), get_id(wire
), get_id(module
), get_id(wire
)));
845 if (verbose
) log("=> export logic associated with the initial state\n");
847 vector
<string
> init_list
;
848 for (auto wire
: module
->wires())
849 if (wire
->attributes
.count("\\init")) {
850 RTLIL::SigSpec sig
= sigmap(wire
);
851 Const val
= wire
->attributes
.at("\\init");
852 val
.bits
.resize(GetSize(sig
), State::Sx
);
853 if (bvmode
&& GetSize(sig
) > 1) {
854 Const
mask(State::S1
, GetSize(sig
));
855 bool use_mask
= false;
856 for (int i
= 0; i
< GetSize(sig
); i
++)
857 if (val
[i
] != State::S0
&& val
[i
] != State::S1
) {
863 init_list
.push_back(stringf("(= (bvand %s #b%s) #b%s) ; %s", get_bv(sig
).c_str(), mask
.as_string().c_str(), val
.as_string().c_str(), get_id(wire
)));
865 init_list
.push_back(stringf("(= %s #b%s) ; %s", get_bv(sig
).c_str(), val
.as_string().c_str(), get_id(wire
)));
867 for (int i
= 0; i
< GetSize(sig
); i
++)
868 if (val
[i
] == State::S0
|| val
[i
] == State::S1
)
869 init_list
.push_back(stringf("(= %s %s) ; %s", get_bool(sig
[i
]).c_str(), val
[i
] == State::S1
? "true" : "false", get_id(wire
)));
873 if (verbose
) log("=> export logic driving asserts\n");
875 int assert_id
= 0, assume_id
= 0, cover_id
= 0;
876 vector
<string
> assert_list
, assume_list
, cover_list
;
878 for (auto cell
: module
->cells())
880 if (cell
->type
.in("$assert", "$assume", "$cover"))
882 int &id
= cell
->type
== "$assert" ? assert_id
:
883 cell
->type
== "$assume" ? assume_id
:
884 cell
->type
== "$cover" ? cover_id
: *(int*)nullptr;
886 char postfix
= cell
->type
== "$assert" ? 'a' :
887 cell
->type
== "$assume" ? 'u' :
888 cell
->type
== "$cover" ? 'c' : 0;
890 string name_a
= get_bool(cell
->getPort("\\A"));
891 string name_en
= get_bool(cell
->getPort("\\EN"));
892 string infostr
= (cell
->name
[0] == '$' && cell
->attributes
.count("\\src")) ? cell
->attributes
.at("\\src").decode_string() : get_id(cell
);
893 decls
.push_back(stringf("; yosys-smt2-%s %d %s\n", cell
->type
.c_str() + 1, id
, infostr
.c_str()));
895 if (cell
->type
== "$cover")
896 decls
.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
897 get_id(module
), postfix
, id
, get_id(module
), name_a
.c_str(), name_en
.c_str(), get_id(cell
)));
899 decls
.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n",
900 get_id(module
), postfix
, id
, get_id(module
), name_a
.c_str(), name_en
.c_str(), get_id(cell
)));
902 if (cell
->type
== "$assert")
903 assert_list
.push_back(stringf("(|%s_a %d| state)", get_id(module
), id
));
904 else if (cell
->type
== "$assume")
905 assume_list
.push_back(stringf("(|%s_u %d| state)", get_id(module
), id
));
911 if (verbose
) log("=> export logic driving hierarchical cells\n");
913 for (auto cell
: module
->cells())
914 if (module
->design
->module(cell
->type
) != nullptr)
917 while (!hiercells_queue
.empty())
919 std::set
<RTLIL::Cell
*> queue
;
920 queue
.swap(hiercells_queue
);
922 for (auto cell
: queue
)
924 string cell_state
= stringf("(|%s_h %s| state)", get_id(module
), get_id(cell
->name
));
925 Module
*m
= module
->design
->module(cell
->type
);
926 log_assert(m
!= nullptr);
928 hier
.push_back(stringf(" (= (|%s_is| state) (|%s_is| %s))\n",
929 get_id(module
), get_id(cell
->type
), cell_state
.c_str()));
931 for (auto &conn
: cell
->connections())
933 if (GetSize(conn
.second
) == 0)
936 Wire
*w
= m
->wire(conn
.first
);
937 SigSpec sig
= sigmap(conn
.second
);
939 if (bvmode
|| GetSize(w
) == 1) {
940 hier
.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w
) > 1 ? get_bv(sig
) : get_bool(sig
)).c_str(),
941 get_id(cell
->type
), get_id(w
), cell_state
.c_str(), get_id(cell
->type
), get_id(w
)));
943 for (int i
= 0; i
< GetSize(w
); i
++)
944 hier
.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig
[i
]).c_str(),
945 get_id(cell
->type
), get_id(w
), i
, cell_state
.c_str(), get_id(cell
->type
), get_id(w
), i
));
951 for (int iter
= 1; !registers
.empty(); iter
++)
953 pool
<Cell
*> this_regs
;
954 this_regs
.swap(registers
);
956 if (verbose
) log("=> export logic driving registers [iteration %d]\n", iter
);
958 for (auto cell
: this_regs
)
960 if (cell
->type
.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
962 std::string expr_d
= get_bool(cell
->getPort("\\D"));
963 std::string expr_q
= get_bool(cell
->getPort("\\Q"), "next_state");
964 trans
.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
), log_signal(cell
->getPort("\\Q"))));
965 ex_state_eq
.push_back(stringf("(= %s %s)", get_bool(cell
->getPort("\\Q")).c_str(), get_bool(cell
->getPort("\\Q"), "other_state").c_str()));
968 if (cell
->type
.in("$ff", "$dff"))
970 std::string expr_d
= get_bv(cell
->getPort("\\D"));
971 std::string expr_q
= get_bv(cell
->getPort("\\Q"), "next_state");
972 trans
.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
), log_signal(cell
->getPort("\\Q"))));
973 ex_state_eq
.push_back(stringf("(= %s %s)", get_bv(cell
->getPort("\\Q")).c_str(), get_bv(cell
->getPort("\\Q"), "other_state").c_str()));
976 if (cell
->type
.in("$anyconst", "$allconst"))
978 std::string expr_d
= get_bv(cell
->getPort("\\Y"));
979 std::string expr_q
= get_bv(cell
->getPort("\\Y"), "next_state");
980 trans
.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
), log_signal(cell
->getPort("\\Y"))));
981 if (cell
->type
== "$anyconst")
982 ex_state_eq
.push_back(stringf("(= %s %s)", get_bv(cell
->getPort("\\Y")).c_str(), get_bv(cell
->getPort("\\Y"), "other_state").c_str()));
985 if (cell
->type
== "$mem")
987 int arrayid
= memarrays
.at(cell
);
989 int abits
= cell
->getParam("\\ABITS").as_int();
990 int width
= cell
->getParam("\\WIDTH").as_int();
991 int wr_ports
= cell
->getParam("\\WR_PORTS").as_int();
993 bool async_read
= false;
994 string initial_memstate
, final_memstate
;
996 if (!cell
->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
997 log_assert(cell
->getParam("\\WR_CLK_ENABLE").is_fully_zero());
999 initial_memstate
= stringf("%s#%d#0", get_id(module
), arrayid
);
1000 final_memstate
= stringf("%s#%d#final", get_id(module
), arrayid
);
1005 int mem_size
= cell
->getParam("\\SIZE").as_int();
1006 int mem_offset
= cell
->getParam("\\OFFSET").as_int();
1009 makebits(final_memstate
, width
*mem_size
, get_id(cell
));
1012 for (int i
= 0; i
< wr_ports
; i
++)
1014 SigSpec addr_sig
= cell
->getPort("\\WR_ADDR").extract(abits
*i
, abits
);
1015 SigSpec data_sig
= cell
->getPort("\\WR_DATA").extract(width
*i
, width
);
1016 SigSpec mask_sig
= cell
->getPort("\\WR_EN").extract(width
*i
, width
);
1018 std::string addr
= get_bv(addr_sig
);
1019 std::string data
= get_bv(data_sig
);
1020 std::string mask
= get_bv(mask_sig
);
1022 decls
.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1023 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
1024 addr
= stringf("(|%s_m:W%dA %s| state)", get_id(module
), i
, get_id(cell
));
1026 decls
.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1027 get_id(module
), i
, get_id(cell
), get_id(module
), width
, data
.c_str(), log_signal(data_sig
)));
1028 data
= stringf("(|%s_m:W%dD %s| state)", get_id(module
), i
, get_id(cell
));
1030 decls
.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1031 get_id(module
), i
, get_id(cell
), get_id(module
), width
, mask
.c_str(), log_signal(mask_sig
)));
1032 mask
= stringf("(|%s_m:W%dM %s| state)", get_id(module
), i
, get_id(cell
));
1034 std::string data_expr
;
1036 for (int k
= mem_size
-1; k
>= 0; k
--) {
1037 std::string new_data
= stringf("(bvor (bvand %s %s) (bvand ((_ extract %d %d) (|%s#%d#%d| state)) (bvnot %s)))",
1038 data
.c_str(), mask
.c_str(), width
*(k
+1)-1, width
*k
, get_id(module
), arrayid
, i
, mask
.c_str());
1039 data_expr
+= stringf("\n (ite (= %s #b%s) %s ((_ extract %d %d) (|%s#%d#%d| state)))",
1040 addr
.c_str(), Const(k
+mem_offset
, abits
).as_string().c_str(), new_data
.c_str(),
1041 width
*(k
+1)-1, width
*k
, get_id(module
), arrayid
, i
);
1044 decls
.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (_ BitVec %d) (concat%s)) ; %s\n",
1045 get_id(module
), arrayid
, i
+1, get_id(module
), width
*mem_size
, data_expr
.c_str(), get_id(cell
)));
1052 dtmembers
.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
1053 initial_memstate
.c_str(), abits
, width
, get_id(cell
)));
1055 decls
.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
1056 initial_memstate
.c_str(), get_id(module
), abits
, width
, get_id(cell
)));
1059 for (int i
= 0; i
< wr_ports
; i
++)
1061 SigSpec addr_sig
= cell
->getPort("\\WR_ADDR").extract(abits
*i
, abits
);
1062 SigSpec data_sig
= cell
->getPort("\\WR_DATA").extract(width
*i
, width
);
1063 SigSpec mask_sig
= cell
->getPort("\\WR_EN").extract(width
*i
, width
);
1065 std::string addr
= get_bv(addr_sig
);
1066 std::string data
= get_bv(data_sig
);
1067 std::string mask
= get_bv(mask_sig
);
1069 decls
.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1070 get_id(module
), i
, get_id(cell
), get_id(module
), abits
, addr
.c_str(), log_signal(addr_sig
)));
1071 addr
= stringf("(|%s_m:W%dA %s| state)", get_id(module
), i
, get_id(cell
));
1073 decls
.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1074 get_id(module
), i
, get_id(cell
), get_id(module
), width
, data
.c_str(), log_signal(data_sig
)));
1075 data
= stringf("(|%s_m:W%dD %s| state)", get_id(module
), i
, get_id(cell
));
1077 decls
.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
1078 get_id(module
), i
, get_id(cell
), get_id(module
), width
, mask
.c_str(), log_signal(mask_sig
)));
1079 mask
= stringf("(|%s_m:W%dM %s| state)", get_id(module
), i
, get_id(cell
));
1081 data
= stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
1082 data
.c_str(), mask
.c_str(), get_id(module
), arrayid
, i
, addr
.c_str(), mask
.c_str());
1084 decls
.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
1085 "(store (|%s#%d#%d| state) %s %s)) ; %s\n",
1086 get_id(module
), arrayid
, i
+1, get_id(module
), abits
, width
,
1087 get_id(module
), arrayid
, i
, addr
.c_str(), data
.c_str(), get_id(cell
)));
1091 std::string expr_d
= stringf("(|%s#%d#%d| state)", get_id(module
), arrayid
, wr_ports
);
1092 std::string expr_q
= stringf("(|%s#%d#0| next_state)", get_id(module
), arrayid
);
1093 trans
.push_back(stringf(" (= %s %s) ; %s\n", expr_d
.c_str(), expr_q
.c_str(), get_id(cell
)));
1094 ex_state_eq
.push_back(stringf("(= (|%s#%d#0| state) (|%s#%d#0| other_state))", get_id(module
), arrayid
, get_id(module
), arrayid
));
1097 hier
.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d
.c_str(), final_memstate
.c_str(), get_id(cell
)));
1099 Const init_data
= cell
->getParam("\\INIT");
1100 int memsize
= cell
->getParam("\\SIZE").as_int();
1102 for (int i
= 0; i
< memsize
; i
++)
1104 if (i
*width
>= GetSize(init_data
))
1107 Const initword
= init_data
.extract(i
*width
, width
, State::Sx
);
1108 Const initmask
= initword
;
1109 bool gen_init_constr
= false;
1111 for (int k
= 0; k
< GetSize(initword
); k
++) {
1112 if (initword
[k
] == State::S0
|| initword
[k
] == State::S1
) {
1113 gen_init_constr
= true;
1114 initmask
[k
] = State::S1
;
1116 initmask
[k
] = State::S0
;
1117 initword
[k
] = State::S0
;
1121 if (gen_init_constr
)
1126 init_list
.push_back(stringf("(= (bvand (select (|%s#%d#0| state) #b%s) #b%s) #b%s) ; %s[%d]",
1127 get_id(module
), arrayid
, Const(i
, abits
).as_string().c_str(),
1128 initmask
.as_string().c_str(), initword
.as_string().c_str(), get_id(cell
), i
));
1135 if (verbose
) log("=> finalizing SMT2 representation of %s.\n", log_id(module
));
1137 for (auto c
: hiercells
) {
1138 assert_list
.push_back(stringf("(|%s_a| (|%s_h %s| state))", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1139 assume_list
.push_back(stringf("(|%s_u| (|%s_h %s| state))", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1140 init_list
.push_back(stringf("(|%s_i| (|%s_h %s| state))", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1141 hier
.push_back(stringf(" (|%s_h| (|%s_h %s| state))\n", get_id(c
->type
), get_id(module
), get_id(c
->name
)));
1142 trans
.push_back(stringf(" (|%s_t| (|%s_h %s| state) (|%s_h %s| next_state))\n",
1143 get_id(c
->type
), get_id(module
), get_id(c
->name
), get_id(module
), get_id(c
->name
)));
1144 ex_state_eq
.push_back(stringf("(|%s_ex_state_eq| (|%s_h %s| state) (|%s_h %s| other_state))\n",
1145 get_id(c
->type
), get_id(module
), get_id(c
->name
), get_id(module
), get_id(c
->name
)));
1150 string expr
= ex_state_eq
.empty() ? "true" : "(and";
1151 if (!ex_state_eq
.empty()) {
1152 if (GetSize(ex_state_eq
) == 1) {
1153 expr
= "\n " + ex_state_eq
.front() + "\n";
1155 for (auto &str
: ex_state_eq
)
1156 expr
+= stringf("\n %s", str
.c_str());
1160 decls
.push_back(stringf("(define-fun |%s_ex_state_eq| ((state |%s_s|) (other_state |%s_s|)) Bool %s)\n",
1161 get_id(module
), get_id(module
), get_id(module
), expr
.c_str()));
1163 expr
= ex_input_eq
.empty() ? "true" : "(and";
1164 if (!ex_input_eq
.empty()) {
1165 if (GetSize(ex_input_eq
) == 1) {
1166 expr
= "\n " + ex_input_eq
.front() + "\n";
1168 for (auto &str
: ex_input_eq
)
1169 expr
+= stringf("\n %s", str
.c_str());
1173 decls
.push_back(stringf("(define-fun |%s_ex_input_eq| ((state |%s_s|) (other_state |%s_s|)) Bool %s)\n",
1174 get_id(module
), get_id(module
), get_id(module
), expr
.c_str()));
1177 string assert_expr
= assert_list
.empty() ? "true" : "(and";
1178 if (!assert_list
.empty()) {
1179 if (GetSize(assert_list
) == 1) {
1180 assert_expr
= "\n " + assert_list
.front() + "\n";
1182 for (auto &str
: assert_list
)
1183 assert_expr
+= stringf("\n %s", str
.c_str());
1184 assert_expr
+= "\n)";
1187 decls
.push_back(stringf("(define-fun |%s_a| ((state |%s_s|)) Bool %s)\n",
1188 get_id(module
), get_id(module
), assert_expr
.c_str()));
1190 string assume_expr
= assume_list
.empty() ? "true" : "(and";
1191 if (!assume_list
.empty()) {
1192 if (GetSize(assume_list
) == 1) {
1193 assume_expr
= "\n " + assume_list
.front() + "\n";
1195 for (auto &str
: assume_list
)
1196 assume_expr
+= stringf("\n %s", str
.c_str());
1197 assume_expr
+= "\n)";
1200 decls
.push_back(stringf("(define-fun |%s_u| ((state |%s_s|)) Bool %s)\n",
1201 get_id(module
), get_id(module
), assume_expr
.c_str()));
1203 string init_expr
= init_list
.empty() ? "true" : "(and";
1204 if (!init_list
.empty()) {
1205 if (GetSize(init_list
) == 1) {
1206 init_expr
= "\n " + init_list
.front() + "\n";
1208 for (auto &str
: init_list
)
1209 init_expr
+= stringf("\n %s", str
.c_str());
1213 decls
.push_back(stringf("(define-fun |%s_i| ((state |%s_s|)) Bool %s)\n",
1214 get_id(module
), get_id(module
), init_expr
.c_str()));
1217 void write(std::ostream
&f
)
1219 f
<< stringf("; yosys-smt2-module %s\n", get_id(module
));
1222 f
<< stringf("(define-sort |%s_s| () (_ BitVec %d))\n", get_id(module
), statebv_width
);
1223 mod_stbv_width
[module
->name
] = statebv_width
;
1226 f
<< stringf("(declare-datatype |%s_s| ((|%s_mk|\n", get_id(module
), get_id(module
));
1227 for (auto it
: dtmembers
)
1229 f
<< stringf(")))\n");
1231 f
<< stringf("(declare-sort |%s_s| 0)\n", get_id(module
));
1233 for (auto it
: decls
)
1236 f
<< stringf("(define-fun |%s_h| ((state |%s_s|)) Bool ", get_id(module
), get_id(module
));
1237 if (GetSize(hier
) > 1) {
1239 for (auto it
: hier
)
1243 if (GetSize(hier
) == 1)
1244 f
<< "\n" + hier
.front() + ")\n";
1248 f
<< stringf("(define-fun |%s_t| ((state |%s_s|) (next_state |%s_s|)) Bool ", get_id(module
), get_id(module
), get_id(module
));
1249 if (GetSize(trans
) > 1) {
1251 for (auto it
: trans
)
1255 if (GetSize(trans
) == 1)
1256 f
<< "\n" + trans
.front() + ")";
1259 f
<< stringf(" ; end of module %s\n", get_id(module
));
1263 struct Smt2Backend
: public Backend
{
1264 Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
1265 void help() YS_OVERRIDE
1267 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1269 log(" write_smt2 [options] [filename]\n");
1271 log("Write a SMT-LIBv2 [1] description of the current design. For a module with name\n");
1272 log("'<mod>' this will declare the sort '<mod>_s' (state of the module) and will\n");
1273 log("define and declare functions operating on that state.\n");
1275 log("The following SMT2 functions are generated for a module with name '<mod>'.\n");
1276 log("Some declarations/definitions are printed with a special comment. A prover\n");
1277 log("using the SMT2 files can use those comments to collect all relevant metadata\n");
1278 log("about the design.\n");
1280 log(" ; yosys-smt2-module <mod>\n");
1281 log(" (declare-sort |<mod>_s| 0)\n");
1282 log(" The sort representing a state of module <mod>.\n");
1284 log(" (define-fun |<mod>_h| ((state |<mod>_s|)) Bool (...))\n");
1285 log(" This function must be asserted for each state to establish the\n");
1286 log(" design hierarchy.\n");
1288 log(" ; yosys-smt2-input <wirename> <width>\n");
1289 log(" ; yosys-smt2-output <wirename> <width>\n");
1290 log(" ; yosys-smt2-register <wirename> <width>\n");
1291 log(" ; yosys-smt2-wire <wirename> <width>\n");
1292 log(" (define-fun |<mod>_n <wirename>| (|<mod>_s|) (_ BitVec <width>))\n");
1293 log(" (define-fun |<mod>_n <wirename>| (|<mod>_s|) Bool)\n");
1294 log(" For each port, register, and wire with the 'keep' attribute set an\n");
1295 log(" accessor function is generated. Single-bit wires are returned as Bool,\n");
1296 log(" multi-bit wires as BitVec.\n");
1298 log(" ; yosys-smt2-cell <submod> <instancename>\n");
1299 log(" (declare-fun |<mod>_h <instancename>| (|<mod>_s|) |<submod>_s|)\n");
1300 log(" There is a function like that for each hierarchical instance. It\n");
1301 log(" returns the sort that represents the state of the sub-module that\n");
1302 log(" implements the instance.\n");
1304 log(" (declare-fun |<mod>_is| (|<mod>_s|) Bool)\n");
1305 log(" This function must be asserted 'true' for initial states, and 'false'\n");
1306 log(" otherwise.\n");
1308 log(" (define-fun |<mod>_i| ((state |<mod>_s|)) Bool (...))\n");
1309 log(" This function must be asserted 'true' for initial states. For\n");
1310 log(" non-initial states it must be left unconstrained.\n");
1312 log(" (define-fun |<mod>_t| ((state |<mod>_s|) (next_state |<mod>_s|)) Bool (...))\n");
1313 log(" This function evaluates to 'true' if the states 'state' and\n");
1314 log(" 'next_state' form a valid state transition.\n");
1316 log(" (define-fun |<mod>_a| ((state |<mod>_s|)) Bool (...))\n");
1317 log(" This function evaluates to 'true' if all assertions hold in the state.\n");
1319 log(" (define-fun |<mod>_u| ((state |<mod>_s|)) Bool (...))\n");
1320 log(" This function evaluates to 'true' if all assumptions hold in the state.\n");
1322 log(" ; yosys-smt2-assert <id> <filename:linenum>\n");
1323 log(" (define-fun |<mod>_a <id>| ((state |<mod>_s|)) Bool (...))\n");
1324 log(" Each $assert cell is converted into one of this functions. The function\n");
1325 log(" evaluates to 'true' if the assert statement holds in the state.\n");
1327 log(" ; yosys-smt2-assume <id> <filename:linenum>\n");
1328 log(" (define-fun |<mod>_u <id>| ((state |<mod>_s|)) Bool (...))\n");
1329 log(" Each $assume cell is converted into one of this functions. The function\n");
1330 log(" evaluates to 'true' if the assume statement holds in the state.\n");
1332 log(" ; yosys-smt2-cover <id> <filename:linenum>\n");
1333 log(" (define-fun |<mod>_c <id>| ((state |<mod>_s|)) Bool (...))\n");
1334 log(" Each $cover cell is converted into one of this functions. The function\n");
1335 log(" evaluates to 'true' if the cover statement is activated in the state.\n");
1340 log(" this will print the recursive walk used to export the modules.\n");
1343 log(" Use a BitVec sort to represent a state instead of an uninterpreted\n");
1344 log(" sort. As a side-effect this will prevent use of arrays to model\n");
1345 log(" memories.\n");
1348 log(" Use SMT-LIB 2.6 style datatypes to represent a state instead of an\n");
1349 log(" uninterpreted sort.\n");
1352 log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
1353 log(" option multi-bit wires are represented using the BitVec sort and\n");
1354 log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
1357 log(" disable support for memories (via ArraysEx theory). this option is\n");
1358 log(" implied by -nobv. only $mem cells without merged registers in\n");
1359 log(" read ports are supported. call \"memory\" with -nordff to make sure\n");
1360 log(" that no registers are merged into $mem read ports. '<mod>_m' functions\n");
1361 log(" will be generated for accessing the arrays that are used to represent\n");
1362 log(" memories.\n");
1365 log(" create '<mod>_n' functions for all public wires. by default only ports,\n");
1366 log(" registers, and wires with the 'keep' attribute are exported.\n");
1368 log(" -tpl <template_file>\n");
1369 log(" use the given template file. the line containing only the token '%%%%'\n");
1370 log(" is replaced with the regular output of this command.\n");
1372 log("[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David\n");
1373 log("R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf\n");
1375 log("---------------------------------------------------------------------------\n");
1379 log("Consider the following module (test.v). We want to prove that the output can\n");
1380 log("never transition from a non-zero value to a zero value.\n");
1382 log(" module test(input clk, output reg [3:0] y);\n");
1383 log(" always @(posedge clk)\n");
1384 log(" y <= (y << 1) | ^y;\n");
1385 log(" endmodule\n");
1387 log("For this proof we create the following template (test.tpl).\n");
1389 log(" ; we need QF_UFBV for this poof\n");
1390 log(" (set-logic QF_UFBV)\n");
1392 log(" ; insert the auto-generated code here\n");
1395 log(" ; declare two state variables s1 and s2\n");
1396 log(" (declare-fun s1 () test_s)\n");
1397 log(" (declare-fun s2 () test_s)\n");
1399 log(" ; state s2 is the successor of state s1\n");
1400 log(" (assert (test_t s1 s2))\n");
1402 log(" ; we are looking for a model with y non-zero in s1\n");
1403 log(" (assert (distinct (|test_n y| s1) #b0000))\n");
1405 log(" ; we are looking for a model with y zero in s2\n");
1406 log(" (assert (= (|test_n y| s2) #b0000))\n");
1408 log(" ; is there such a model?\n");
1409 log(" (check-sat)\n");
1411 log("The following yosys script will create a 'test.smt2' file for our proof:\n");
1413 log(" read_verilog test.v\n");
1414 log(" hierarchy -check; proc; opt; check -assert\n");
1415 log(" write_smt2 -bv -tpl test.tpl test.smt2\n");
1417 log("Running 'cvc4 test.smt2' will print 'unsat' because y can never transition\n");
1418 log("from non-zero to zero in the test design.\n");
1421 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1423 std::ifstream template_f
;
1424 bool bvmode
= true, memmode
= true, wiresmode
= false, verbose
= false, statebv
= false, statedt
= false;
1425 bool forallmode
= false;
1427 log_header(design
, "Executing SMT2 backend.\n");
1430 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1432 if (args
[argidx
] == "-tpl" && argidx
+1 < args
.size()) {
1433 template_f
.open(args
[++argidx
]);
1434 if (template_f
.fail())
1435 log_error("Can't open template file `%s'.\n", args
[argidx
].c_str());
1438 if (args
[argidx
] == "-bv" || args
[argidx
] == "-mem") {
1439 log_warning("Options -bv and -mem are now the default. Support for -bv and -mem will be removed in the future.\n");
1442 if (args
[argidx
] == "-stbv") {
1447 if (args
[argidx
] == "-stdt") {
1452 if (args
[argidx
] == "-nobv") {
1457 if (args
[argidx
] == "-nomem") {
1461 if (args
[argidx
] == "-wires") {
1465 if (args
[argidx
] == "-verbose") {
1471 extra_args(f
, filename
, args
, argidx
);
1473 if (template_f
.is_open()) {
1475 while (std::getline(template_f
, line
)) {
1477 while (indent
< GetSize(line
) && (line
[indent
] == ' ' || line
[indent
] == '\t'))
1479 if (line
.substr(indent
, 2) == "%%")
1481 *f
<< line
<< std::endl
;
1485 *f
<< stringf("; SMT-LIBv2 description generated by %s\n", yosys_version_str
);
1488 *f
<< stringf("; yosys-smt2-nobv\n");
1491 *f
<< stringf("; yosys-smt2-nomem\n");
1494 *f
<< stringf("; yosys-smt2-stbv\n");
1497 *f
<< stringf("; yosys-smt2-stdt\n");
1499 std::vector
<RTLIL::Module
*> sorted_modules
;
1501 // extract module dependencies
1502 std::map
<RTLIL::Module
*, std::set
<RTLIL::Module
*>> module_deps
;
1503 for (auto &mod_it
: design
->modules_
) {
1504 module_deps
[mod_it
.second
] = std::set
<RTLIL::Module
*>();
1505 for (auto &cell_it
: mod_it
.second
->cells_
)
1506 if (design
->modules_
.count(cell_it
.second
->type
) > 0)
1507 module_deps
[mod_it
.second
].insert(design
->modules_
.at(cell_it
.second
->type
));
1510 // simple good-enough topological sort
1511 // (O(n*m) on n elements and depth m)
1512 while (module_deps
.size() > 0) {
1513 size_t sorted_modules_idx
= sorted_modules
.size();
1514 for (auto &it
: module_deps
) {
1515 for (auto &dep
: it
.second
)
1516 if (module_deps
.count(dep
) > 0)
1518 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
1519 sorted_modules
.push_back(it
.first
);
1522 if (sorted_modules_idx
== sorted_modules
.size())
1523 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps
.begin()->first
->name
));
1524 while (sorted_modules_idx
< sorted_modules
.size())
1525 module_deps
.erase(sorted_modules
.at(sorted_modules_idx
++));
1528 dict
<IdString
, int> mod_stbv_width
;
1529 dict
<IdString
, dict
<IdString
, pair
<bool, bool>>> mod_clk_cache
;
1530 Module
*topmod
= design
->top_module();
1531 std::string topmod_id
;
1533 for (auto module
: sorted_modules
)
1534 for (auto cell
: module
->cells())
1535 if (cell
->type
.in("$allconst", "$allseq"))
1540 *f
<< stringf("; yosys-smt2-forall\n");
1541 if (!statebv
&& !statedt
)
1542 log_error("Forall-exists problems are only supported in -stbv or -stdt mode.\n");
1545 for (auto module
: sorted_modules
)
1547 if (module
->get_blackbox_attribute() || module
->has_memories_warn() || module
->has_processes_warn())
1550 log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module
));
1552 Smt2Worker
worker(module
, bvmode
, memmode
, wiresmode
, verbose
, statebv
, statedt
, forallmode
, mod_stbv_width
, mod_clk_cache
);
1556 if (module
== topmod
)
1557 topmod_id
= worker
.get_id(module
);
1561 *f
<< stringf("; yosys-smt2-topmod %s\n", topmod_id
.c_str());
1563 *f
<< stringf("; end of yosys output\n");
1565 if (template_f
.is_open()) {
1567 while (std::getline(template_f
, line
))
1568 *f
<< line
<< std::endl
;
1573 PRIVATE_NAMESPACE_END