2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
28 PRIVATE_NAMESPACE_BEGIN
34 RTLIL::Module
*module
;
39 dict
<IdString
, shared_str
> idcache
;
40 pool
<shared_str
> used_names
;
41 vector
<shared_str
> strbuf
;
43 struct assign_rhs_chunk
{
46 bool operator<(const assign_rhs_chunk
&other
) const { return offset
< other
.offset
; }
49 dict
<Wire
*, vector
<assign_rhs_chunk
>> partial_assignments
;
50 vector
<string
> assignments
;
55 shared_str
s(stringf("_%d", idcounter
++));
56 if (!used_names
.count(s
)) {
63 const char *cid(IdString id
, bool precache
= false)
65 if (!idcache
.count(id
))
67 string name
= stringf("_%s", id
.c_str());
69 if (name
.substr(0, 2) == "_\\")
70 name
= "_" + name
.substr(2);
72 for (auto &c
: name
) {
73 if (c
== '|' || c
== '$' || c
== '_') continue;
74 if (c
>= 'a' && c
<='z') continue;
75 if (c
>= 'A' && c
<='Z') continue;
76 if (c
>= '0' && c
<='9') continue;
77 if (precache
) return nullptr;
84 while (used_names
.count(name
))
92 return idcache
.at(id
).c_str();
95 SmvWorker(RTLIL::Module
*module
, bool verbose
, std::ostream
&f
) :
96 ct(module
->design
), sigmap(module
), module(module
), f(f
), verbose(verbose
), idcounter(0)
98 for (auto mod
: module
->design
->modules())
101 for (auto wire
: module
->wires())
102 cid(wire
->name
, true);
104 for (auto cell
: module
->cells()) {
105 cid(cell
->name
, true);
106 cid(cell
->type
, true);
107 for (auto &conn
: cell
->connections())
108 cid(conn
.first
, true);
112 const char *rvalue(SigSpec sig
, bool skip_sigmap
= false, int width
= -1, bool is_signed
= false)
118 int count_chunks
= 0;
119 for (auto &c
: sig
.chunks()) {
124 if (c
.offset
!= 0 || c
.width
!= c
.wire
->width
)
125 s
= stringf("%s[%d:%d]", cid(c
.wire
->name
), c
.offset
+c
.width
-1, c
.offset
) + s
;
127 s
= cid(c
.wire
->name
) + s
;
129 string v
= stringf("0ub%d_", c
.width
);
130 for (int i
= c
.width
-1; i
>= 0; i
--)
131 v
+= c
.data
.at(i
) == State::S1
? '1' : '0';
138 if (GetSize(sig
) > width
)
139 s
= stringf("signed(resize(%s, %d))", s
.c_str(), width
);
141 s
= stringf("resize(signed(%s), %d)", s
.c_str(), width
);
143 s
= stringf("resize(%s, %d)", s
.c_str(), width
);
144 } else if (is_signed
)
145 s
= stringf("signed(%s)", s
.c_str());
146 else if (count_chunks
> 1)
147 s
= stringf("(%s)", s
.c_str());
150 return strbuf
.back().c_str();
153 const char *rvalue_u(SigSpec sig
, int width
= -1)
155 return rvalue(sig
, false, width
, false);
158 const char *rvalue_s(SigSpec sig
, int width
= -1, bool is_signed
= true)
160 return rvalue(sig
, false, width
, is_signed
);
163 const char *lvalue(SigSpec sig
, bool skip_sigmap
= false)
169 return rvalue(sig
, true);
171 const char *temp_id
= cid();
172 f
<< stringf(" %s : unsigned word[%d]; -- %s\n", temp_id
, GetSize(sig
), log_signal(sig
));
175 for (auto &c
: sig
.chunks())
177 log_assert(c
.wire
!= nullptr);
179 assign_rhs_chunk rhs
;
180 if (offset
!= 0 || c
.width
!= GetSize(sig
))
181 rhs
.rhs_expr
= stringf("%s[%d:%d]", temp_id
, offset
+c
.width
-1, offset
);
183 rhs
.rhs_expr
= temp_id
;
184 rhs
.offset
= c
.offset
;
187 partial_assignments
[c
.wire
].push_back(rhs
);
196 f
<< stringf("MODULE %s\n", cid(module
->name
));
197 f
<< stringf(" VAR\n");
199 for (auto wire
: module
->wires())
201 SigSpec this_sig
= wire
, driver_sig
= sigmap(wire
);
202 SigSpec unused_bits_in_this_sig
;
203 SigSpec driver_for_unused_bits
;
205 for (int i
= 0; i
< GetSize(this_sig
); i
++)
206 if (this_sig
[i
] != driver_sig
[i
]) {
207 unused_bits_in_this_sig
.append(this_sig
[i
]);
208 driver_for_unused_bits
.append(driver_sig
[i
]);
211 if (GetSize(unused_bits_in_this_sig
) == GetSize(this_sig
))
213 f
<< stringf(" -- unused -- %s : unsigned word[%d]; -- %s\n", cid(wire
->name
), wire
->width
, log_id(wire
));
217 f
<< stringf(" %s : unsigned word[%d]; -- %s\n", cid(wire
->name
), wire
->width
, log_id(wire
));
219 if (!unused_bits_in_this_sig
.empty())
220 assignments
.push_back(stringf("%s := 0ub%d_0; -- unused %s -- using %s instead", lvalue(unused_bits_in_this_sig
, true),
221 GetSize(unused_bits_in_this_sig
), log_signal(unused_bits_in_this_sig
), log_signal(driver_for_unused_bits
)));
225 for (auto cell
: module
->cells())
227 // FIXME: $slice, $concat, $mem
229 if (cell
->type
.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
231 SigSpec sig_a
= cell
->getPort("\\A");
232 SigSpec sig_b
= cell
->getPort("\\B");
234 int width_y
= GetSize(cell
->getPort("\\Y"));
235 int shift_b_width
= GetSize(sig_b
);
236 int width_ay
= std::max(GetSize(sig_a
), width_y
);
237 int width
= width_ay
;
239 for (int i
= 1, j
= 0;; i
<<= 1, j
++)
242 shift_b_width
= std::min(shift_b_width
, j
);
246 bool signed_a
= cell
->getParam("\\A_SIGNED").as_bool();
247 bool signed_b
= cell
->getParam("\\B_SIGNED").as_bool();
248 string op
= cell
->type
.in("$shl", "$sshl") ? "<<" : ">>";
251 if (cell
->type
== "$sshr" && signed_a
)
253 expr_a
= rvalue_s(sig_a
, width
);
254 expr
= stringf("resize(unsigned(%s %s %s), %d)", expr_a
.c_str(), op
.c_str(), rvalue(sig_b
.extract(0, shift_b_width
)), width_y
);
255 if (shift_b_width
< GetSize(sig_b
))
256 expr
= stringf("%s != 0ud%d_0 ? (bool(%s) ? !0ud%d_0 : 0ud%d_0) : %s",
257 rvalue(sig_b
.extract(shift_b_width
, GetSize(sig_b
) - shift_b_width
)), GetSize(sig_b
) - shift_b_width
,
258 rvalue(sig_a
[GetSize(sig_a
)-1]), width_y
, width_y
, expr
.c_str());
260 else if (cell
->type
.in("$shift", "$shiftx") && signed_b
)
262 expr_a
= rvalue_u(sig_a
, width
);
264 const char *b_shr
= rvalue_u(sig_b
);
265 const char *b_shl
= cid();
267 f
<< stringf(" %s : unsigned word[%d]; -- neg(%s)\n", b_shl
, GetSize(sig_b
), log_signal(sig_b
));
268 assignments
.push_back(stringf("%s := unsigned(-%s);", b_shl
, rvalue_s(sig_b
)));
270 string expr_shl
= stringf("resize(%s << %s[%d:0], %d)", expr_a
.c_str(), b_shl
, shift_b_width
-1, width_y
);
271 string expr_shr
= stringf("resize(%s >> %s[%d:0], %d)", expr_a
.c_str(), b_shr
, shift_b_width
-1, width_y
);
273 if (shift_b_width
< GetSize(sig_b
)) {
274 expr_shl
= stringf("%s[%d:%d] != 0ud%d_0 ? 0ud%d_0 : %s", b_shl
, GetSize(sig_b
)-1, shift_b_width
,
275 GetSize(sig_b
)-shift_b_width
, width_y
, expr_shl
.c_str());
276 expr_shr
= stringf("%s[%d:%d] != 0ud%d_0 ? 0ud%d_0 : %s", b_shr
, GetSize(sig_b
)-1, shift_b_width
,
277 GetSize(sig_b
)-shift_b_width
, width_y
, expr_shr
.c_str());
280 expr
= stringf("bool(%s) ? %s : %s", rvalue(sig_b
[GetSize(sig_b
)-1]), expr_shl
.c_str(), expr_shr
.c_str());
284 if (cell
->type
.in("$shift", "$shiftx") || !signed_a
)
285 expr_a
= rvalue_u(sig_a
, width
);
287 expr_a
= stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a
, width_ay
), width
);
289 expr
= stringf("resize(%s %s %s[%d:0], %d)", expr_a
.c_str(), op
.c_str(), rvalue_u(sig_b
), shift_b_width
-1, width_y
);
290 if (shift_b_width
< GetSize(sig_b
))
291 expr
= stringf("%s[%d:%d] != 0ud%d_0 ? 0ud%d_0 : %s", rvalue_u(sig_b
), GetSize(sig_b
)-1, shift_b_width
,
292 GetSize(sig_b
)-shift_b_width
, width_y
, expr
.c_str());
295 assignments
.push_back(stringf("%s := %s;", lvalue(cell
->getPort("\\Y")), expr
.c_str()));
300 if (cell
->type
.in("$not", "$pos", "$neg"))
302 int width
= GetSize(cell
->getPort("\\Y"));
305 if (cell
->type
== "$not") op
= "!";
306 if (cell
->type
== "$pos") op
= "";
307 if (cell
->type
== "$neg") op
= "-";
309 if (cell
->getParam("\\A_SIGNED").as_bool())
311 assignments
.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell
->getPort("\\Y")),
312 op
.c_str(), rvalue_s(cell
->getPort("\\A"), width
)));
316 assignments
.push_back(stringf("%s := %s%s;", lvalue(cell
->getPort("\\Y")),
317 op
.c_str(), rvalue_u(cell
->getPort("\\A"), width
)));
323 if (cell
->type
.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor"))
325 int width
= GetSize(cell
->getPort("\\Y"));
326 string expr_a
, expr_b
, op
;
328 if (cell
->type
== "$add") op
= "+";
329 if (cell
->type
== "$sub") op
= "-";
330 if (cell
->type
== "$mul") op
= "*";
331 if (cell
->type
== "$and") op
= "&";
332 if (cell
->type
== "$or") op
= "|";
333 if (cell
->type
== "$xor") op
= "xor";
334 if (cell
->type
== "$xnor") op
= "xnor";
336 if (cell
->getParam("\\A_SIGNED").as_bool())
338 assignments
.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell
->getPort("\\Y")),
339 rvalue_s(cell
->getPort("\\A"), width
), op
.c_str(), rvalue_s(cell
->getPort("\\B"), width
)));
343 assignments
.push_back(stringf("%s := %s %s %s;", lvalue(cell
->getPort("\\Y")),
344 rvalue_u(cell
->getPort("\\A"), width
), op
.c_str(), rvalue_u(cell
->getPort("\\B"), width
)));
350 if (cell
->type
.in("$div", "$mod"))
352 int width_y
= GetSize(cell
->getPort("\\Y"));
353 int width
= std::max(width_y
, GetSize(cell
->getPort("\\A")));
354 width
= std::max(width
, GetSize(cell
->getPort("\\B")));
355 string expr_a
, expr_b
, op
;
357 if (cell
->type
== "$div") op
= "/";
358 if (cell
->type
== "$mod") op
= "mod";
360 if (cell
->getParam("\\A_SIGNED").as_bool())
362 assignments
.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell
->getPort("\\Y")),
363 rvalue_s(cell
->getPort("\\A"), width
), op
.c_str(), rvalue_s(cell
->getPort("\\B"), width
), width_y
));
367 assignments
.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell
->getPort("\\Y")),
368 rvalue_u(cell
->getPort("\\A"), width
), op
.c_str(), rvalue_u(cell
->getPort("\\B"), width
), width_y
));
374 if (cell
->type
.in("$eq", "$ne", "$eqx", "$nex", "$lt", "$le", "$ge", "$gt"))
376 int width
= std::max(GetSize(cell
->getPort("\\A")), GetSize(cell
->getPort("\\B")));
377 string expr_a
, expr_b
, op
;
379 if (cell
->type
== "$eq") op
= "=";
380 if (cell
->type
== "$ne") op
= "!=";
381 if (cell
->type
== "$eqx") op
= "=";
382 if (cell
->type
== "$nex") op
= "!=";
383 if (cell
->type
== "$lt") op
= "<";
384 if (cell
->type
== "$le") op
= "<=";
385 if (cell
->type
== "$ge") op
= ">=";
386 if (cell
->type
== "$gt") op
= ">";
388 if (cell
->getParam("\\A_SIGNED").as_bool())
390 expr_a
= stringf("resize(signed(%s), %d)", rvalue(cell
->getPort("\\A")), width
);
391 expr_b
= stringf("resize(signed(%s), %d)", rvalue(cell
->getPort("\\B")), width
);
395 expr_a
= stringf("resize(%s, %d)", rvalue(cell
->getPort("\\A")), width
);
396 expr_b
= stringf("resize(%s, %d)", rvalue(cell
->getPort("\\B")), width
);
399 assignments
.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell
->getPort("\\Y")),
400 expr_a
.c_str(), op
.c_str(), expr_b
.c_str(), GetSize(cell
->getPort("\\Y"))));
405 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_bool"))
407 int width_a
= GetSize(cell
->getPort("\\A"));
408 int width_y
= GetSize(cell
->getPort("\\Y"));
409 const char *expr_a
= rvalue(cell
->getPort("\\A"));
410 const char *expr_y
= lvalue(cell
->getPort("\\Y"));
413 if (cell
->type
== "$reduce_and") expr
= stringf("%s = !0ub%d_0", expr_a
, width_a
);
414 if (cell
->type
== "$reduce_or") expr
= stringf("%s != 0ub%d_0", expr_a
, width_a
);
415 if (cell
->type
== "$reduce_bool") expr
= stringf("%s != 0ub%d_0", expr_a
, width_a
);
417 assignments
.push_back(stringf("%s := resize(word1(%s), %d);", expr_y
, expr
.c_str(), width_y
));
421 if (cell
->type
.in("$reduce_xor", "$reduce_xnor"))
423 int width_y
= GetSize(cell
->getPort("\\Y"));
424 const char *expr_y
= lvalue(cell
->getPort("\\Y"));
427 for (auto bit
: cell
->getPort("\\A")) {
433 if (cell
->type
== "$reduce_xnor")
434 expr
= "!(" + expr
+ ")";
436 assignments
.push_back(stringf("%s := resize(%s, %d);", expr_y
, expr
.c_str(), width_y
));
440 if (cell
->type
.in("$logic_and", "$logic_or"))
442 int width_a
= GetSize(cell
->getPort("\\A"));
443 int width_b
= GetSize(cell
->getPort("\\B"));
444 int width_y
= GetSize(cell
->getPort("\\Y"));
446 string expr_a
= stringf("(%s != 0ub%d_0)", rvalue(cell
->getPort("\\A")), width_a
);
447 string expr_b
= stringf("(%s != 0ub%d_0)", rvalue(cell
->getPort("\\B")), width_b
);
448 const char *expr_y
= lvalue(cell
->getPort("\\Y"));
451 if (cell
->type
== "$logic_and") expr
= expr_a
+ " & " + expr_b
;
452 if (cell
->type
== "$logic_or") expr
= expr_a
+ " | " + expr_b
;
454 assignments
.push_back(stringf("%s := resize(word1(%s), %d);", expr_y
, expr
.c_str(), width_y
));
458 if (cell
->type
.in("$logic_not"))
460 int width_a
= GetSize(cell
->getPort("\\A"));
461 int width_y
= GetSize(cell
->getPort("\\Y"));
463 string expr_a
= stringf("(%s = 0ub%d_0)", rvalue(cell
->getPort("\\A")), width_a
);
464 const char *expr_y
= lvalue(cell
->getPort("\\Y"));
466 assignments
.push_back(stringf("%s := resize(word1(%s), %d);", expr_y
, expr_a
.c_str(), width_y
));
470 if (cell
->type
.in("$mux", "$pmux"))
472 int width
= GetSize(cell
->getPort("\\Y"));
473 SigSpec sig_a
= cell
->getPort("\\A");
474 SigSpec sig_b
= cell
->getPort("\\B");
475 SigSpec sig_s
= cell
->getPort("\\S");
478 for (int i
= 0; i
< GetSize(sig_s
); i
++)
479 expr
+= stringf("bool(%s) ? %s : ", rvalue(sig_s
[i
]), rvalue(sig_b
.extract(i
*width
, width
)));
480 expr
+= rvalue(sig_a
);
482 assignments
.push_back(stringf("%s := %s;", lvalue(cell
->getPort("\\Y")), expr
.c_str()));
486 if (cell
->type
== "$dff")
488 // FIXME: use init property
489 assignments
.push_back(stringf("next(%s) := %s;", lvalue(cell
->getPort("\\Q")), rvalue(cell
->getPort("\\D"))));
493 if (cell
->type
.in("$_BUF_", "$_NOT_"))
495 string op
= cell
->type
== "$_NOT_" ? "!" : "";
496 assignments
.push_back(stringf("%s := %s%s;", lvalue(cell
->getPort("\\Y")), op
.c_str(), rvalue(cell
->getPort("\\A"))));
500 if (cell
->type
.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
504 if (cell
->type
.in("$_AND_", "$_NAND_")) op
= "&";
505 if (cell
->type
.in("$_OR_", "$_NOR_")) op
= "|";
506 if (cell
->type
.in("$_XOR_")) op
= "xor";
507 if (cell
->type
.in("$_XNOR_")) op
= "xnor";
509 if (cell
->type
.in("$_NAND_", "$_NOR_"))
510 assignments
.push_back(stringf("%s := !(%s %s %s);", lvalue(cell
->getPort("\\Y")),
511 rvalue(cell
->getPort("\\A")), op
.c_str(), rvalue(cell
->getPort("\\B"))));
513 assignments
.push_back(stringf("%s := %s %s %s;", lvalue(cell
->getPort("\\Y")),
514 rvalue(cell
->getPort("\\A")), op
.c_str(), rvalue(cell
->getPort("\\B"))));
518 if (cell
->type
== "$_MUX_")
520 assignments
.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell
->getPort("\\Y")),
521 rvalue(cell
->getPort("\\S")), rvalue(cell
->getPort("\\B")), rvalue(cell
->getPort("\\A"))));
525 if (cell
->type
== "$_AOI3_")
527 assignments
.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell
->getPort("\\Y")),
528 rvalue(cell
->getPort("\\A")), rvalue(cell
->getPort("\\B")), rvalue(cell
->getPort("\\C"))));
532 if (cell
->type
== "$_OAI3_")
534 assignments
.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell
->getPort("\\Y")),
535 rvalue(cell
->getPort("\\A")), rvalue(cell
->getPort("\\B")), rvalue(cell
->getPort("\\C"))));
539 if (cell
->type
== "$_AOI4_")
541 assignments
.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell
->getPort("\\Y")),
542 rvalue(cell
->getPort("\\A")), rvalue(cell
->getPort("\\B")), rvalue(cell
->getPort("\\C")), rvalue(cell
->getPort("\\D"))));
546 if (cell
->type
== "$_OAI4_")
548 assignments
.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell
->getPort("\\Y")),
549 rvalue(cell
->getPort("\\A")), rvalue(cell
->getPort("\\B")), rvalue(cell
->getPort("\\C")), rvalue(cell
->getPort("\\D"))));
553 if (cell
->type
[0] == '$')
554 log_error("Found currently unsupported cell type %s (%s.%s).\n", log_id(cell
->type
), log_id(module
), log_id(cell
));
556 f
<< stringf(" %s : %s;\n", cid(cell
->name
), cid(cell
->type
));
558 for (auto &conn
: cell
->connections())
559 if (cell
->output(conn
.first
))
560 assignments
.push_back(stringf("%s := %s.%s;", lvalue(conn
.second
), cid(cell
->name
), cid(conn
.first
)));
562 assignments
.push_back(stringf("%s.%s := %s;", cid(cell
->name
), cid(conn
.first
), rvalue(conn
.second
)));
565 for (auto &it
: partial_assignments
)
567 std::sort(it
.second
.begin(), it
.second
.end());
571 for (auto rhs
: it
.second
) {
573 expr
= " :: " + expr
;
574 if (offset
< rhs
.offset
)
575 expr
= stringf(" :: 0ub%d_0 ", rhs
.offset
- offset
) + expr
;
576 expr
= rhs
.rhs_expr
+ expr
;
577 offset
= rhs
.offset
+ rhs
.width
;
579 if (offset
< it
.first
->width
)
580 expr
= stringf("0ub%d_0 :: ", it
.first
->width
- offset
) + expr
;
581 assignments
.push_back(stringf("%s := %s;", cid(it
.first
->name
), expr
.c_str()));
584 f
<< stringf(" ASSIGN\n");
585 for (const string
&line
: assignments
)
586 f
<< stringf(" %s\n", line
.c_str());
590 struct SmvBackend
: public Backend
{
591 SmvBackend() : Backend("smv", "write design to SMV file") { }
594 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
596 log(" write_smv [options] [filename]\n");
598 log("Write an SMV description of the current design.\n");
601 log(" this will print the recursive walk used to export the modules.\n");
603 log(" -tpl <template_file>\n");
604 log(" use the given template file. the line containing only the token '%%%%'\n");
605 log(" is replaced with the regular output of this command.\n");
607 log("THIS COMMAND IS UNDER CONSTRUCTION\n");
610 virtual void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
)
612 std::ifstream template_f
;
613 bool verbose
= false;
615 log_header("Executing SMV backend.\n");
618 for (argidx
= 1; argidx
< args
.size(); argidx
++)
620 if (args
[argidx
] == "-tpl" && argidx
+1 < args
.size()) {
621 template_f
.open(args
[++argidx
]);
622 if (template_f
.fail())
623 log_error("Can't open template file `%s'.\n", args
[argidx
].c_str());
626 if (args
[argidx
] == "-verbose") {
632 extra_args(f
, filename
, args
, argidx
);
634 pool
<Module
*> modules
;
636 for (auto module
: design
->modules())
637 if (!module
->get_bool_attribute("\\blackbox") && !module
->has_memories_warn() && !module
->has_processes_warn())
638 modules
.insert(module
);
640 if (template_f
.is_open())
643 while (std::getline(template_f
, line
))
646 while (indent
< GetSize(line
) && (line
[indent
] == ' ' || line
[indent
] == '\t'))
649 if (line
[indent
] == '%')
651 vector
<string
> stmt
= split_tokens(line
);
653 if (GetSize(stmt
) == 1 && stmt
[0] == "%%")
656 if (GetSize(stmt
) == 2 && stmt
[0] == "%module")
658 Module
*module
= design
->module(RTLIL::escape_id(stmt
[1]));
659 modules
.erase(module
);
661 if (module
== nullptr)
662 log_error("Module '%s' not found.\n", stmt
[1].c_str());
664 *f
<< stringf("-- SMV description generated by %s\n", yosys_version_str
);
666 log("Creating SMV representation of module %s.\n", log_id(module
));
667 SmvWorker
worker(module
, verbose
, *f
);
670 *f
<< stringf("-- end of yosys output\n");
674 log_error("Unknown template statement: '%s'", line
.c_str() + indent
);
677 *f
<< line
<< std::endl
;
681 if (!modules
.empty())
683 *f
<< stringf("-- SMV description generated by %s\n", yosys_version_str
);
685 for (auto module
: modules
) {
686 log("Creating SMV representation of module %s.\n", log_id(module
));
687 SmvWorker
worker(module
, verbose
, *f
);
691 *f
<< stringf("-- end of yosys output\n");
694 if (template_f
.is_open()) {
696 while (std::getline(template_f
, line
))
697 *f
<< line
<< std::endl
;
702 PRIVATE_NAMESPACE_END