backends/spice/spice.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/rtlil.h"
  21 #include "kernel/register.h"
  22 #include "kernel/sigtools.h"
  23 #include "kernel/celltypes.h"
  24 #include "kernel/log.h"
  25 #include <string>
  26
  27 USING_YOSYS_NAMESPACE
  28 PRIVATE_NAMESPACE_BEGIN
  29
  30 static string spice_id2str(IdString id)
  31 {
  32         static const char *escape_chars = "$\\[]()<>=";
  33         string s = RTLIL::unescape_id(id);
  34
  35         for (auto &ch : s)
  36                 if (strchr(escape_chars, ch) != nullptr) ch = '_';
  37
  38         return s;
  39 }
  40
  41 static string spice_id2str(IdString id, bool use_inames, idict<IdString, 1> &inums)
  42 {
  43         if (!use_inames && *id.c_str() == '$')
  44                 return stringf("%d", inums(id));
  45         return spice_id2str(id);
  46 }
  47
  48 static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter, bool use_inames, idict<IdString, 1> &inums)
  49 {
  50         if (s.wire) {
  51                 if (s.wire->port_id)
  52                         use_inames = true;
  53                 if (s.wire->width > 1)
  54                         f << stringf(" %s.%d", spice_id2str(s.wire->name, use_inames, inums).c_str(), s.offset);
  55                 else
  56                         f << stringf(" %s", spice_id2str(s.wire->name, use_inames, inums).c_str());
  57         } else {
  58                 if (s == RTLIL::State::S0)
  59                         f << stringf(" %s", neg.c_str());
  60                 else if (s == RTLIL::State::S1)
  61                         f << stringf(" %s", pos.c_str());
  62                 else
  63                         f << stringf(" %s%d", ncpf.c_str(), nc_counter++);
  64         }
  65 }
  66
  67 static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian, bool use_inames)
  68 {
  69         SigMap sigmap(module);
  70         idict<IdString, 1> inums;
  71         int cell_counter = 0, conn_counter = 0, nc_counter = 0;
  72
  73         for (auto &cell_it : module->cells_)
  74         {
  75                 RTLIL::Cell *cell = cell_it.second;
  76                 f << stringf("X%d", cell_counter++);
  77
  78                 std::vector<RTLIL::SigSpec> port_sigs;
  79
  80                 if (design->modules_.count(cell->type) == 0)
  81                 {
  82                         log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
  83                                         log_id(cell->type), log_id(module), log_id(cell));
  84                         for (auto &conn : cell->connections()) {
  85                                 RTLIL::SigSpec sig = sigmap(conn.second);
  86                                 port_sigs.push_back(sig);
  87                         }
  88                 }
  89                 else
  90                 {
  91                         RTLIL::Module *mod = design->modules_.at(cell->type);
  92
  93                         std::vector<RTLIL::Wire*> ports;
  94                         for (auto wire_it : mod->wires_) {
  95                                 RTLIL::Wire *wire = wire_it.second;
  96                                 if (wire->port_id == 0)
  97                                         continue;
  98                                 while (int(ports.size()) < wire->port_id)
  99                                         ports.push_back(NULL);
 100                                 ports.at(wire->port_id-1) = wire;
 101                         }
 102
 103                         for (RTLIL::Wire *wire : ports) {
 104                                 log_assert(wire != NULL);
 105                                 RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
 106                                 if (cell->hasPort(wire->name)) {
 107                                         sig = sigmap(cell->getPort(wire->name));
 108                                         sig.extend_u0(wire->width, false);
 109                                 }
 110                                 port_sigs.push_back(sig);
 111                         }
 112                 }
 113
 114                 for (auto &sig : port_sigs) {
 115                         for (int i = 0; i < sig.size(); i++) {
 116                                 RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1);
 117                                 print_spice_net(f, s, neg, pos, ncpf, nc_counter, use_inames, inums);
 118                         }
 119                 }
 120
 121                 f << stringf(" %s\n", spice_id2str(cell->type).c_str());
 122         }
 123
 124         for (auto &conn : module->connections())
 125         for (int i = 0; i < conn.first.size(); i++) {
 126                 f << stringf("V%d", conn_counter++);
 127                 print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter, use_inames, inums);
 128                 print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter, use_inames, inums);
 129                 f << stringf(" DC 0\n");
 130         }
 131 }
 132
 133 struct SpiceBackend : public Backend {
 134         SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { }
 135         void help() YS_OVERRIDE
 136         {
 137                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 138                 log("\n");
 139                 log("    write_spice [options] [filename]\n");
 140                 log("\n");
 141                 log("Write the current design to an SPICE netlist file.\n");
 142                 log("\n");
 143                 log("    -big_endian\n");
 144                 log("        generate multi-bit ports in MSB first order\n");
 145                 log("        (default is LSB first)\n");
 146                 log("\n");
 147                 log("    -neg net_name\n");
 148                 log("        set the net name for constant 0 (default: Vss)\n");
 149                 log("\n");
 150                 log("    -pos net_name\n");
 151                 log("        set the net name for constant 1 (default: Vdd)\n");
 152                 log("\n");
 153                 log("    -nc_prefix\n");
 154                 log("        prefix for not-connected nets (default: _NC)\n");
 155                 log("\n");
 156                 log("    -inames\n");
 157                 log("        include names of internal ($-prefixed) nets in outputs\n");
 158                 log("        (default is to use net numbers instead)\n");
 159                 log("\n");
 160                 log("    -top top_module\n");
 161                 log("        set the specified module as design top module\n");
 162                 log("\n");
 163         }
 164         void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 165         {
 166                 std::string top_module_name;
 167                 RTLIL::Module *top_module = NULL;
 168                 bool big_endian = false, use_inames = false;
 169                 std::string neg = "Vss", pos = "Vdd", ncpf = "_NC";
 170
 171                 log_header(design, "Executing SPICE backend.\n");
 172
 173                 size_t argidx;
 174                 for (argidx = 1; argidx < args.size(); argidx++)
 175                 {
 176                         if (args[argidx] == "-big_endian") {
 177                                 big_endian = true;
 178                                 continue;
 179                         }
 180                         if (args[argidx] == "-inames") {
 181                                 use_inames = true;
 182                                 continue;
 183                         }
 184                         if (args[argidx] == "-neg" && argidx+1 < args.size()) {
 185                                 neg = args[++argidx];
 186                                 continue;
 187                         }
 188                         if (args[argidx] == "-pos" && argidx+1 < args.size()) {
 189                                 pos = args[++argidx];
 190                                 continue;
 191                         }
 192                         if (args[argidx] == "-nc_prefix" && argidx+1 < args.size()) {
 193                                 ncpf = args[++argidx];
 194                                 continue;
 195                         }
 196                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 197                                 top_module_name = args[++argidx];
 198                                 continue;
 199                         }
 200                         break;
 201                 }
 202                 extra_args(f, filename, args, argidx);
 203
 204                 if (top_module_name.empty())
 205                         for (auto & mod_it:design->modules_)
 206                                 if (mod_it.second->get_bool_attribute("\\top"))
 207                                         top_module_name = mod_it.first.str();
 208
 209                 *f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
 210                 *f << stringf("\n");
 211
 212                 for (auto module_it : design->modules_)
 213                 {
 214                         RTLIL::Module *module = module_it.second;
 215                         if (module->get_blackbox_attribute())
 216                                 continue;
 217
 218                         if (module->processes.size() != 0)
 219                                 log_error("Found unmapped processes in module %s: unmapped processes are not supported in SPICE backend!\n", log_id(module));
 220                         if (module->memories.size() != 0)
 221                                 log_error("Found unmapped memories in module %s: unmapped memories are not supported in SPICE backend!\n", log_id(module));
 222
 223                         if (module->name == RTLIL::escape_id(top_module_name)) {
 224                                 top_module = module;
 225                                 continue;
 226                         }
 227
 228                         std::vector<RTLIL::Wire*> ports;
 229                         for (auto wire_it : module->wires_) {
 230                                 RTLIL::Wire *wire = wire_it.second;
 231                                 if (wire->port_id == 0)
 232                                         continue;
 233                                 while (int(ports.size()) < wire->port_id)
 234                                         ports.push_back(NULL);
 235                                 ports.at(wire->port_id-1) = wire;
 236                         }
 237
 238                         *f << stringf(".SUBCKT %s", spice_id2str(module->name).c_str());
 239                         for (RTLIL::Wire *wire : ports) {
 240                                 log_assert(wire != NULL);
 241                                 if (wire->width > 1) {
 242                                         for (int i = 0; i < wire->width; i++)
 243                                                 *f << stringf(" %s.%d", spice_id2str(wire->name).c_str(), big_endian ? wire->width - 1 - i : i);
 244                                 } else
 245                                         *f << stringf(" %s", spice_id2str(wire->name).c_str());
 246                         }
 247                         *f << stringf("\n");
 248                         print_spice_module(*f, module, design, neg, pos, ncpf, big_endian, use_inames);
 249                         *f << stringf(".ENDS %s\n\n", spice_id2str(module->name).c_str());
 250                 }
 251
 252                 if (!top_module_name.empty()) {
 253                         if (top_module == NULL)
 254                                 log_error("Can't find top module `%s'!\n", top_module_name.c_str());
 255                         print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian, use_inames);
 256                         *f << stringf("\n");
 257                 }
 258
 259                 *f << stringf("************************\n");
 260                 *f << stringf("* end of SPICE netlist *\n");
 261                 *f << stringf("************************\n");
 262                 *f << stringf("\n");
 263         }
 264 } SpiceBackend;
 265
 266 PRIVATE_NAMESPACE_END